la verificacion de sistemas digitales

Verificacin de Sistemas Digitales

Hctor Sucar

Alejandro Moreno

Maestra en Diseo de Circuitos Integrados

ITESO

1. Intro to Verification

Verificacion de Sistemas Digitales - Maestra en Diseo de Circuitos Integrados - ITESO 3

Development flow

Device specification System requirements, external interface, architecture

Verification framework (test bench)

Micro-architecture specification Design hierarchy and interfaces

Reference model

Verification plan, functional coverage

Functional implementation RTL model

Verification checkers

RTL verification vs reference model

Coverage evaluation

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Development flow (cont.) Structural design

Logic synthesis, timing constraints Full custom circuits (analog) Gate-level model (unit delay) Gate-level verification pre-SDF (mixed with RTL) Mixed signal verification

Physical design and tape-out Layout (synthesis & full custom) Layout integration and LVS/DRC Formal verification Gate-level verification post-SDF (timing back-annotation)

Fabrication Mask generation Wafer fabrication and packaging Test generation (BIST, ATPG) Fault grading

Verificacion de Sistemas Digitales - Maestra en Diseo de Circuitos Integrados - ITESO

*Standard Delay Format *Register Transfer Level

*Layout vs. Schematic Verification *Design Rules Checking

*Built-in Self-Test *Automatic Test Pattern Generation

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What is Verification?

To prove equivalence

To check/compare the expected or correct result

To find errors in the result

You are always verifying:

When you are shopping a good wine

When you are driving a car

Always


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What is Hardware Verification?

The process to determine that an implementation behaves according to a given set of requirements

(Spec) for all possible scenarios

Hardware Verification = Correctness and Completeness

Spec Implementation

VERIFICATION

DESIGN


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Verification vs. Validation

Verify

To prove that the implementation is a correct functional representation of its specification.

Validate

To prove that the implementation is a correct physical representation of its specification.


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Verification vs. Testing

Spec RTL/Netlist

Verification

Silicon

Testing

HW Design Manufacturing

Verification Proves the pre-silicon design

(implementation errors)

Testing Proves the post-silicon design

(manufacturing defects)


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Common Errors

Specification Errors: Ambiguous requirements

Interpretation: Human factor

Logic Bugs: Typical design bugs

Timing: Clock Hierarchy, Delays

Corner cases: Max/Min Values

Environment: Testbench


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The Importance of Verification

Pre-Silicon Post-Silicon

Pre-Production Post-Production

Why Verification is important? R. Quality and Cost

If you find a bug in pre-silicon verification,

the cost is almost free, also it reduces the TTM

Low Cost Bugs are more costly Very Expensive


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The Importance of Verification (cont.)

Development effort

Verification consumes about 70% of the development effort, it involves: planning, environment, simulations, debug, and many loops.

Critical path

Verification increases or decreases TTM, and it impacts cost significantly.


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Verification time can be reduced:

Parallelism: Human and Computing tasks.

Object Oriented Verification: Abstraction, Encapsulation, Modularity, Polymorphism, Inheritance.

Automation: Automation lets you do something else while a machine completes a task autonomously, faster and with predictable results. It eliminates human factor.


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Randomization: By constraining a random generator to produce valid inputs within the bounds of a particular domain, it is possible to automatically produce almost all of the interesting conditions.

Functional Coverage: Automate tests to cover functionality is better than specific testcases. FC identifies the circuit blocks that were not exercised by analysis of simulation with random stimulus.


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Types of Hardware Verification

Structural Verification or Formal Verification Proves the equivalence between two different representations or models using formal methods.

Examples: Property Checking (Assertions), Equivalence Checking (Synthesizable Model), or Model Checking.

Functional Verification Proves the equivalence between two representations or models, Reference Model and Functional Model -RTL- using simulation tools.


The course will be focused on Functional Verification

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Functional Verification

The FV process is based on two principles:

Controllability - Ability of internal/external inputs to move the model from any initial state to any other state: Stimuli

Observability - Ability of internal/external outputs to get the current state of the model for analysis: Responses


Functional Models

RTL/RM

Controllability

Stimuli

Observability

Response

What is a stimulus? What is a response? How do you usually perform this process?

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Paradigms and Challenges

Verification Problem: what we are really verifying?

Verification Scope: when we really finish the verification?

Design for Verification: what verifies our verification environment?

Interpretation: which interpretation is the best?

Human Factor: Human errors are always present

Mixed-Signal Verification: how to mix analog and digital verification?

Object Oriented Verification : how to use HVL and OOP?


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State of the Art

Techniques: Automation, Coverage-Driven, Assertion-Based

Languages: SystemVerilog, e-Laguage, SystemC.

Tools:

QuestaSim Mentor (evolution of ModelSim)

Specman Cadence

VCS Synopsys

VCS-NanoSim Synopsys (Mixed-Signal)

Methodologies: Based on Object Oriented, Layers, AVM/OVM/UVM (Mentor/Cadence), VMM (Synopsys).


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Conclusions

Hardware Verification is the process to prove that an implementation behaves according to the specification for all possible scenarios.

Verification is the measure of quality of the product. Verification time can be reduced through: Parallelism, Abstraction, Automation, Randomization and Functional Coverage.

Structural Verification proves the equivalence between two representations or models using formal methods.

FV proves the equivalence between two models: RM vs RTL using simulation tools. FV is based on Controllability and Observability.


la verificacion de sistemas digitales

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