Counters and Shift Registers

Synchronous and Ripple Counters

Lab Exam

•  Have you read the Instructions sent via email/posted on web ?

•  Please come well prepared to design circuits based on your lab expts. And also for a brief viva.

•  Questions ?

Lab  -­‐  Specimen  Ques0ons  •  Measure the center frequency, upper and lower cutoff frequencies,

and the quality factor of the following RLC band pass circuit. •  Construct a full wave rectifier with a load resistance of 100Ω and a

filtering capacitance of 330µF. Measure and record the input AC voltages, output voltage and the diode current.

•  Plot the VI characteristics of the Zener diode and determine the Zener breakdown voltage.

•  Identify the components present in each of the branches of the given circuit and determine their values.

•  Design a mod-k async/sync counter •  Design a async/sync counter that counts 0,4,7,9,0,4… These are specimen Qs. There could be trickier Qs. Pls be prepared well.

End Sem Exam Syllabus

•  Complete Poriton covered – Except MOSFETS/MOSFET Amplifiers

•  You will have BJT/BJT Amplifiers

Counters

Concepts

•  Flip-flops •  Counters

– Synchronous •  Design

– Ripple

Basic Building Block •  Flip-flop

– D, T, RS, JK

J

K

Q

Q

Clock Ck J K Qn+1

0 0 Qn

0 1 0 1 0 1 1 1 Qn

Truth Table

Positive Edge Triggered JK flip-flop

Positive Edge triggered JK FF

•  J,K are called synchronous inputs •  The states of J and K are read just before

the positive edge of the CLOCK •  FF can also have asynchronous inputs •  The states at the asynchronous inputs

cause the output to change irrespective of the CLOCK – CLEAR: to make Q=0 – SET: to make Q=1

Asynchronous inputs

•  CLEAR and SET are active HIGH inputs – The required changes at the outputs happen

when these inputs are HIGH •  For normal operations these must be LOW •  You cannot leave any input pins open. All

the input pins must be tied to either a logical high or a logical low state

JK Flip Flop

Ck J K Qn+1

0 0 Qn

0 1 0 1 0 1 1 1 Qn

Truth Table Transition Table

Qn Qn+1 J K 0 0 0 X 0 1 1 X 1 0 X 1 1 1 X 0

Counters

•  1 bit counter – A: 0, 1 – One flip-flop

•  2 bit counter – BA: 00, 01, 10, 11 – Two flip-flops

•  3 bit counter – CBA: 000, 001, 010, 011, 100, 101, 110, 111 – Three flip-flops

Counters

•  Asynchronous Counters (Ripple Counters) – Outputs do not change at the same time – Gives ÷2, ÷4, ÷8, ÷16, etc. – For other divide-by-N: Decoders are required

to remove the unused states – Used for low frequency applications

J

K

Q

Q

J

K

Q

Q

J

K

Q

Q

1 1 1

1 1 1

A B C

CK

QA

QB

QC

1

1

1

0

1

1

1

1

0

0

1

0

1

0

1

0

0

1

1

0

0

0

0

0

Mod – 8 Up Counter (Ripple)

Mod – 8 Down Counter (Ripple)

Mod – 8 Up-Down Counter (Ripple)

Decade Counter with Direct Inputs (Ripple)

Counters

•  Synchronous Counters – Outputs change at the same time

(synchronous with the clock) – Design is generally complicated – Need to design the counter as per the

specified sequence of states – May be designed for any divide-by-N – Can be used up to the maximum frequency of

operation of the flip-flops

Design Example

•  Design a synchronous counter with the following sequence of states: (BA): 00,01,10,11,00 …

•  Solution – Make a table of present state, next state and

the required JK inputs – Using the excitation table fill up the required

J,K inputs – Minimize the J,K input functions – Draw the circuit diagram

2-bit synchronous up-counter Present State Next State B A

B A B A JB KB JA KA 0 0 0 1 0 X 1 X 0 1 1 0 1 X X 1 1 0 1 1 X 0 1 X 1 1 0 0 X 1 X 1

Transition Table

Qn Qn+1 J K 0 0 0 X 0 1 1 X 1 0 X 1 1 1 X 0

2-bit synchronous up-counter Present State Next State B A

B A B A JB KB JA KA 0 0 0 1 0 X 1 X 0 1 1 0 1 X X 1 1 0 1 1 X 0 1 X 1 1 0 0 X 1 X 1

B A 0 1 0 0 1 1 X X

JB=A

2-bit synchronous up-counter Present State Next State B A

B A B A JB KB JA KA 0 0 0 1 0 X 1 X 0 1 1 0 1 X X 1 1 0 1 1 X 0 1 X 1 1 0 0 X 1 X 1

B A 0 1 0 X X 1 0 1

KB=A

2-bit synchronous up-counter Present State Next State B A

B A B A JB KB JA KA 0 0 0 1 0 X 1 X 0 1 1 0 1 X X 1 1 0 1 1 X 0 1 X 1 1 0 0 X 1 X 1

B A 0 1 0 1 X 1 1 X

JA=1

2-bit synchronous up-counter Present State Next State B A

B A B A JB KB JA KA 0 0 0 1 0 X 1 X 0 1 1 0 1 X X 1 1 0 1 1 X 0 1 X 1 1 0 0 X 1 X 1

B A 0 1 0 X 1 1 X 1

KA=1

A B J

K

Q

Q

J

K

Q

Q

1

1

CK

QA

QB

1

0

0

1

1

1

0

0

1

0

0

1

1

1

0

0

Divide-by-3 synchronous up-counter Present State Next State B A

B A B A JB KB JA KA 0 0 0 1 0 X 1 X 0 1 1 0 1 X X 1 1 0 0 0 X 1 0 X 1 1 0 0 X 1 X 1

Transition Table

Qn Qn+1 J K 0 0 0 X 0 1 1 X 1 0 X 1 1 1 X 0

Divide-by-3 synchronous up-counter

B A 0 1 0 0 1 1 X X

JB=A

Present State Next State B A B A B A JB KB JA KA 0 0 0 1 0 X 1 X 0 1 1 0 1 X X 1 1 0 0 0 X 1 0 X 1 1 0 0 X 1 X 1

Divide-by-3 synchronous up-counter

B A 0 1 0 X X 1 1 1

KB=1

Present State Next State B A B A B A JB KB JA KA 0 0 0 1 0 X 1 X 0 1 1 0 1 X X 1 1 0 0 0 X 1 0 X 1 1 0 0 X 1 X 1

Divide-by-3 synchronous up-counter

B A 0 1 0 1 X 1 0 X

JA=B’

Present State Next State B A B A B A JB KB JA KA 0 0 0 1 0 X 1 X 0 1 1 0 1 X X 1 1 0 0 0 X 1 0 X 1 1 0 0 X 1 X 1

Divide-by-3 synchronous up-counter

B A 0 1 0 X 1 1 X 1

KA=1

Present State Next State B A B A B A JB KB JA KA 0 0 0 1 0 X 1 X 0 1 1 0 1 X X 1 1 0 0 0 X 1 0 X 1 1 0 0 X 1 X 1

Shift Register

Parallel Transfer between Shift Register

Bi Directional Shift Register

Parallel In Serial Out SR