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University of Notre DameCSE/EE 40462/60462, Fall 2013

VLSI Circuit Design

Lecture 111st October 2013

University of Notre Dame, CSE/EE 40462/60462

VLSI Circuit Design, Outline29 lectures in 15 weeks (27th Aug.— 12th Dec. 2013)

2CSE/EE 40462/60462 VLSI Circuit Design, Ismo Hänninen

Course Wk Lecture Homework1 L1: Overview

L2: Physics & Semiconductor Devices H0: Pre-course knowledge quiz (due wk 2 Monday before noon)2 L3: CMOS Circuits #1 H1: Basic CMOS Transistor Circuits (due wk 3 Tuesday)

L4: CMOS Circuits #23 L5: MOS Transistor Theory H2: MOSFET Theory & Modeling (due wk 4 Tuesday)

L6: MOSFET Circuits4 L7: MOSFET Real World Effects H3: Circuit Level Simulation Using SPICE (due wk 6 Tuesday)

L8: Basic CMOS Fabrication Process5 L9: CMOS Layout Design & Design Rules H4: Fabrication & Layouts (due wk 6 Tuesday)

L10: Standard Cells & Stick Figure Layouts6 L11: Layouts & Simulation

L12: Review for EXAM 1/3 EXAM 1/3 handout (due wk 7 Tuesday)7 L13: Verilog #1 H5: Verilog (due wk 8 Tuesday)

H5: Semiconductor Layout Tools (due wk 7 Thursday)

VLSI DESIGNI s m o H ä n n i n e n

U n i v e r s i t y o f N o t r e D a m eF a l l 2 0 1 3

B a s e d o n m a t e r i a l f r o mP r o f s . P e t e r K o g g e , J o s e p h N a h a s , J a y B r o c k m a n ,

U n i v e r s i t y o f N o t r e D a m eA n d P r o f . D a v i d H a r r i s ,

H a r v e y M u d d C o l l e g eh t t p : / / w w w . c m o s v l s i . c o m / c o u r s e m a t e r i a l s . h t m l

11. CMOS Layout Design 3

Slide 3 VLSI Circuit Design, 11. CMOS Layout Design 3

Outline

ReviewDesign Rules

Layout StylesStandard Cell Layouts

Stick DiagramsEuler PathsWiring Tracks and Spacing'sArea Estimation

Semiconductor Layout Tools


R U L E S

A Simplified Rule System


Rules

A simplified, technology generations independent design rule system

Express rules in terms of = f/2E.g. = 0.3 mm in 0.6 mm processCalled “Lambda rules”

Lambda rules are NOT used in commercial applicationsLambda rules need to be very conservative and thus waste space

Lambda rules are good for education! MOSIS SCMOS SUMB RulesSee Book Front Inside Cover


Simplified Design Rules

Conservative rules to get you started (W&H Fig. 1.39)

2

Missing Rule:Poly to Dif Contact

http:// http://www3.nd.edu/~cse/2013fa/40462/links.html


Transistor Width and Length

Transistor Length LParallel to travelingdirection of carriers

Transistor Width WPerpendicular to traveling

direction of carriers

Typically Width >> Length

Dimensions of Gate Overlap over Source/Drain Diffusion = Active area of a transistor


Layout Styles


Layout Styles

CustomRandom transistor and other component positioning and wiring

Standard CellLogic gates “pre-designed”

Power rails (Vdd and Vss) on top and bottomCommon N and P wells

PMOS transistors on topNMOS transistors on bottom

Gates wired together automatically using Place and Route Tool

Pitch-Matched Data PathCustom or automatic layout of logic in data channels

Typically 8, 16, 32, or 64 bits wide.Channels match each other and mesh (Memory will be discussed later)


Stick Diagrams

Stick diagrams help plan layout quicklyNeed not be to scaleDraw with color pencils or dry-erase markersRelative position of key components

What type of gates are these?

What are the widths of the nmos and pmos transistors?Slide 11 VLSI Circuit Design, 11. CMOS Layout Design 3

Repetitive Custom Layout of Ring Oscillator

Vdd

X X X X X X

X X X X X

X X X X X X

Gnd

X X


R E - U S I N G C E L L S

Standard Cell Layout


Gate Layout

Layout can be very time consumingReducing this time can be expedited if you

Build a library of “standard cells”Design gates to fit together nicely

Standard cell design methodologyVDD and GND should be some standard height & parallelWithin cell, all pMOS in top half and all nMOS in bottom halfPreferred practice: diffusion for all transistors in a row (poly vertical)

All gates include well and substrate contacts

Multi-gate circuits constructed by “snapping” gates togetherIf two standard cells abut, Vdd & GND “snap together”Adjacent gates must still satisfy design rules at boundaries

Bigger circuits constructed by rows of such multi-gatesWith “routing channels” between them for wiring (typically 2 metal levels)


In Out

NOT to scale!

What is the width of the nmos and pmos transistors? Why?What happens to size of inverter if we want to change widths?

Inverter Layout


NAND Gate Layouts

A

B

Out

A B

N

Audience Question: Why is rightmost preferred?


Inside A Modern “Standard Cell”

Have Diffusion running horizontallyP type “below” the Vdd busN type “above” the GND

Have Poly running vertically

Use metal to appropriately wire diffusionsTo Vdd & GndTo the other diffusionTo different points in current diffusion

Attach I/O contacts to metal

Question to be answered by later “Euler Path” algorithm:Can we draw diffusion as single long rectangles without gaps?

P WellP Well

N Well

VDD Bus

VSS Bus

PMOS Transistors

NMOS Transistors

Internal Gate WiringAnd Gate I/O contacts


A Simple Standard Cell Library


More Complex Gates


Pitch-Matching (Fig. 1.65)

Would it help if:A could be slightly shorter?

C could be slightly narrower?

D could be smaller?


Vdd

What If We Want to “Stack” Gates?

Vdd

Gnd

Gnd

Vdd

Design Rule says what?

But what if we “flip” one row?

Vdd

Gnd

Vdd

Gnd

Vdd

Gnd


MIPS ALU & Data Flow via Standard Cells


Now for the Full 8 Bit Data Flow


What If We Can’t Use the Internal Wiring Channels?

Audience Questions: 1. How many levels of metal do we need for this?2. How would you estimate the height of the wiring channels?3. Why is deciding which logic gate standard cell goes where important?

Wiring Channel

Wiring Channel


A Fully Synthesized 8-bit MIPS


Single DiffusionStick Diagrams


4-Input NAND Gate “Sticks” Layout

I1

I2

I3

I4

OUT

Step 1:order gates

Step 2:interconnect

Complementary transistor pairsshare common gate connection.

If pmos are 8/2, what are the nmos transistors?


Euler Paths

We start off withDiffusion as one row, no breaks!Poly runs vertically

Thus each transistor must “touch”electrically ones next to it

Question: How can we order the relationship between poly and input?“Touching” must match the desired transistor diagramMetal may optionally be used

Approach:Start with some transistor & “trace” path through rest of that typeMay require trial and error, and/or rearrangement


Finding Gate Ordering: Euler Paths

See if you can “trace” transistor gates in same order, crossing each gate once, for N and P networks independently

Where “tracing” means path from source/drain of one to source/drain of nextWithout “jumping” connections

ABCD works here


A More Complex Example

See if you can “trace” transistor gates in same order, crossing each gate once, for N and P networks independently

Where “tracing” means a path from source/drain of one to source/drain of next

Without “jumping”

ordering CBADE works for N, not Pordering CBDEA works for P, not Nordering BCADE works for both!

A (B+C) + DE

B C

A

B

CA

OUT

D

E

D E

XN

YP

XP

YN


A More Complex Example

Trace interconnected gates in SAME order, crossing each gate once, for N,P networks

ordering CBADE works for N, not Pordering CBDEA works for P, not Nordering BCADE works for both!

A (B+C) + DE

B C

A

B

CA

OUT

D

E

D E

XN

YP

XP

YN


Sticks Layout

A (B+C) + DE

B C

A

B

CA

OUT

D

E

D E

XN

YP

XP

YN


Wiring Tracks, Spacingand Area Estimation


Review: Wiring Tracks

A wiring track is the space required for a wire4 width, 4 spacing from neighbor = 8 pitch

Transistors also consume one wiring track (WHY?)


Review: Well spacing

Wells must surround transistors by 6 Implies minimum of 12 between opposite transistor flavorsLeaves room for one wire track “for free”


First Cut Area Estimation

Estimate area by counting required metal wiring tracksMultiply by 8 to express in Where does the “8” come from?


Example: NAND3

Horizontal n-active and p-active stripsVertical polysilicon gatesMetal1 VDD rail at topMetal1 GND/VSS rail at bottom32 by 40


Example: O3AI

Sketch a stick diagram for O3AI and estimate area

DCBAY )(


Example: O3AI


DCBAY )(


Another Example

Consider F= ~((A+B) (C+D))Sketch transistorsSketch stick diagramEstimate area

(H&W Question 1.17)


Typical Layout Densities

(H&W Table 1.10)

Element Area (in 2)

Random Logic 1000-1500/transistor

Datapath 250-750/transistor

SRAM 1000/bit

DRAM 100/bit

ROM 100/bit


C A D E N C E D E S I G N E N V I R O N M E N T

Semiconductor Layout Tools


Layout Tools

Drawing, Analyzing, and Verifying Circuit Layouts

CAD-tools are necessary for practical layout workCadence Design Systems is one of the major Electronic Design Automation companies

We use Cadence Virtuoso Front to Back Design Environment (icfb)Large software suite for layout, schematic, simulation, synthesisLinux/Unix machines, remote access using Xming and tunneling preferredSet up using instructions in homework H5*

The homework H5 assignments in nutshell:AMI 0.6 µm process technology, follow MOSIS SCMOS SUBM rules ( = 0.3 µm)Layout NMOS transistor cell and run Design Rule Check (DRC)Layout PMOS transistor cell and run DRCLayout CMOS Inverter using your new cells and run DRCRun Layout Versus Schematic (LVS) check on your CMOS InverterLayout 3-Stage Ring Oscillator and run DRC


l11_cmoslayout3

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