l. ratti a,c , m. manghisoni b,c , v. re b,c , v. speziali a,c , g. traversi b,c
DESCRIPTION
CMOS processes in the 100 nm minimum feature size range for applications to the next generation collider experiments. L. Ratti a,c , M. Manghisoni b,c , V. Re b,c , V. Speziali a,c , G. Traversi b,c. a Università degli Studi di Pavia Dipartimento di Elettronica. - PowerPoint PPT PresentationTRANSCRIPT
CMOS processes in the 100 nm minimum feature size range for applications to the next
generation collider experiments
L. Rattia,c, M. Manghisonib,c, V. Reb,c, V. Spezialia,c, G. Traversib,c
cINFN Sezione di Pavia
bUniversità degli Studi di Bergamo Dipartimento di Ingegneria Industriale
aUniversità degli Studi di Pavia Dipartimento di Elettronica
2VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
Use of CMOS microelectronic processes in the last two decades has had a deep impact on the way HEP instrumentation is conceived
Motivation
Quarter micron technology able to comply with the challenging design requirements of the LHC experiments in terms of
noise figure
power dissipation
radiation tolerance
Luminosity and track densities expected at the next generation colliders (LHC upgrade, ILC, Super B-Factory) set the demand for increased spatial resolution, denser functional packing, higher radiation hardness and better noise/power trade-off
HEP people is considering moving to more scaled CMOS processes
Technology monitoring to
keep design criteria and methodologies up to date
fight process obsolescence
study scaling down effects on the main design parameters
3VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
Investigated technologies and devices
Single transistors from HCMOS9 130 nm and CMOS090 90 nm triple well, epitaxial CMOS technologies by STMicroelectronics
Technology features:– VDD = 1.2 V– tOX= 2 nm– COX=15 fF/μm2
Available geometries– W = 200, 600, 1000 μm– L = 0.13 - 1 μm
Technology features:
– VDD = 1 V
– tOX= 1.6 nm
– COX=18 fF/μm2
Available geometries– W = 100, 200, 600, 1000 μm– L = 0.1 – 0.7 μm
HCMOS9 (Lmin=130 nm) CMOS090 (Lmin=90 nm)
Devices under test are PMOS and NMOS transistors with standard open layout
4VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
Operating regionDrain current in DUTs: from tens of A to 1 mA low power operation as in high density front-end circuits
Characteristic normalized drain current I*Z may provide a reference point to define device operating region
2TOX
*Z nVC2I
• μ carrier mobility
• COX specific gate oxide capacitance
• VT thermal voltage
• n proportional to ID(VGS) subthreshold characteristic
1
10
100
10-9 10-8 10-7 10-6 10-5
gm
/ID [
1/V
]
IDL/W [A]
CMOS 130 nm
CMOS 90 nm
PMOS
NMOS
I*Z,P,130 I*
Z,P,90
I*Z,N,130
I*Z,N,90
Weak inversion lawStrong inversion law
5VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
Operating region
LW
I
IIC
*Z
D0
Inversion coefficient
At the considered drain currents, DUTs work in weak or moderate inversion region
At a given drain current, operation is shifted towards weak inversion region with technology scaling
0.01
0.1
1
10
100
0.1 1
nmos L=0.13 mnmos L=1.00 mpmos L=0.13 mpmos L=1.00 m
Inv
ersi
on
Co
eff
icei
nt
Drain Current [mA]
Strong inversion
Moderate inversion
Weak inversion
90 nm techW=600 m
10-7
10-6
1 1.5 2 2.5 3 3.5
NMOSPMOS
I* z [A
]
Physical tOX
[nm]
90 nm
180 nm
130 nm
STMicroelectronics
6VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
Transconductance
At small ID (weak inversion), gm fairly independent of the device dimension and polarity
In weak inversion, possible difference between PMOS and NMOS and between CMOS nodes only due to different n values (n1.25 for both polarities and technologies considered here)
T
Dm nV
Ig
0
0.01
0.02
0.03
0 0.0002 0.0004 0.0006 0.0008 0.001
Tra
nsc
on
du
ctan
ce [
A/V
]
Drain Current [A]
NMOSW=600 mV
DS=0.6 V
L=0.35 m
130 nm tech
90 nm tech L=0.13 m
L=0.35 m
0
0.01
0.02
0.03
0 0.0002 0.0004 0.0006 0.0008 0.001
Tra
nsc
on
du
ctan
ce [
A/V
]
Drain Current [A]
90 nm techW=600 m|V
DS|=0.6 V
NMOS
PMOS
L=0.70 m
L=0.35 m
7VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
Noise in CMOS transistors
Noise in the drain current of a MOSFET can be represented through an equivalent noise voltage source in series with the device gate
(f)SS(f)S 21/f
2W
2V
SW - white noise
• channel thermal noise (main contribution in the considered operating conditions)
• other contributions from parasitic resistances
n
g
T4kS
W
m
B2ch ,
• kB Boltzmann’s constant
• T absolute temperature
• αw excess noise coefficient
• γ channel thermal noise coefficient
S1/f - 1/f noise
• technology dependent contribution
• both kf and αf depends on the polarity of the DUT
fWLfC
k(f)S
OX
f21/f
• kf 1/f noise parameter
• αf 1/f noise slope-related coefficient
8VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
1
10
100
103 104 105 106 107 108
CIN
= 6 pF
ID = 100 A
W/L = 2000/0.45, 0.25 um processW/L = 1000/0.5, 0.13 um processW/L = 600/0.5, 0.09 um process
Noi
se V
olta
ge
Sp
ectr
um
[nV
/Hz1/
2 ]
Frequency [Hz]
NMOS
Noise in different CMOS generations
250 nm TSMC
130 nm STM
90 nm STM
9VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
1
10
100
103 104 105 106 107 108
L=0.13 m
L=0.35 m
L=1.00 m
No
ise
Vo
lta
ge
Sp
ect
rum
[n
V/H
z1/2 ]
Frequency [Hz]
130 nm techW=1000 mID=0.25 mA
VDS
=600 mV
NMOS
Noise vs gate length – STM 130 nm
High frequency, white noise virtually independent of the gate length L, in agreement with gm behavior
1/f noise contribution decreases with increasing channel length, as predicted by the noise equation
1
10
100
102 103 104 105 106 107 108
L=0.13 m
L=0.35 m
L=1.00 m
No
ise
Vo
ltag
e S
pec
tru
m [
nV
/Hz1
/2]
Frequency [Hz]
130 nm techW=1000 mID=0.25 mA
|VDS
|=600 mV
PMOS
10VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
Noise vs drain current - NMOS
0.1
1
10
100
103 104 105 106 107
Id=0.10 mAId=0.25 mAId=1.00 mA
No
ise
Vo
ltag
e S
pe
ctru
m [
nV
/Hz
1/2 ]
Frequency [Hz]
STM 90 nm
NMOSW/L=600/0.2V
DS=600 mV
0.1
1
10
100
103 104 105 106 107 108
Id=0.10 mAId=0.25 mAId=1.00 mA
No
ise
Vo
lta
ge
Sp
ect
rum
[n
V/H
z1/2 ]
Frequency [Hz]
STM 130 nm
NMOSW/L=1000/0.35V
DS=600 mV
High frequency, white noise decreases with increasing drain current in both technologies, in agreement with gm behavior
1/f noise contribution is to a large extent independent of the drain current
11VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
Noise vs drain current - PMOS
0.1
1
10
100
102 103 104 105 106 107
Id=0.10 mAId=0.25 mAId=1.00 mA
No
ise
Vo
lta
ge
Sp
ect
rum
[n
V/H
z1/2 ]
Frequency [Hz]
STM 90 nm
PMOSW/L=600/0.2|V
DS|=600 mV
0.1
1
10
100
102 103 104 105 106 107
Id=0.10 mAId=0.25 mAId=1.00 mA
No
ise
Vo
ltag
e S
pec
tru
m [
nV
/Hz1
/2]
Frequency [Hz]
STM 130 nm
PMOSW/L=1000/0.35|V
DS|=600 mV
High frequency, white noise decreases with increasing drain current, more markedly so in the 90 nm technology
1/f noise contribution increases with increasing current, more significantly in the STM 130 nm technology
12VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
Noise and inversion region
1
10
100
103 104 105 106 107 108
STM 90 nm
STM 130 nm
No
ise
Vo
lta
ge
Sp
ect
rum
[n
V/H
z1/2]
Frequency [Hz]
NMOSW/L=600/0.35ID=0.1 mA
VDS
=600 mV
1
10
100
103 104 105 106 107 108
STM 90 nm
STM 130 nm
No
ise
Vo
ltag
e S
pec
tru
m [
nV
/Hz1
/2]
Frequency [Hz]
NMOSW/L=600/0.35ID=1 mA
VDS
=600 mV
At low drain current both devices work in the weak inversion region channel thermal noise is roughly the same for both devices
Better 1/f noise performance provided by the STM 90 nm technology
At high drain current, a significant difference in the channel thermal noise can be detected device from the 90 nm technology works closer to weak inversion region
13VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
0
50
100
150
200
250
300
0 50 100 150 200 250 300
Eq
uiv
ale
nt
No
ise
Res
ista
nce
[
n/gm
[
90 nm techNMOS L>0.13 m
Linear fitoffset = 1.68 +/- 1.45slope = 0.96 +/- 0.02
Channel thermal noise – STM 90 nm
Equivalent channel thermal noise resistance
slope excess noise coefficient w
w close to unity no sizeable short channel effects in the considered operating regions (no data available for channel thermal noise in devices with L ≤0.13 m)
Negligible contributions from parasitic resistances
offset noise contributions from parasitic resistors
T4k
SR
B
2W
Th
14VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
0
50
100
150
200
250
300
0 50 100 150 200 250 300
Eq
uiv
ale
nt
No
ise
Res
ista
nce
[
n/gm
[
130 nm techNMOS L > 0.13 mLinear fitoffset = 6.85 +/- 1.90slope = 1.01 +/- 0.02
0
50
100
150
200
250
300
0 50 100 150 200 250 300
Eq
uiv
ale
nt
No
ise
Res
ista
nce
[
n/gm
[
130 nm techPMOSLinear fitoffset = 1.82 +/- 2.12slope = 0.97 +/- 0.02
Channel thermal noise – STM 130 nm
αw close to unity no sizeable short channel effects in the considered operating regions also for STM 130 nm technology (except for NMOS with L=0.13 m)
Negligible contributions from parasitic resistances in NMOS devices, larger in PMOS transistors possibly due to different doping levels used in critical layers
15VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
Flicker noise
1
10
100
103 104 105 106 107
NMOSPMOSN
ois
e V
olt
age
Sp
ectr
um
[n
V/H
z1/2]
Frequency [Hz]
90 nm techW/L=600/0.2ID=1 mA
|VDS
|=600 mV
f=0.84
f=1.12
Slope f of the 1/f noise term is significantly smaller than 1 in NMOS transistors and larger than 1 in PMOS devices
16VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
0.6
0.8
1
1.2
1.4
1.6
0 0.2 0.4 0.6 0.8 1 1.2
f
Drain Current [mA]
PMOS
NMOS
130 nm tech
0.6
0.8
1
1.2
1.4
1.6
0 0.2 0.4 0.6 0.8 1 1.2
f
Drain Current [mA]
PMOS
NMOS
90 nm tech
Slope coefficient f
In the examined operating region, f does not exhibit any clear dependence on the drain current or on the channel length
f between 1 and 1.3 for PMOS devices, between 0.8 and 1 for NMOS devices
17VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
Slope coefficient f
Very similar behavior of f was detected through different CMOS generations and different foundries
0.6
0.8
1
1.2
1.4
1.6
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
PMOS
NMOS
f
Minimum Feature Size [m]
STM 90 nm
STM 130 nm
STM 180 nm
STM 350 nm
TSMC250 nm
18VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
1/f noise coefficient kf vs gate length
In the case of the 130 nm technology, short channel devices (L<0.5 m) exhibit a flicker noise coefficient larger than for NMOSFETs with longer channels
The same behavior concerns devices with L<0.2 m in the case of the 90 nm technology
0
5
10
15
20
25
30
35
40
0 0.2 0.4 0.6 0.8 1 1.2
Id=0.10 mAId=0.25 mAId=0.50 mAId=0.75 mAId=1.00 mA
Kf
[J 1
0 -2
5 H
z (a
lph
a-1
) ]
Channel Length [m]
NMOS W=1000 m
STM 130 nm
0
5
10
15
20
25
30
35
40
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
Id=0.10 mAId=0.25 mAId=0.50 mAId=0.75 mAId=1.00 mA
Kf
[J 1
0 -2
5 H
z (a
lph
a-1
) ]
Channel Length [m]
NMOSW=600 m
STM 90 nm
19VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
1/f noise coefficient kf vs Vov
0
20
40
60
80
100
120
-0.05 0 0.05 0.1 0.15 0.2
k f [J
10 -2
5 H
z (a
lph
a-1
) ]
Gate Overdrive Voltage [V]
90 nm
130 nm
PMOS
0
20
40
60
80
100
120
-0.05 0 0.05 0.1 0.15 0.2
k f [J
10 -2
5 H
z (a
lph
a-1
) ]
Gate Overdrive Voltage [V]
NMOS
PMOS
STM 130 nm
In PMOS devices, flicker noise coefficient is clearly bias dependent (dependence is weaker in STM 90 nm technology)
In NMOS transistors kf is to a large extent independent of the overdrive voltage VOV
20VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
60Co -rays effects on device performances
0.13 µm technology (open-structure layout)
ID increase in the
subthreshold region of NMOS: edge effects due
to radiation-induced charge at the shallow trench isolation (STI)
oxide. The effect is larger in devices with a shorter channel, affecting ID
regions of interest for low-power applications
(ID = 100 A). 10-10
10-8
10-6
10-4
10-2
-1.2 -0.8 -0.4 0 0.4 0.8 1.2
NMOS
I D [
A]
VGS
[V]
PMOS
W/L = 1000/0.5
before irradiation
10 MRad
21VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
In short-channel NMOS, at low ID (around 100 A) 1/f noise increases by a
much larger extent than at higher drain currents.This may be correlated with the ID increase in the subthreshold region,
meaning that the shallow trench oxide contributes in determining the 1/f noise properties of irradiated open-structure devices.
0.1
1
10
100
103 104 105 106 107 108
before irradiation10 Mrad
Noi
se V
olta
ge S
pect
rum
[nV
/Hz
1/2 ]
f [Hz]
NMOSID
= 100 A
W/L = 1000/0.35
0.1
1
10
100
103 104 105 106 107 108
before irradiation10 Mrad
Noi
se V
olta
ge S
pect
rum
[nV
/Hz
1/2 ]
f [Hz]
NMOSID
= 1 mA
W/L = 1000/0.35
60Co -rays effects on device performances
22VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
Conclusions
Static, signal and noise measurements have been performed on devices belonging to two different CMOS technology nodes, namely the 130 nm and 90 nm STM processes
Channel thermal noise equations developed to describe the device behavior in the considered operating regions provide a reliable model, with short channel effect playing a minor role in both the considered processes
1/f noise results confirm the behavior detected in previous submicron processes as far as the dependence on device polarity and bias and gate geometry is concerned
Extracted noise parameters show that using the 90 nm process may ensure an improvement in the noise performances in applications where large signal dynamic range is not needed while miniaturization can be an asset
Characterization of the 90 nm technology will be completed with radiation hardness tests (open structure vs enclosed layout, study of possible STI effects)
23VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
Backup slides
24VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
Channel thermal noise coefficient
WI
LIu ,u
3
2
2
1
u1
1*z
D
25VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
Low noise charge preamplifier design
f
f
1pOX
ff2
pm
B1gD t
1
WLC
kA2
t
1
g
T4kACCENC
• CD detector capacitance
• CG preamplifier input capacitance
• tp peaking time
• A1 A2 shaping coefficients
Circuit designers can take advantage of single device characterization to predict noise behavior of charge sensitive amplifiers
Data extracted from single transistor characterization can be used to plot minimum ENC as a function of the main design parameters (peaking time, power dissipation, polarity and dimensions of the preamplifier input device)
Equivalent noise charge is the figure of merit to be minimized:
Channel thermal noise contribution
Flicker noise contribution
It is interesting to assess whether (and if so to what extent) using a more scaled technology may improve noise performances
26VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
100
1000
10 102 103
Op
tim
um
EN
C [
e- r
ms]
Peaking time [ns]
STM 90 nm
CD=20 pF
PD.max
=0.25 mW
L=0.20 m
NMOS
PMOSSTM 130 nm
ENC vs peaking time
In the explored peaking time and power range, PMOS input device always provides better noise performances than NMOS input (except for the 130 nm process at tp close to 10 ns)
Using the 90 nm process may yield quite significant improvement with respect to the 130 nm technology, especially when NMOS input charge preamplifiers are considered
ENC was evaluated in the case of a second order, unipolar (RC2-CR) shaping processor
27VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
400
600
800
1000
3000
5000
0.01 0.1 1
STM 90 nm
STM 130 nm
Op
tim
um
EN
C [
e- r
ms]
Dissipated power [mW]
PMOSC
D=20 pF
L=0.20 mtp=20 ns
ENC vs dissipated power
At tp=20 ns, noise performances provided by NMOS and PMOS input devices in the 90 nm technology are comparable
400
600
800
1000
3000
5000
0.01 0.1 1
STM 90 nm
STM 130 nm
Op
tim
um
EN
C [
e- r
ms]
Dissipated power [mW]
NMOSC
D=20 pF
L=0.20 mtp=20 ns
Better noise-power trade-off can be achieved by using the 90 nm technology
28VI International Meeting on Front-End Electronics, Perugia, May 18th 2006
Transconductance in all inversion regions
WI
LIu ,
14u1
2
nV
Ig
*z
D
T
Dm