1 Presentation Title

KS NOTE Power Study

NDK100/ PE Jimmy

2 Presentation Title

Power table -1

3 Presentation Title

Power table -2

4 Presentation Title

H8

PMH7

SB

ADP

3207

NB

PCI DEVICE

POWERTSURUMAPWR_SW

M_ON

A_ONB_ON

VCCXM_ON

VCCXA_ON

VCCXB_ON

MPWRGDBPWRGD

BPWRGD

PWR_SW_H8

PLTRST

PCIRST

CPU_PWRGD (BPWRGDX VR_PWRGD)

VCCCPUCORE

VR_PWRGD CPURST

SLP_S3 . SLP_S4

CPU

1

2

9

4

12

11

10

8

7

5

13

14

15

aux_ON

5 Presentation Title

(1) DOCK_PWR19_F&VREGIN19& VCC3SW Power generate process with adapter

F10Adapter In Dock_PWR19_F

U12

F14

CV19

VREGIN19

1. Insert adapter to system

6 Presentation Title

Input

output

VREGIN19

VCC3SW

U74 VCC3SW

因此只要 power VREGIN19 supply to U74 , 無須控制信號 U74 產生 VCC3SW

7 Presentation Title

DOCK_PWR19_F&VREGIN19& VCC3SW Power Sequence

CV19U13

VINT19

When DCIN_DRV=H, 打開 U13 and generate VINT19

VINT19

8 Presentation Title

Power on Enable signal generate DOCK_PWR19 VINT19

when adapter insert and U64 detect AC power OK , then generate EXTPWR.

9 Presentation Title

EXTPWR 信號 be sent to Q50 產生 EXTPWR_PMH .

Of course , system need Power VL5 來打開 Q50 .

VL5 generate process as next page:

EXTPWR_PMH generate process and Power Sequence

10 Presentation Title

VL5

When U58 detect VINT19 OK , 產生MAX1977_LCDO5 , 再通過 R189 產生 VL5

VINT19U58 MAX1977_LOD5

R189Vl5

11 Presentation Title

M1_ON & M2_ON&AUX_ON

EXTPWR_PMH

EXTPWR_PMHU72

M1_ON

M2_ON

AUXON

Control Signal EXTPWR_PMH be sent to U72 , 然后產生 Control Signal M1_ON/M2_ON/AUX_ON

PWH7

12 Presentation Title

M1_ON & M2_ON&AUX_ON Sequence

13 Presentation Title

PWH Control Signal Sequence

這里順便了解一下 PWH Control Signal Sequence

(1) System detect EXTPWR OK then generate M_ON & AUX_ON (2) System detect PWRSTWITCH OK then generate A_ON &B_ON ,也就是說﹕ System generate M_ON & AUX_ON before pressing power button System generate A_ON & B_ON after pressing power button

14 Presentation Title

VCC3M_ON & VCC5M_ON & VCC1R5M_ON & VCC1R2AUX_ON & VCC3AUX_ON

15 Presentation Title

VCC3M & VCC5M

Output VCC3M Output VCC5M

Enable Signal : VCC5M_ON

VCC5M_ON

VINT19 U58 Max1977

VCC3M&VCC5M

16 Presentation Title

VCC3M & VCC5M Sequence

17 Presentation Title

MPWRGVCC5M

VCC3M

When U74 detect VCC3M&VCC5Mall OK , then it send MPWRG

BD4175KVT

U74VCC3M&VCC5M

VREGIN19MPWRG

18 Presentation Title

MPWRG Sequence

19 Presentation Title

MPWRG Signal

AND5M_ON & 3M_ON

VCC3M&VCC5MM_PGS

generate high signal when the following condition are satisfied. (1) VCC3M_ON& VCC5M_ON High (2) VCC5M Voltage SPEC: 4.311V~4.461V VCC3M Voltage SPEC : 2.793V~2.943V shut down when the following condition are satisfied (3) VCC5M < 4.311V or VCC5M > 4.461V , M_PGS shut down (4) VCC3M> 2.943V or VCC3M< 2.793V , M_PGS shut t down

20 Presentation Title

VCC1R5M

Output

Control signal

Power

U57Max1540

VCC5M&VINT19

VCC1R5M_ON VCC1R5M

21 Presentation Title

VCC1R5M Sequence

22 Presentation Title

VCC1R2AUX

VCC1R2AUX_ON

VCC1R5M

U35 VCC1R2AUX

23 Presentation Title

VCC1R2AUX Sequence

24 Presentation Title

VCC2R5M

VCC3MU30

VCC2R5M

25 Presentation Title

VCC2R5AUX & VCC3AUX

VCC3AUX_ON

VREGIN19 U74 VCC3AUX_DRV

VCC2R5M

VCC3M

Q46

Q49

VCC2R5AUX

VCC3AUX

26 Presentation Title

VCC2R5AUX & VCC3AUX Sequence

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以上介紹的 Power 是在 Adapter insert system but do not power on 產生的 ,

下面介紹 Power on 后系統的上電情況 .

Summary

28 Presentation Title

2. Power On PWRSWITCH# & PWRSW# & PWRSW_H8#

Press Power Button PWRSWITCH# D10PWRSW# PWRSW_H8#

KBC

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PWRSWITCH# & PWRSW# & PWRSW_H8# Sequence

30 Presentation Title

Enable signal Diagram

PWRSWITCH

KBC

PWH7

D10

PWRSW PWRSW_H8 ICH72

1

3

ICH_SLP_S3#

ICH_SLP_S4#

4

PM_SLP_S3#

PM_SLP_S3#

5

5

A1_ON

B1_ON

B2_ON

31 Presentation Title

ICH_SLP_S3# & ICH_SLP_S4# & PM_SLP_S3# & PM_SLP_S5# Sequence

ICH_SLP_S3# & ICH_SLP_S4# Sequence PM_SLP_S3# & PM_SLP_S5# Sequence

32 Presentation Title

A1_ON & B1_ON & B2_ON Sequence

33 Presentation Title

VCC1R8A_ON & VCC1R05B_ON & B_ON & VCC0R9B_ON

34 Presentation Title

VCC1R8A

Power

Output

Control Signal

U21VCC5M & VINT19

VCC1R8AVCC1R8A_ON

35 Presentation Title

VCC1R8A Sequence

36 Presentation Title

VCC1R05B

U57VINT19&VCC5M

VCC1R05B_ON

VCC1R05B

37 Presentation Title

VCC0R9B & VREF

Power

Control Signal

Output

U21VCC1R8A&VCC5M

VCC0R9B_ON

VCC0R9B

DDR2_VREF

38 Presentation Title

VCC2R5B

B_ON VCC2R5B_DRVU74

VCC2R5BQ39

39 Presentation Title

VCC0R9B & VCC1R05B & VCC2R5B

40 Presentation Title

VCC3B & VCC5B

B_ON 通過 U74 將 Q67&Q52 打開 to generate VCC3B&VCC5B

41 Presentation Title

VCC1R5B

B_ONU75

VCC2R5B_DRV

VCC1R5MU60 VCC1R5B

42 Presentation Title

VCCCPUCORE_ON

If VCC1R05B & VCC1R5M OK then VTT_PWRG turn high

ANDVTT_PWRG

B2_ON

SHUTDOWN2

VCORE_ON

43 Presentation Title

VCCCPUCOREVCCCPUCORE

If VCCCPUCORE OK , then generate VR_PWRGD

44 Presentation Title

VCCCPUCORE Sequence

45 Presentation Title

B POWER & VCCCPUCORE Sequence

46 Presentation Title

MPWRG & APWRG & BPWRG

If VCC3M/VCC5M & VCC3A & VCC3B/VCC5B OK , then pull high MPWRG & APWRG & BPWRG

47 Presentation Title

MPWRG & APWRG & BPWRG Sequence

Spec:APWRG to BPWRG is 80-120ms

80-120ms

48 Presentation Title

BPWRG

ICH7

CALISTOGA

PCIRST

7 7

PCIRST# CPURST#

CPUPWRGD

CPURST

1

3

2

2

CPU ADS 4

VR_PWRGD

CPUPWRGD=VR_PWRGD AND BPWRG

PLTRST