ATLAS Tile Calorimeter InterfaceThe 8th Workshop on Electronics for LHC Experiments, Colmar, 9-13

September 2002

K. Anderson, A. Gupta, J. Pilcher, H.Sanders, F. Tang, R. Teuscher, H. Wu

The University of Chicago

IntroductionInterface DesignPerformance and Radiation Test ResultsProduction Quality ControlConclusions

INTRODUCTION: TileCal and Its Readout

Electronics 64 modules in barrel region

(r1=2.28M r2=4.23M L=5.64M)

128 modules in extended regions

(r12.28M r24.23M L= 2.65M)

256 electronics drawers (64x4)

InterfaceTileCal Interface

INTRODUCTION: TileCal and Its Readout Electronics

45 PMT Blocks in barrel region 31 PMT Blocks in extended regions

One Front-end Electronics 3-in-1 Card Per PMT Block

PMT High Voltage Boards 3-in-1 Motherboard (4 sections) 8 Trigger Summing Cards in barrel

region (Stacked on 3-in-1 Motherboard)

6 Trigger Summing Cards in extended region.

(Stacked on 3-in-1 Motherboard) 1 Source Calibration Card

(Stacked on 3-in-1 Motherboard) 8 Digitizer Boards in barrel region 6 Digitizer Boards in extended

regions 1 Interface Card

(Stacked on one of Digitizer Boards)

Each Electronics Drawer Contains Following Electronics Boards:

INTRODUCTION: Interface Location in Electronics Drawer

A total of 256 Interface cards needed (One per drawer)

Card dimensions: 189x100mm Located near center of drawer Receive TTC optical signals in

electronics drawer for functional and timing controls Convert to LVDS signals and

distribute to 8 digitizer boards and 3-in-1 mother board

Transfer event data from digitizer boards to RODs Input from 8 Digitizer Boards

(from 16 Tile-DMU chips) Output to off-detector ROD

modules via G-link

INTERFACE DESIGN: GoalsGoals:• Complete 2-fold

redundancy to ROD. (except for LVDS receivers) Avoid single point of

failure for data from full drawer

Output data robust against transient SEE errors on link

• TTC failure detection and automatic switch function Interface automatic

selects a TTC signal based on signal failure conditions

INTERFACE DESIGN: Goals (Cont.1)Goals:• Data Organizer

Collect data from 16 Tile-DMUs in parallel based on Tile-DMU output protocol

Repack 32-bit data words from scrambled data transferred over 2-bit LVDS data lines (40Mpbs)

Insensitive to timing differences related to digitizer board geometry

CRC-16 and Global CRC transmission error checks over input and output segments

Altera EP20K160E

INTERFACE DESIGN: Goals (Cont.2)

Goals:• Data Organizer

G-link protocol control logic.

640Mbps output data rate (371Mbps required for TileCal @ 100Khz LVL1A rate)

• Low Cost FPGA designs Altera EP20K200E On-board JTAG

configuration port

• Single 3.3V Power Supply

Altera EP20K160E

INTERFACE DESIGN: TTC Receiver

TTC Receiver Output Waveforms

INTERFACE DESIGN:Structure of Data Organizer

INTERFACE DESIGN: Tile-DMU data stream format

INTERFACE DESIGN: Tile-DMU data stream format

INTERFACE DESIGN: Repacked stream data format

INTERFACE DESIGN: G-link Optical Transmitter (Taiwan)

Serializer Output Waveforms

From G-link Serializer

max3288cue

VCSEL Diode

TEST RESULTS: System Readout PerformanceMuon response for the 3 sampling depths (=90o)

Pedestal Superimposed

•Using “signal” from empty events

•Width reflects energy algorithm as well as electronics

•10 digitizations for each measurement (not optimized)

Muon signal well resolved from pedestal

TEST RESULTS: Radiation Requirements

Interface located at z=160cm r=410cm

Radiation Type

Sim. Level

Safety Factors Required Level

Sim.

Low Dose Rate

Lot Varn.

Total

TID 0.023Krd 3.5 5 4 70 1.6Krd

NIEL 1.5x1010 n/cm2

5 1 4 20 3.0x1011 n/cm2

SEE 6.3x108

h/cm2

5 1 4 20 1.3x1010 h/cm2

TEST RESULTS: Radiation Tests Interface located at z=160cm r=410cm All 3 studies showed Interface was fully

operational under tests

Radiation Type

Required Level

Source ExposedDose

Test Lab

TID 1.6Krd Colbt-60 2.4krd Argonne

NIEL 3.0x1011 n/cm2

Neutron 5.0x1011

n/cm2

CEA/PROSPERODijon, France

SEE 1.3x1010 h/cm2

Proton 1.5x1010

p/cm2

Indiana Univ

Production Quality Control

Web Materials Schematics, specification drawings, gerber, QC

requirements, revision history etc. Instructions to vendor (PCB and assembly)

Parts, artwork files provided by Chicago, vendor responsible for PCB fabrication and assembly

5 trial boards based on full production setup Burn-in test (power-up @65C for one week) All functional and performance tests Record to Database (Web accessible) Others

Conclusions Design is well

suited to our needs

Performance and Radiation tests demonstrated well satisfactory

Mass production is being installed in TileCal