Wookhyun Kwon 1 3/09/2009

S-RCAT(Sphere-shaped-Recess-Channel-Array-Transistor) Technology for 70nm DRAM feature

size and beyond

J.Y.Kim and Kinam Kim, et all (Samsung Electronics)

2005 Symposium on VLSI Technology

Wookhyun Kwon

Wookhyun Kwon 2 3/09/2009

This is a story about….

Egg of Columbus

How to solve a difficult problem of DRAM technology.

It was a great idea like the Egg of Columbus.

Wookhyun Kwon 3 3/09/2009

DRAM Operation

Vstorage = Qc / Cstorage

Storage Capacitor

GateBit Line

Key of DRAM operation

How long the storage node maintain the stored charge?

Target >100msec

Wookhyun Kwon 4 3/09/2009

Xj

Scaling Rule

Parameter Scaling Factor

Channel Length (Lch) 1/K

Tox 1/K

Nsub K

Xj 1/K

Channel length scaling is a necessity for small cell size. But…

Short channel Enhance DIBL

Thin gate oxide Enhance GIDL

High Nsub & Shallow junction depth Increase junction leakage.

We could not obtain sufficient data retention time near 100nm tech.

How to solve this problems?

DIBL

GIDLJunction Leakage

Motivation: Data Retention Time Issue

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Suggested Solutions

High Tech.

High-K material (for Gox and Storage cap.)

Increasing Cs

Thick gate oxide

SOI (Silicon on Insulator)

Reduce DIBL

Increasing Fab. Cost!

Wookhyun Kwon 6 3/09/2009

Simplest way is…

Planar RCAT

RCAT (Recessed Channel Array Transistor) DRAM (512Mb, ’03)

Long effective channel length & Deep junction depth.

Improve refresh characteristics

Making a long channel length in same area.

Xj

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1st Generation RCAT

Tech 110nm 90nm 80nm 70nm

Recess Depth 150nm 170nm 190n, 200nm

Vth 1.1V 1.1V 1.2V 1.2VRecess Depth

RCAT Scaling

But, by increasing recess depth

Sharp curvature problem Gox reliability

Uniformity

Neck part enlargement

Chemical Dry Etching

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2nd Generation RCAT= S-RACT

S-RCAT (Shere-shaped RCAT) DRAM (2Gb, ’03)

Larger effective channel length

Larger curvature small vertical field suppress GIDL

Small junction depth

Poly Void

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Process Sequence

Oxide spacerIsotropic Dry Etching

Key Process

Oxide spacer for protecting Si-neck-enlargement

Isotropic dry etch (Low power silicon etch)

Steam RTP oxidation or Plasma oxidation

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Electrical Characteristics

Good uniformity of Vth (250mV)

Improving DIBL (80mV 40mV)

Smaller junction leakage

Improving data retention time

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Source (IRTS 2006)

DRAM Cell Size Trend

46nm (Half pitch)

6F2

S-RCAT

We are now here!

Who?

S-RCAT

Wookhyun Kwon 12 3/09/2009

Summary

In DRAM technology, the data retention was the big problem.

Using RCAT structure, we could solve the problem by increasing the effective channel length in same cell size.

It don’t need a significant high-technology.

The great idea comes from very simple idea.

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Thank you.

Questions?

Wookhyun Kwon 14 3/09/2009

Reference

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More Scaling

S-RCAT has a good scalability to sub-50nm.

Below 40nm, the isolation between balls (C ) will be a limiter.

for further scaling below, another breakthrough in technology is needed.

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4F2 with Vertical Transistor

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6F2 Architecture

Source (Samsung)

25% cell size reduction

The 6F2 architecture have

Diagonal direction of channel

Non-planar channel (RCAT)