j.ye @ smu report: r&d work for lar upgrade may 4, 2007 @ ucsc optical link for lar upgrade...

Report: R&D work for LAr upgradeMay 4, 2007 @ UCSCJ.Ye @ SMU

Optical link for LAr upgrade readoutOptical link for LAr upgrade readout

Objectives:

Evaluate the 0.25 m Silicon on Sapphire (SOS) technology (Peregrine Semiconductor) for the LOC ASIC (done in 2006-2007)

Design the link-on-chip (LOC) ASIC version 1 (LOC1), a “prove of principle” chip. (done in 2006 - 2007)

Test LOC1. (in progress for 2007)

Design and test LOC2, a user chip. (2008 - 2009)

Irradiation evaluation on link components: VCSELs, fibers (in progress in 2007)

Manpower:One FTE, two RAs in a team of three FTEs, two RAs and two faculty members.


Evaluation of the 0.25 Evaluation of the 0.25 m SOS technology (1)m SOS technology (1)

1. Three gamma (Co-60) tests for total dose effect (TID) and one proton test (for SEE and TID) were carried out on a dedicated test chip.

2. The gamma TID tests were carried out at BNL (many thanks to Jim Kierstead and Francesco) on the transistor array which contains 48 NMOS, 48 PMOS, with 4 types of different layouts, to study the leakage current and threshold voltage change in ionizing irradiation.

3. The proton (230 MeV) SEE test was carried out at MGH on the shift registers.

4. Results submitted to NSREC, RADECS and NASA symposiums.

Transistors Array

Resistors

Resistors

Shift Register

#3

Shift Register #1

RingOsc. #1

Ring Oscillator #2

Shift Register #4

Shift Register #2

PLL components

Transistors Array

Resistors

Resistors

Shift Register

#3

Shift Register #1

RingOsc. #1

Ring Oscillator #2

Shift Register #4

Shift Register #2

PLL components

Image of the dedicated test chip.• The transistor array is used for TID test. • The shift register is used for SEE test.• PLL components, ring oscillator are used to measure parameters for LOC1 design.• Peregrine offered 50% discount of $40k, as a $20k in-kind support to this project. We share all results up to 100 krad with them.



5. Results from gamma (Co-60) TID tests.o Two types of tests were carried out:

• With the sapphire substrate floating to study leakage current sources.• With the substrate grounded during irradiation, a way we’ve found to

control the leakage current and threshold voltage change in radiation.o Leakage current sources:

o Back channel leakage has always been a concern in SOS and SOI technology. With the grounded substrate, the leakage current increase and threshold voltage change in our test chip during irradiation up to 4 Mrad are very small and not a concern.

This 0.25 m SOS technology is very rad-hard.

NMOS PMOS

NMOS PMOS

Back channel leakage contribution is 70% in NMOS, 15% in PMOS. Side leakage can be mitigated with layout techniques (like the ELT), Back channel has been controlled through expensive fabrication process.

With a grounded substrate, the leakage current increase is controlled below 250 nA. Threshold voltage increase is small and simulated to be within fabrication variations.A mechanism is proposed, under study with GEANT. A provisional patent has been filed from SMU.



6. Proton testo Source: 230 MeV proton, 1.9×1013 proton/cm2

o Tests: TID up to 106 Mrad (Si); SEE cross section (probability).o Results:

• TID: survives the TID test of 106 Mrad(Si)

• SEE: very small SEE cross section.

Test Element Type Fluence(proton/cm 2) Error Count # Cross section(cm2)

Std Shift Register 18×1012 0 <5.6×10-13

ELT Shift Register 18×1012 0 <5.6×10-13

Res. Hard Shift Register 18×1012 0 <5.6×10-13

SET free logic latch 18×1012 0 <5.6×10-13

Vcontrol(V)


Tests on fiber and VCSELTests on fiber and VCSEL

The Fiber:o Infinicor SX+ 50/250m/1.6mm MM

10G fiber from Corning. Germanium doped.o Tested wit Gamma (Co-60) and

Proton (230 MeV, 1.9×1013 proton/cm2). o Very small light loss at low flux (dose rate).

Big loss at high flux but anneals very quickly (within 1 hour) back.

o Very promising for LHC upgrade.o More tests with gamma needed.

The VCSEL:o Two HFE6192-562 (10G LC w/ 50 ohm flex) from Finisar tested .o Irradiated with 230 MeV proton, 1.9×1013 proton/cm2. o The VCSELs are biased during irradiations.o Eye diagram – see plots and table.o Looks very promising but more tests needed.

VCSEL

Before irradiation After irradiation

Rise/fall time (ps)

O-power (W)

Rise/fall time (ps)

O-power (W)

L1 114/130 431 110/128 133

L2 120/132 450 122/132 295

L1, before irradiation

L1, after irradiation


LOC1 design and submissionLOC1 design and submission

1. Status:o Prototype chip with the clock

unit (PLL), serializer, laser driver, designed and submitted in Feb. 2007. Chip will be back to SMU May 16, 2007.

o One self-biasing PLL (1.25GHz), one LC PLL (4GHz) are also placed on this chip for irradiation tests, for component level studies for future higher speed designs.

2. Goal:o Evaluate the LOC design,

perform in-lab tests, and rad-hard tests at system level.

o Provide a test chip to work on fiber attachment at chip level.

3. Spec:o 2.5 Gbps – 3.125 Gbps.

4. Submission cost:$34k. Peregrine offered 15% discount from $40k, as an in-

kind $6k contribution to this program that they are also interested in.


Conclusions on the SOS evaluation and the LOC1 Conclusions on the SOS evaluation and the LOC1 designdesign

SOS technology evaluation:

1. Peregrine 0.25 m silicon-on-sapphire technology is rad-hard for LAr readout upgrade ASIC development.

2. SEE cross section based on shift registers is found to be less than 5.6×10-12 for 230 MeV protons.

LOC1 ASIC design and submission:

1. A prototype serializer ASIC, the LOC1, has been designed and submitted. The design speed of this ASIC is 2.5 – 3.125 Gbps.

2. LOC1 is not a user chip, it is only meant for the “proof of principle” for key components and their integration in the LOC design concept.

3. LC-based PLL with a central frequency of 4 GHz has been implemented in the same submission for future higher speed designs.

Other components in the link:

We have preliminary candidates for the VCSEL and the fiber.


Plans for 2007 and 2008Plans for 2007 and 2008

1. In-lab and irradiation tests on LOC1 (2007)o Preparation for LOC1 tests:

• design PCBs to carry LOC1.• incorporate the board in our existing test systems already developed to

test the GOL.• Change VHDL code to record more information in irradiation tests.

o Plan:• In-lab function tests on LOC1:

May – August 2007.• Irradiation tests (gamma, proton) on LOC1, including data analysis:

Sept. – December 2007.• Preliminary reliability studies may also be carried out.

Sept – March 2008.

2. Fiber attachment studies (2007 – 2008):o Three attachment schemes will be studied, including flip-chip bonding. o For serial data speeds around 3 Gbps, industrial standard packaged VCSEL

module is preferred for fiber coupling. o Attracted local small companies to submit SBIR proposals on fiber coupling

studies.3. Design and evaluation of LOC2 (2008 – 2009):

o Design of LOC2 will start after we finish testing LOC1.o LOC2 will be a user chip. Close interaction with the “users” will be needed to

define the interface and functionalities. At that time, we will need to address issues like the reference clock frequency, jitter and data bus width, signal standards (CMOS or LVDS), etc. We expect a much longer design period for LOC2 than for LOC1 because of these issues.

o Chip packaging issue will be addressed with LOC2.o LOC2 will be fully evaluated in a link system, in radiation environment.

Reliability tests will be carried out with packaged chips.


Budget (for 2008)Budget (for 2008)

Manpower (1)

One FTE @ $55k/yr, w/ 25% benefit $68.75k

Manpower (2)

Two RA EE students, $1,500/mon/student. For two:$36k/yr, w/ 32% tuition benefit.

$47.5k

M&S (1) LOC2 submission $40k

M&S (2)PCB fab, flip-chip/wire bonding, components for LOC2 test

$15k

Travel For irradiation tests only $5k

Others Reliability test $0

Total With SMU 45.5% overhead $256.4k

Scenario one, LOC2 design and submission in FY 2008:


Budget (for 2008)Budget (for 2008)

Manpower (1)

One FTE @ $55k/yr, w/ 25% benefit $68.75k

Manpower (2)

Two RA EE students, $1,500/mon/student. For two:$36k/yr, w/ 32% tuition benefit.

$47.5k

Total With SMU 45.5% overhead $169.1k

Scenario two, LOC2 design in 2008 but submit for fabrication in FY 2009:

j.ye @ smu report: r&d work for lar upgrade may 4, 2007 @ ucsc optical link for lar upgrade...

Documents