june 3, 2005h themann susb physics & astronomy 1 phenix silicon pixel fem s. abeytunge c....
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June 3, 2005 H Themann SUSB Physics & Astronomy
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Phenix Silicon Pixel FEM
S. AbeytungeC. PancakeE. ShaftoH. Themann
June 3, 2005 H Themann SUSB Physics & Astronomy
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Main Tasks
• USB - PC Test Interface
• Na60 Pilot Board Tests • Prototype FEM (1.6Gbits/s fast ethernet)
• FEM – (3-4 channel VME version)
– (Production version)
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Current Status:
Prototype USB interface built and testedBasic FPGA communication code completeClock and Serial Commands tested with Na60 Pilot Visual Basic code ongoing development
USB PC Test Interface:
º No special hardware requiredº Visual Basic executable runs on Windows
PCº Execute all Digital Pilot commandsº Test and configure Pixel Chips via JTAGº Read FEM status registersº Buffered Pixel data and TDO data
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Visual Basic Control Panel
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Na60 Pilot Board Tests:
º Use Pilot/Pixel test board for FEM developmentº Develop FPGA Codeº Integrate USB test port
Current Status:
Basic FPGA communication code completeClock and Serial Commands tested with Na60 Pilot Create JTAG configuration stringsReadout Pixel data with Phenix DAQ (GTM, DCM)
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Prototype FEM (1.6Gbits/s fast ethernet):
º Develop FPGA code for 1.6Gbits/s fast ethernetº “Fast Or” Trigger extractionº Interface with RIKEN Pilot data formatº Interface with SPIRO
Schedule:Design / Layout Start Jun. 22, 2005Fabrication Sep. 12, 2005Test / Debug Oct. 5, 2005Interface with SPIRO Oct. 17, 2005
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FEM (3-4 channel VME version):
º Interface to “new” Phenix DAQ !º Interface to “new” Phenix slow control !º Develop “Fast Or” trigger module
Schedule:Design / Layout Start Aug.1st, 2005Fabrication Feb. 2006Test / Debug March 2006
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FEM (Production version):
º FEMº VME trigger module
Schedule:Design / Layout Start Mar. 1st, 2006Fabrication Aug. 2006Test / Debug Sept. 2006
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Data Generator - FEM Interface Board
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USB Interface
Na60 Pilot Board InterfaceFEM Test Interface Board
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Schedule 2005 M J J A S O N D
USB Test Interface Design FPGA code VB interface
Na60 Pilot Board tests Board arrives at SB Interface to Pilot Readout via Phenix DAQ
Prototype FEM (1.6Gbits/s) Design / Layout Fabrication Test / Debug Interface with SPIRO
FEM (3-4 channel VME) Design / Layout
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Schedule 2006 J F M A M J J A S O
FEM (3-4 channel VME) Design / Layout Fabrication Test / Debug
VTM (VME Trigger Module) Design / Layout Fabrication Test / Debug
FEM (VME Production Ver.) Design / Layout Fabrication Test / Debug