jim strait l3 co-manager, 402.04.05 november 30, 2017 · t14: overall cassette design and...

T14: Overall cassette design and prototypes processJim StraitL3 Co-Manager, 402.04.05 November 30, 2017

Scope of WBS 402.4.5 – Cassettes Cassette conceptual design

Requirements Conceptual design Different types of cassettes Interfaces Safety and Hazards

R&D and Engineering Institutions and personnel Prototyping program Risks Value Engineering Milestones

Guide to the talks in this session2

Outline

T14: Cassette design J. Strait, 2017 November 30

402.4.5 – Cassettes402.4.5.1 – Cassette Components

402.4.5.1.1 – Cooling PlatesCassette cooling plates and covers.

402.4.5.1.2 – Silicon-module motherboards*Motherboards to service the silicon modules.

402.4.5.1.3 – Cassette Interface and CablesCassette interfaces and all HV and LV cables and fibers that run between the interface and the motherboards.

402.4.5.2 – Cassette Mechanics and ToolingThe equipment, tooling, fixtures, and facilities needed for the assembly, testing and shipping of the cassettes

402.4.5.3 – Cassette Assembly, Testing and ShippingAssembly and testing of prototype and production cassettes and shipment of production cassettes to CERN.

___________________________________________________________________________*Scintillator-module motherboards are covered under 402.4.6 – Scintillator System

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Scope: WBS 402.4.5 – Cassettes


The Endcap Calorimeter system requires the following types and numbers of cassettes 168 Double-sided, 60° wide, all-silicon cassettes for the CE-E 192 Single-sided, 30° wide, all-silicon cassettes for the CE-H 384 Single-sided, 30° wide, mixed silicon/scintillator cassettes for

the CE-H

USCMS is responsible for building a subset of these: 192 Single-sided, 30° wide, all-silicon cassettes for the CE-H 168 Single-sided, 30° wide, mixed silicon/scintillator cassettes for

the CE-H Plus 1 spare of each type and size (30 total)

CMS Management requests that all cassette assembly sites be able to make any type of cassette. We plan to provide space but not all tooling to meet this request.

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Scope: WBS 402.4.5 – Cassettes


Conceptual Design

5T14: Cassette design J. Strait, 2017 November 30

Cassettes are complete, self-contained detector sub-assemblies, which are assembled into the HGCAL mechanical structure to form the Endcap Calorimeters.

The cassettes must: Combine silicon and scintillator modules and their respective

motherboards into an integrated detector, ready to be read out. Provide a mechanism to maintain the temperature of the active

detectors (silicon sensors and SiPMs) at a stable temperature -30°C

Provide interfaces to the services necessary to test and operate the detectors:- HV to bias the sensors- LV to power the on-detector electronics- Fibers to read out the data and send control signals- Refrigeration fluid

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Requirements (1)


The cassettes must: Provide a robust mechanical structure for the active detectors

elements Conform to the endcap geometry, which is set by

- rmin and rmax = f(z) (interface with the rest of CMS) - defined sampling structure of the calorimeter

Be of minimal thickness to maximize the density of the calorimeter Be of manageable size and weight to facilitate

- Handling during assembly and testing- Shipping from cassette assembly site to CERN/CMS- Handling during insertion into the endcap mechanical structure

Minimize the complexity of requirements placed on the detector elements that are integrated into the cassette.

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Requirements (2)


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Cassette Conceptual Design


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Three types of cassettes


CE‐EDouble sidedSilicon Sensors

CE‐HSingle sided

Silicon +Scint/SiPM

Sensors

CE‐HSingle sidedSilicon Sensors

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Cassette Type Characteristics


The US deliverables are: All CE-H (Silicon) cassettes: 192 + 16 spares 7 layers of CE-H (Mixed) cassettes: 168 + 14 spares

=> 360 cassettes + 30 spares = 390 total

# Full # Partial

CE‐E 2 91 ‐ 102 4 ‐ 13 0 60°1.56 ‐ 1.67

1.24 ‐ 1.32

220 ‐ 250

168

CE‐H (Silicon)

1 26 ‐ 33 2 ‐ 5 0 30°0.87 ‐ 0.97

1.33 ‐ 1.47

56 ‐ 68

192

CE‐H (Mixed)

1 5 ‐ 19 1 ‐ 4 3 ‐ 12 30°1.00 ‐ 1.39

1.54 ‐ 2.17

74 ‐ 144

384

Length (m)

Mass (kg)

# in CMS

Cassettte Type

Active sides

# Scint TileModules

Width(°)

Width (m)

Silicon Modules

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CE-E Cassette


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CE-H Cassette – Silicon Section


cassette cover

silicon modules

motherboard

cooling plate

Further details in M. Alyari’s talk

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Cooling Plate


Cassette design details and cooling calculations in E.Voirin’s talk.

Cooling plate fabrication in M.Alyari’s talk.

Main functions:• Cool sensors and electronics• Position and support the detector

elements• Attachment to external support

structure

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Mounting Silicon Modules


Further details in M. Alyari’s talk

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Silicon Modules and Motherboards


silicon modules

motherboard

Details in E.Frahm’s talk.

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Mixed Silicon-Scintillator Cassettes


Scintillator/SiPM Tile‐Module

Details in T.Kolberg’s talk.

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Mixed Cassette Cross-Section


Cassette edge with SiPM motherboard and cassette interface

The cassettes are the major detector integration unit: Silicon modules and Scintillator/SiPM tile modules Motherboards for silicon and SiPM detectors Services connections between on-detector electronics and the

outside world- Low-voltage power (digital and analog) for the electronics- High-voltage to bias the sensors- Optical connections for trigger, data and detector control- Instrumentation for cryogenics and environmental control

Cooling for the active elements Mechanical support and precise positioning within the absorber

structure

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Interfaces


Standard industrial hazards: Lifting heavy objects (cooling plates) Ergonomics of cassette assembly: e.g. leaning to install modules

in the middle of a cooling plate, repetitive motions, etc. Potentially sharp edges of components …

High voltage Cryogenic (-30°) operations Possible ODH from CO2 coolant or dry nitrogen.

(Very large leaks would be required to generate an ODH condition.)

No extraordinary hazards – all within the capabilities of Fermilab / SiDet to safely control.

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Safety and Hazards


Further discussion of hazards in Z. Gecse’s talk

R&D and Engineering

20T14: Cassette design J. Strait, 2017 November 30

FermilabM.Alyari (postdoc), P.Rubinov (eng), S.Timpone (eng), E.Voirin (eng), H.Cheung (sci), Z.Gecse (sci), J.Strait (sci), S.Tkaczyk (sci)

MinnesotaM.Revering (student), E.Frahm (eng), J.Mans (prof), R.Rusack (prof)

BrownGreg Landsberg (prof)

AlabamaConor Henderson (prof)

Collaboration with LLR/CERN on cassette designLLR: C.Ochando (sci), T.Pierre-Emile (eng), G.Fayolle (eng), M.Roy (tech)CERN: H.Gerwig (eng), S.Surkov* (eng)

* Formally U. of Wisconsin

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Institutional and Personnel Involvement


The cassette prototype program proceeds in 3 phases… Thermo-electro-mechanical mockup In process now … milestone to complete by Aug 2018 See presentation by M. Alyari

Prototype series #1 Fully functional prototypes using first complete front-end chip version

and development version of the motherboard Design work to start this spring … milestone to complete by May 2019

Prototype series #2 Prototype with (near) final front-end and motherboard electronics Design work to start in 2019 … milestone to complete by Sep 2020

… leading to the start of cassette production in summer 2021

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Cassette Prototyping Program


8” sensors and modules do not exist yet => build a mockup to learn key features of cassette design and assembly with dummy modules and motherboards.

30° cooling plate with CO2 cooling loop of size ~ largest CE-H all-silicon cassette

8 in. “dummy” modules with passive siliconwafers, prototype baseplates, simplified PCBto simulate electronics heating and test high-speed data transmission

Corresponding simplified motherboard.

Extensive array of temperature measurements23

Thermo-electro-mechanical mockup


Goals: Test assembly techniques and understand tolerances Validate thermal and thermo-mechanical performance Test high-speed data transmission between

module and motherboard through several candidate low-profile connectors.

Plan: First assembly with modules early next year. Full set of tests during winter-spring Follow up with mixed cassette mockups Milestone for completion: 28 Aug 2018.

See presentation by M. Alyari for details.24

Thermo-electro-mechanical mockup


Real 8” silicon modules and scintillator/SiPM tile-modules. Active 8” silicon sensors Fully active front-end PCB (“hexaboard”) Tile-modules with full array of scintillator tiles and SiPMs Front-end electronics based on first fully-functional version of the

front-end chip “HGROC-DV1”

Fully functional motherboards Function of concentrator may be provided by FPGAs Prototype cassette interface

Fully realistic cooling plate design – Two 30° cassettes to form a 60° “insertion unit”

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Prototype Series #1


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Prototype Series #1


Goals: Develop assembly and testing methods with real detectors Validate thermal and thermo-mechanical performance of

cassette with real modules Test of all detector elements to the extent possible with first

round electronics.

Plan: Design development to start in parallel with mockup tests. All-silicon cassette assembled as soon as modules are

available (spring 2019) Milestone “HGCROC-DV1 Cassette tested” 30 May 2019 Follow with mixed cassette prototype test by Sep 2019

8” silicon modules and scintillator/SiPM tile-modules of (nearly) final design. Front-end electronics based on (nearly) final front-end chip

“HGROC-DV2” Both full and partial modules available

Motherboards of (nearly) final design Concentrator ASIC V2 “Final” cassette interface

Include all three cassette variants and size ranges Silicon and mixed single-sided CE-H cassettes, including a

prototype of the largest ones (CE-H layers 18-24) CE-E double-sided cassette (to be built at assembly Site #2,

probably CERN)

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Prototype Series #2


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Prototype Series #2


Goals: Develop and validate final assembly and testing

procedures (see talk by Z. Gecse) Full validation of final cassette design including

performance of final module and electronics elements Provide requirements for final iterations of all designs

Plan: Design development to start in parallel with series #1

testing. Prototype built at both assembly sites spring-summer 2020 Milestone “HGCROC-DV2 Cassette validated” 17 Sep

2020.

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Cassette Development and Production Schedule


Cassette design / development milestones

Cassette assembly facility milestones

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Cassette Prototyping Schedule


Risks from (draft) HGCAL Risk Register Cooling Plate fabrication fails specification in term of flatness,

location of features, cooling tube performance. Motherboard and Interface Board fabrication fails mechanical or

electrical specifications with adequate reliability -- larger than expected failure rate identified during cassette production.

Damage or loss of cassettes during assembly or shipping. A single cassette or batch of cassettes is damaged or lost when handling cassettes during assembly, testing or shipping to CERN.

Risks from (draft) US CMS HL-LHC Project Risk Register Cassette is damaged during assembly Damaging 10 cassettes during cold testing Batch of 20 cassettes are damaged in shipping

Straightforward mitigation strategies can minimize these risks.31

Cassette Risks


A complete conceptual design is documented in the US CDR and the CMS-HGCAL TDR. US groups have been very active participants in developing this

design.

The first thermo-electro-mechanical mockup is under construction. The first fully operational prototype will be assembled

and tested in FY2019. No major hazards or risks.

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Conclusion and Outlook


Cooling Plates – Erik Voirin Cooling plate design details Modeling of the thermal performance of the cassettes

Motherboards – Erich Frahm Design, construction, and testing of the silicon motherboards Motherboards for the mockup and prototypes

Cassette Assembly – Zoltan Gecse Tools and clean room facility for cassette assembly Development of assembly and test procedures and plans

Mockup Cassette – Maral Alyari Status and plans for construction and test of the mockup cassette Many details about the evolving cassette design

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Guide to the talks that follow


jim strait l3 co-manager, 402.04.05 november 30, 2017 · t14: overall cassette design and...

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