jasma balasangameshwara resume 16012011
TRANSCRIPT
Jasma BalasangameshwaraResume
Contact
Research InterestsGrid Computing, Data Mining, Distributing Computing
Education
Pursuing Research Work on Grid Computing under Anna University, Coimbatore,
Tamil Nadu, INDIA since April-2009.
Master of Technology in Computer Science and Engg, M.S.Ramaiah Institute of
Technology affiliated to Visweswaraiah Technological University, Karnataka, INDIA
Bachelor of Engineering, in Information Science & Engineering, from Atria
Institute of Technology affiliated to Visweswaraiah Technological University,
Karnataka, INDIA
M.Tech Thesis
A Decentralized Approach to Dynamic Load Balancing for Heterogeneous Computing NodesSupervisor: Mrs. Annapurna Patil, Department of Computer Science and Engineering, M.S Ramaiah Institute of Technology, Bangalore, India
Publications
Journal
A Decentralized Recent Neighbor Load Balancing Algorithm for Computational GridsJasma Balasangameshwara and Nedunchezhian RajuInternational Journal of ACM Jordan (IJJ), Vol. 1, No. 3, 2010iswsa2010.acm.org/volumes/volume1/no3/ijjvol1no3p12.pdf
Conference
A Fault Tolerant Optimal Neighbor Load Balancing Algorithm for Grid EnvironmentJasma Balasangameshwara and Nedunchezhian Raju2010 International Conference on Computational Intelligence and Communication Systems, held on November 26-28, 2010, Bhopal, India
A Recent Neighbor Algorithm for Load Balancing in Clusters with Distributed Servers Prashanth Kambli and Jasma Balasangameshwara
: +91 9886 019 686 Email Id : [email protected]
Address : J414, New Rajendra Nagar, Delhi-60
International Conference on High Performance Computing, Networking and Communication Systems, held on July 13-16, 2009, Orlando, Floridahttp://www.promoteresearch.org/2009/proceedings-listing-2009/hpcncs09.html
Employment
Worked as an software intern in Intel Corporation in Platform Validation and Enabling Team from 17th July 2006 to 17th July 2007 (1 year) on VB.Net. My responsibility was to develop and manage the following projects
Event Monitoring Agent for Random Test Generator Each processor has a set of registers that needs to be monitored. Only certain events can be programmed in certain registers, which basically limit the number of events that can be collected at once. The Event Monitoring Agent collects and analyzes the various types of performance counters that are hit when a particular test case is run on the target platform and also determines the success/failure of the tests conducted on the platform.
Event Monitoring System for Focus Test GeneratorThis project schedules and runs the test cases on the target platform to collect all events that are hit. The processor performance is determined based on the number of successful hits to an event.
Development of an Automation Tool for Post Silicon ValidationPost Silicon Validation is the real time testing of the silicon chip. After the fabrication of the chip, the stability of the chip is determined by testing its core and I/O. The automation tool is responsible for maintaining a database for the type of chips currently being tested, number of test cases run and outcome of the test case. The silicon chip resides on a platform, which is connected to a host machine. The tool runs on a server, which is connected to all the active platforms to determine the validation status of its respective chips.
Currently working as a faculty member (on leave) in the Department of Computer Science & Engineering of Atria Institute of Technology, Bangalore from May 2008.
Teaching Skills
Programming Languages:C, C++, Java, J2EE, C# Technologies Worked on:VB, .NET Mark-up Languages:HTML, XML Scripting Languages: JavaScript Database: Oracle 9i(SQL/PLSQL) Operating Systems: Win 98/XP/2000, Linux Networking Simulator Tools: Opnet, GridSim
Academic Experience
Courses taught at Atria Institute of Technology, Bangalore for under-graduate stream (Bachelor of Engineering).
Logic Design Computer Networks
Computer Graphics and Visualization Web Programming
Academic Excellence
Faculty Development Programs
Participated in four-day workshop on “Computer Graphics and Visualization” held at RNSIT, Bangalore in January 2009.
Participated in four-day workshop on “Web Programming” held at RNSIT, Bangalore in July 2009
Referee
Dr. Renuka Ravindran, M.Sc, Ph.D., Professor, Dept. of Computer Science & Engineering, Atria Institute of Technology, BangaloreEmail: [email protected]
Personal Details
Father’s Name: Dr V.H BalasangameshwaraMother’s Name: Devaki RajuDate of Birth: 10/03/1984Nationality: INDIANMartial Status: MarriedLanguages Known: English, Hindi and KannadaExtra Curricular Activities: Bharathanatyam, Kuchipudi and Kathak