IWLPC October 13-15, 2015

Metrology Considerations for Through Silicon Via

ManufacturingKe Xiao, Sanjeev Singh, Holly Edmundson,

John Allgair, Tim JohnsonNanometrics, Inc.

Daniel Smith, Yudesh RamnathGlobal Foundries US, Inc.

Through Silicon Vias

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3D IC integration improves performance and device density power consumption

TSV is a key enabling technology for 3D IC integration

Three “flavors” of process Via first (vias created prior to FEOL processing) Via middle (vias created after FEOL processing) Via last (vias created from backside of finished

wafer)

Via-middle 3D TSV packaging process flow

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Interferometry Overview

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Incoming light is split between a reference leg and a test leg

The reference surface can move to change the reference path length

The detector registers the sum of the signal from the test surface and the reference surface.

Scanning White Light Interferometry

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Monochromatic Interference

(3 wavelengths)

Reference Leg = Test Leg at this point

Reference Leg = Test Leg at this point

White-light Interference

Scan objective,

Collect interference patterns (x-y)

Extract interference pattern (z)

Analysis results in 3D image (topography)

PZT

Z-position

Inte

nsi

ty

Interference

objective

Image lens

Camera

Object

Light

source

Reference mirror

Technology Overview: Scanning White Light Interferometry

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Signal from a single pixel

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Scanning White-Light Interferometry Data

■ The data is a collection of images taken at different scan positions, both through focus and through interference.

■ Tracing a single pixel through the stack gives a white-light interference pattern.

■ Analyzing each individual pixel trace gives a topography image.

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DCD Metrology

Apply photoresist

Expose

Develop

Measure CD (prior to etch)

CD-SEM image of 6um DCD

Optical image of 6um DCD

3D surface of 6um DCD

cross-section of 6um DCD

Focus exposure matrix wafer for DCD

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■ Typical Interferometer Performance

– 30 WPH, 13 sites

– Depth precision ~ 7nm

– CD precision ~ 5 nm CD Measured with Imaging Interferometer

TSV Etch - Depth & TCD

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SPC chart of 6x55 um TSV depth and TCD measured with imaging interferometer

■ Typical Interferometer Performance

– 23 WPH, 13 sites

– Height precision ~ 20 nm

– CD precision ~ 20 nm

X-SEM of TSV

High aspect-ratio TSV Etch - Depth & TCD3x50 um TSV bottom surface and top surface topography as

measured by imaging white-light interferometer

3x50 um TSV Samples

Mean Depth Data (13 sites, 15 rpts)

Depth Std DevDepth Range

(WIW)

Sample 1 0.036 um 0.508 um

Sample 2 0.041 um 0.488 um

TSV InspectionLower magnification Imaging Interferometry to generate larger fields of view used to scan the full wafer for missing or mis-processed vias. Image of via bottom surfaces

Image of via bottom surfaces

Incompletely etched or blocked vias can look identical to a properly etched via with brightfield inspection.

Finding the bottom surface ensures the via was etched to depth.

TSV Cu fill by electroplating process

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Schematic of underfill and void problem

■ Monitoring the surface topography can reveal problems with underfill that affect yield.

TSV Cu fill by electroplating process

14X-SEM of voids at the bottom of Cu-filled TSVs

■ To find voids, the fill process can be interrupted when the vias are partially filled.

■ The depth of the vias can be measured with interferometry.

■ Vias with voids will measure shallower than vias without.

■ The wafer can then be returned to complete the fill process.

Schematic of partially filled vias.

CMP and Cu pumping

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■ Following the Cu fill, excess Cu is removed.

■ The planarity of the surface is critical to subsequent processing steps.

■ Planarity can be affected by the CMP that removes the excess Cu.

■ Planarity can also be affected by changes in the Cu-filled via during anneal.

Erosion following CMP

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■ Cross-sections show non-uniformity in polish near the TSV.

Erosion following CMP

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Surface topography of post-CMP TSV showing erosion

■ Surface map is generated by imaging interferometry

■ Allows for high-speed in-line monitoring

TSV Cu pumping

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■ Grain growth during anneal can change the surface profile of the filled via

■ Cross-section shows change in surface profile and effect on the subsequent layer.

TSV Cu pumping

19SPC chart of Cu pumping step height relative to field

■ Surface map shows the emergence of a distinct grain.

Grain emerging from Cu filled TSV

TSV Reveal

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SEM image of revealed TSV Cu, post cmp (left), and pillar post etch (right)

■ In this final step, the completed TSVs are exposed and made ready for stacking.

3D interferometer image of Cu pillar

TSV Reveal

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■ Wafer map of pillar height, measured with interferometry.

3D interferometer image of Cu pillar

TSVs for 3D IC integration pose new processing challenges.

Interferometry provides a robust, non-destructive method for the challenge of monitoring the TSV etch to depth

Interferometry can also supplement or replace other technologies for monitoring many of the other critical parameters in the TSV process.

Summary