itanium processor
DESCRIPTION
Itanium Processor. PRESENTED BY: Sasmita Kumari Misra Branch: CS&E Roll No: S/08/64. INTRODUCTION. - PowerPoint PPT PresentationTRANSCRIPT
![Page 1: Itanium Processor](https://reader034.vdocuments.us/reader034/viewer/2022042422/568136d3550346895d9e70c0/html5/thumbnails/1.jpg)
Itanium Processor
PRESENTED BY:Sasmita Kumari Misra
Branch: CS&ERoll No: S/08/64
![Page 2: Itanium Processor](https://reader034.vdocuments.us/reader034/viewer/2022042422/568136d3550346895d9e70c0/html5/thumbnails/2.jpg)
The Itanium processor family came about for several reasons, but the primary one was that the processor architecture advances of RISC were no longer growing at the rate seen in the 1980’s or the 1990’s.Yet,customers continued demand greater application performance.
The Itanium processor family was developed as a response to address the future performance and growth needs of business, technical and scientific users with greater flexibility, better performance and a much greater ‘bang for the buck’ in the price performance arena.
The Itanium architecture achieves a more difficult goal than a processor that could have been designed with ‘price as no object’.
INTRODUCTION
![Page 3: Itanium Processor](https://reader034.vdocuments.us/reader034/viewer/2022042422/568136d3550346895d9e70c0/html5/thumbnails/3.jpg)
OverviewHistory
32 bit Processors (Pentium Pro, Pentium Xeon)
64 bit Processors (Xeon, Itanium, Itanium 2)
ISAEPICPredicated Execution (Branch Prediction)
Software Pipelining
![Page 4: Itanium Processor](https://reader034.vdocuments.us/reader034/viewer/2022042422/568136d3550346895d9e70c0/html5/thumbnails/4.jpg)
OverviewISA cont.
Register StackingIA-32 EmulationSpeculation
ArchitectureBenchmarks
![Page 5: Itanium Processor](https://reader034.vdocuments.us/reader034/viewer/2022042422/568136d3550346895d9e70c0/html5/thumbnails/5.jpg)
ISA OverviewMost Modern Processors:
Instruction Level Parallelism (ILP)
Processor, at runtime, decides which instructions have no dependencies
Hardware branch prediction
![Page 6: Itanium Processor](https://reader034.vdocuments.us/reader034/viewer/2022042422/568136d3550346895d9e70c0/html5/thumbnails/6.jpg)
Itanium’s ISA IA-64 – Intel’s (first) 64-bit ISA Not an extension to x86 (sucks) (Completely
new ISA) Allows for speedups without engineering
“tricks” Largely RISC Surrounded by patents
![Page 7: Itanium Processor](https://reader034.vdocuments.us/reader034/viewer/2022042422/568136d3550346895d9e70c0/html5/thumbnails/7.jpg)
IA-64IA-64 largely depends on software for
parallelism
VLIW – Very Long Instruction Word
EPIC – Explicitly Parallel Instruction Computer
![Page 8: Itanium Processor](https://reader034.vdocuments.us/reader034/viewer/2022042422/568136d3550346895d9e70c0/html5/thumbnails/8.jpg)
IA-64VLIW – Overview
RISC technique Bundles of instructions to be run in parallel
Similar to superscaling Uses compiler instead of branch prediction hardware
![Page 9: Itanium Processor](https://reader034.vdocuments.us/reader034/viewer/2022042422/568136d3550346895d9e70c0/html5/thumbnails/9.jpg)
IA-64EPIC – Overview
Builds on VLIW Redefines instruction format Instruction coding tells CPU how to process data
Very compiler dependent Predicated execution
![Page 10: Itanium Processor](https://reader034.vdocuments.us/reader034/viewer/2022042422/568136d3550346895d9e70c0/html5/thumbnails/10.jpg)
IA-64Predicated Execution:
Decrease need for branch prediction
Increase number of speculative executions
Branch conditions put into predicate registers
Predicate registers kill results of executions from not-taken branch
![Page 11: Itanium Processor](https://reader034.vdocuments.us/reader034/viewer/2022042422/568136d3550346895d9e70c0/html5/thumbnails/11.jpg)
IA-64Software Pipelining:
Take advantage of programming trends and large number of available registers
Allow multiple iterations of a loop to be in flight at once
![Page 12: Itanium Processor](https://reader034.vdocuments.us/reader034/viewer/2022042422/568136d3550346895d9e70c0/html5/thumbnails/12.jpg)
IA-64EPIC – Pros:
Compiler has more time to spend with code
Time spent by compiler is a one-time cost
Reduces circuit complexity
![Page 13: Itanium Processor](https://reader034.vdocuments.us/reader034/viewer/2022042422/568136d3550346895d9e70c0/html5/thumbnails/13.jpg)
IA-64EPIC – Cons:
Runtime behavior isn’t always obvious in source code
Runtime behavior may depend on input data
Depends greatly on compiler performance
![Page 14: Itanium Processor](https://reader034.vdocuments.us/reader034/viewer/2022042422/568136d3550346895d9e70c0/html5/thumbnails/14.jpg)
IA-64IA-32 Support:
Done with hardware emulation
Uses special jump escape instructions to access
Slow (painfully so)
![Page 15: Itanium Processor](https://reader034.vdocuments.us/reader034/viewer/2022042422/568136d3550346895d9e70c0/html5/thumbnails/15.jpg)
IA-6432 Bit Hardware Emulation - Very Poor
Performance
Software Emulation of x86 32-bit from either Microsoft or Linux can perform 50% better than Intel’s Hardware Emulation
Less than 1% of the chip devoted to Hardware Emulation
![Page 16: Itanium Processor](https://reader034.vdocuments.us/reader034/viewer/2022042422/568136d3550346895d9e70c0/html5/thumbnails/16.jpg)
IA-64IA-32 Slowness:
No out-of-order execution abilities
Functional units don’t generate flags
Multiple outstanding unaligned memory loads not supported
![Page 17: Itanium Processor](https://reader034.vdocuments.us/reader034/viewer/2022042422/568136d3550346895d9e70c0/html5/thumbnails/17.jpg)
IA-64IA-32 Support:
Hardware emulation augmented for Itanium 2
Software emulation (IA-32 Execution Layer) added
Runs IA-32 code at same speed as equivalently clocked Xeon
![Page 18: Itanium Processor](https://reader034.vdocuments.us/reader034/viewer/2022042422/568136d3550346895d9e70c0/html5/thumbnails/18.jpg)
ArchitecturePhysical LayoutConceptual Design Elements
![Page 19: Itanium Processor](https://reader034.vdocuments.us/reader034/viewer/2022042422/568136d3550346895d9e70c0/html5/thumbnails/19.jpg)
Register Stack Engine (RSE)Improve performance by removing latency
associated with saving/restoring state for function calls
Hardware implementation of register stack ISA functionality
![Page 20: Itanium Processor](https://reader034.vdocuments.us/reader034/viewer/2022042422/568136d3550346895d9e70c0/html5/thumbnails/20.jpg)
Itanium Pipeline10 Stage
Instruction Pointer GenerationFetchRotateExpandRenameWord-Line DecodeRegister ReadExecuteException DetectWrite Back
![Page 21: Itanium Processor](https://reader034.vdocuments.us/reader034/viewer/2022042422/568136d3550346895d9e70c0/html5/thumbnails/21.jpg)
Itanium’s ability to handle just about any operating system that is run on it makes it a natural fit for today’s mixed network environments. Itanium architecture today includes world-class capability for targeted applications, including:•Databases•High-Performance Computing•Enterprise Resource Planning, Supply Chain Management •Mechanical Computer Aided Engineering(MCAE),Intensive Custom Applications(financial, petroleum, others)•Business Intelligence•Security Transactions
![Page 22: Itanium Processor](https://reader034.vdocuments.us/reader034/viewer/2022042422/568136d3550346895d9e70c0/html5/thumbnails/22.jpg)
Itanium 2 Pipeline8 stage
Instruction Pointer GenerationRotateExpandRenameRegister ReadExecuteDetectWrite Back
![Page 23: Itanium Processor](https://reader034.vdocuments.us/reader034/viewer/2022042422/568136d3550346895d9e70c0/html5/thumbnails/23.jpg)
Processor Abstraction Layer (PAL)
Internal processor firmware
External system firmware
![Page 24: Itanium Processor](https://reader034.vdocuments.us/reader034/viewer/2022042422/568136d3550346895d9e70c0/html5/thumbnails/24.jpg)
Itanium 2 Execution Core6 multimedia units6 integer units2 FPU3 branch units4 load / store units
![Page 25: Itanium Processor](https://reader034.vdocuments.us/reader034/viewer/2022042422/568136d3550346895d9e70c0/html5/thumbnails/25.jpg)
IA-32 Execution Hardware
![Page 26: Itanium Processor](https://reader034.vdocuments.us/reader034/viewer/2022042422/568136d3550346895d9e70c0/html5/thumbnails/26.jpg)
Thank You