issues multiple clock domains multiple frequencies clock skew between clock domains on-chip pll...

IssuesIssues

Multiple clock domainsMultiple clock domains Multiple frequenciesMultiple frequencies Clock skew between clock domainsClock skew between clock domains On-chip PLL generated clocksOn-chip PLL generated clocks Multiple PLLs for deskewingMultiple PLLs for deskewing Invalidation of delay testsInvalidation of delay tests Overtesting (testing of sequential false paths)Overtesting (testing of sequential false paths) Design of scan enable signalsDesign of scan enable signals Power dissipationPower dissipation Ground bounceGround bounce

ObjectivesObjectives

Apply test with system timing in the capture windowApply test with system timing in the capture window

Clk1Clk1

Clk2Clk2

Clk3Clk3

Multiple frequenciesMultiple frequencies

F1F1

F2F2

F3F3

F1F1

F1F1

F2F2 F3F3

F2F2

F3F3

Capture domainCapture domain

Laun

ch d

omai

nLa

unch

dom

ain

Multiple clock domainsMultiple clock domains

D1D1

D1D1

D2D2 D3D3

D2D2

D3D3

D1D1

D2D2

D3D3

Capture domainCapture domain

Laun

ch d

omai

nLa

unch

dom

ain

Single clock domain, single captureSingle clock domain, single capture

Capture window: from last shift to captureCapture window: from last shift to capture Scan enable has to propagate to all scan cells in Scan enable has to propagate to all scan cells in

less than one cycleless than one cycle Overtesting - transitions may be launched from an Overtesting - transitions may be launched from an

illegal stateillegal state Delay test may be invalidated Delay test may be invalidated

last shiftlast shift capturecapture

SenSen

ClkClk

capture modecapture mode

shift modeshift mode

loadingloading unloadingunloading

Scan enable signal for at-speed scanScan enable signal for at-speed scan

Scan enable signal designed as a clock treeScan enable signal designed as a clock tree

clockclock

scan enablescan enable

Pipelined scan enable signalPipelined scan enable signal

clockclock


Speed of loadingSpeed of loading

Only the timing in capture window is crucial to Only the timing in capture window is crucial to at-speed testingat-speed testing

The loading and unloading frequency is The loading and unloading frequency is irrelevant to at-speed testingirrelevant to at-speed testing

Slower frequency can be used to reduce power Slower frequency can be used to reduce power and constraints on test controllerand constraints on test controller

Faster frequency can be used to reduce the test Faster frequency can be used to reduce the test application timeapplication time

SS CCSS SSClockClock

suppressionsuppressionClockClock

suppressionsuppression

Double captureDouble capture

first capture & transition launchfirst capture & transition launchcapturecapture

SenSen

ClkClk

last shiftlast shift

TimeTimeframeframe

11

Launch from a semi-legal stateLaunch from a semi-legal state Reduced overtestingReduced overtesting Double time frame sequential fault simulationDouble time frame sequential fault simulation

TimeTimeframeframe

22

““Slow” scan enableSlow” scan enable

Scan enable signal has 1.5 cycle to propagate

Scan enable signal has 1.5 cycle to propagate

last shiftlast shift capturecapture capturecapture first shiftfirst shift

ClockClocksuppressionsuppression


SenSen

ClkClk

clockclock


Slow scan enableSlow scan enable

last shiftlast shift launchlaunch capturecapture first shiftfirst shift



SenSen

ClkClk

Loading of random stateLoading of random state





SenSen

ClkClk

1. Initialization of internal nodes1. Initialization of internal nodes2. Deactivation of scan enable 2. Deactivation of scan enable 3. Propagation of scan enable signal (1.5 cycle)3. Propagation of scan enable signal (1.5 cycle)4. Transition to a semi-legal state4. Transition to a semi-legal state5. Launch of transitions5. Launch of transitions





SenSen

ClkClk

1. Propagation of signals1. Propagation of signals2. Capture of responses2. Capture of responses





SenSen

ClkClk

1. Activation of scan enable1. Activation of scan enable2. Propagation of scan enable2. Propagation of scan enable3. First shift out of responses3. First shift out of responses





SenSen

ClkClk

Continued unloading of responsesContinued unloading of responses

Phase lock loop circuitPhase lock loop circuit

Frequency synthesisFrequency synthesis

PLLPLLPLLPLL

ffp p / n/ nffp p / n/ n

ClockClock ffpp = nf= nfclkclk

PLL deskewingPLL deskewing

PLLPLL22PLLPLL22

ClockClock

DeskewingDeskewing

NoNo YesYes

PLLPLL11PLLPLL11

global skewglobal skew

Clock skew and race conditionsClock skew and race conditions

clockclock

Clock skew results in raceClock skew results in race Separate capture requiredSeparate capture required

Fundamental principleFundamental principle

If clock skew is not managed between A and B If clock skew is not managed between A and B If there is logic driven by A and captured in BIf there is logic driven by A and captured in B There should be no simultaneous change of There should be no simultaneous change of

state in A and capture in Bstate in A and capture in B

Domain ADomain A Domain BDomain B

Shift or captureShift or capture CaptureCapture


ObjectiveObjective: at-speed testing of logic within every : at-speed testing of logic within every clock domain and between clock domainsclock domain and between clock domains

PLLPLLPLLPLL

Test modeTest mode

BIST modeBIST mode

CLKCLK

SESE

CLKCLK

SESE

CLKCLK

SESE

Implementation - clock suppressedImplementation - clock suppressed

Robust operations assured with clock skew between domainsRobust operations assured with clock skew between domains Captured and shifted data used as a stimuli for other domainsCaptured and shifted data used as a stimuli for other domains The order of capture can change in different vectorsThe order of capture can change in different vectors Combinational fault simulation is sufficient as the response Combinational fault simulation is sufficient as the response

data is shifted outdata is shifted out One scan enable signal can be used for all domainsOne scan enable signal can be used for all domains

SS

SS

SS

S*S*S*S*

S*S*SS

SSSS

DD11

DD22

DD33







CC

CC

CC

Implementation with hold statesImplementation with hold states

Clock suppression replaced with hold stateClock suppression replaced with hold state Non-capturing domains put in hold stateNon-capturing domains put in hold state

SS

SS

SS

S*S*S*S*

S*S*SS

SSSS

DD11

DD22

DD33

HH

HH

HH

HH

HH

HH

ControlControlControlControl

CLKCLK

SESE HH

CC

CC

CC

scan

Multiple frequencies - single captureMultiple frequencies - single capture

CC

All intra and inter domain logic is tested at speedAll intra and inter domain logic is tested at speed Combinational fault simulation is adequateCombinational fault simulation is adequate

Clk1Clk1

Clk1*Clk1*

Sen1Sen1

Clk2*Clk2*

Sen2Sen2

Load / unload windowLoad / unload window Capture windowCapture window

CC

Slow enable and multiple frequenciesSlow enable and multiple frequencies

CC

CC

Clk1Clk1

Clk1*Clk1*

Sen1Sen1

Clk2*Clk2*

Sen2Sen2

CC


Multiple clocks per capture cycle All inter domain logic can be tested Sequential fault simulation

SS

SS

SS

SS

SS

SS

DD11

DD22

DD33

CC

CC

CC

CC

Multiple clock domains – domain analysisMultiple clock domains – domain analysis

Merging non-interacting clock domains Allows several clocks to be targeted at once

• Reduces tester clock requirements• More efficient patterns• Better pattern count

SS

SS

SS

SS

SS

SS

DD11

DD22

DD33

CC

CC

CCCC

CC

CC

Clock routingClock routing

BIST ResetBIST Reset

External clockExternal clocksourcesource

holdhold

SenSen

BISTBISTDoneDone

BIST RunBIST Run

...... ...

...

Shift counterShift counterShift counterShift counter

Pattern counterPattern counterPattern counterPattern counter

SenSen

ScanScanScanScan

ScanScanScanScan

SinSin SoutSout

MMIISSRR

PPRRPPGG

PLLPLLPLLPLL

ClockClockControlControl

clock signals feeding “BIST ready” netlistclock signals feeding “BIST ready” netlist

BIST BIST clockclock

Embedded clock controlEmbedded clock control

Capture waveformCapture waveformgenerator for clk1generator for clk1

Shift clock generatorShift clock generator(Clock divider)(Clock divider)



clk1 - fastest PLL outputclk1 - fastest PLL output

clk1 - outclk1 - out



BIST clockBIST clock

InputsInputsfrom PLLfrom PLL

BIST RunBIST RunCapture windowCapture window

SummarySummary

Handling of multiple frequency and clock domains Handling of very high speed designs with on-chip

clocks At-speed test in every inter- and intra-clock domain Robust handling of clock skews through clock

suppression and hold state Separation of timing in loading-unloading and capture No simultaneous change of state and capture in

interacting domains without skew management At-speed test is possible without at-speed scan Power and ground bouncing can be managed by

clock suppression and staggering in shift

issues multiple clock domains multiple frequencies clock skew between clock domains on-chip pll...

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