issue 23: pld capacity and gate counting
TRANSCRIPT
Issue 23
Fourth Quarter 1996
GENERALFawcett: PLD Capacity .................................. 2
Guest Editorial: Software Strategies ........... 3
Customer Success Stories
FPGAs: Supercomputing Systems ........ 6
RC Company of the Quarter ................. 8
Xilinx Joins VSI Alliance ................................. 9
New AppLINX CD-ROM ............................... 9
Financial Results ............................................ 10
New Product Literature ............................... 10
Upcoming Events .......................................... 10
WebLINX and SmartSearch ........................ 11
Training Update ............................................. 12
First Hands-On Workshopon Reconfigurable Computing .............. 12
PRODUCTSNew XC9500 ISP Products in Production .. 13
XC4000 Family Update:5 Million Units Sold .................................. 13XC4000EX Family Begins Production .. 13
Xilinx Discontinuance Policy ...................... 14
XC4000A/H FPGA Devices Discontinued . 14
DEVELOPMENT SYSTEMSNew CPLD Software Updates ................... 15
VITAL Model Support for CPLDs ............. 15
HW-130 Update ............................................ 15
HINTS & ISSUESImplementing Median Filters ..................... 16
XC9500 ISP on the HP3070 ...................... 17
Downloading wtih Embedded Processor ... 18
Technical Support Resources .................... 19
Running XACTstep Under Windows NT .... 20
Technical Questions & Answers ......... 22-23
Component Availability Chart ............. 24-25
Programming Support Charts .............. 26-27
Alliance Program Charts ........................ 28-30
Development Systems Chart ..................... 31
Fax Response Form ....................................... 32
The ProgrammableLogic CompanySM
Inside This Issue:
T H E Q U A R T E R L Y J O U R N A L F O R X I L I N X P R O G R A M M A B L E L O G I C U S E R S
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FAX in Your Comments and SuggestionsTo: Brad Fawcett, XCell Editor Xilinx Inc. FAX: 408-879-4676
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New AppLINXCD-ROM Released!
Downloading CPLDs Withan Embedded ProcessorAn embedded processor can be used to controlCPLD programming, resulting in considerableflexibility throughout the product life cycle...
See Page 18
5,000,000 and CountingThe world’s most popular FPGA, the XC4000 Series, hits two milestones...5M units shipped and the first production of the XC4000EX family...
See Page 13
The latest AppLINX CD-ROM contains a collectionof applications and product information useful fordesigners working with Xilinx devices...
See Page 9
DESIGN TIPS & HINTS
XC9500 CPLDs inVolume ProductionFour members of the in-system-programmable XC9500 CPLD familyare ready for designers looking for thebest ISP solution...
See Page 13
GENERAL FEATURES
PRODUCT INFORMATION
Xilinx wishes you and your family
a happy and healthy holiday season!
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FROM THE FAWCETT
PLD Capacity&‘Gate Counting’By BRADLY FAWCETT ◆◆◆◆◆ Editor
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XCellPlease direct all inquiries,comments and submissions to:
Editor: Bradly Fawcett
Xilinx, Inc.2100 Logic DriveSan Jose, CA 95124Phone: 408-879-5097FAX: 408-879-4676E-Mail: [email protected]
©1996 Xilinx Inc.All rights reserved.
XCell is published quarterly forcustomers of Xilinx, Inc. Xilinx, theXilinx logo and XACT are registeredtrademarks; all XC-designatedproducts, XACTstep, LogiCore,Foundation Series, Alliance Series,NeoCAD, FastFLASH, and EZTag aretrademarks; and “The ProgrammableLogic Company” is a service mark ofXilinx, Inc. All other trademarks arethe property of their respective owners.
2
Continued on page 5
Every user of programmable logic atsome point faces the question, “How large adevice will I require to fit my design?”
One of the most diffi-cult problems facing thoseof us who make, marketand sell programmablelogic devices is establish-ing meaningful capacitymetrics for our devices.We would like to supplypotential users withmetrics that provide anaccurate indication of the
amount of logic that can be implementedwithin a given CPLD or FPGA device, and,at the same time, reflect the relative capac-ity of our devices compared to other manu-facturers’ competing products. Unfortunately,these two goals are often at odds with oneanother. In fact, a look at the density claimsthat I see in some PLD advertisementsthese days reminds me of the old sayingthat there are three types of falsehoods -lies, damned lies and statistics.
Of course, what is a problem for us isalso a problem for potential programmablelogic users, who must sift through the com-peting claims of the various vendors and tryto select the most cost-effective solution fortheir application.
At the root of the problem is the multi-plicity of available programmable logicarchitectures. Since each family of devicestends to have a unique architecture for itslogic resources, direct comparisons, such asmerely counting the number of availablelogic blocks or macrocells, are not alwayssufficient. (However, in some instances,direct comparisons of available resourcesprobably could be used a bit more oftenthan I think they are).
Most vendors, including Xilinx, describedevice capacities in terms of “gate counts”— the number of 2-input NAND gates thatwould be required to implement the samefunction. This metric has the advantage ofbeing familiar to ASIC designers and, intheory, allows the comparison of program-mable logic device capacities to those oftraditional, mask-programmed gate arrays.
But FPGA and CPLD devices do notconsist of arrays of 2-input NAND gates;they have structures such as look-up tables,multiplexers and flip-flops for implementinglogic functions. Thus, “counting gates” is farfrom an exact science; different vendorsapply varying methodologies to determinegate counts.
All too often, gate counting becomes agame of “one-upmanship” among compet-ing vendors. In fact, it seems to me thatsome marketeers decide what gate capacitythey want to claim, and then design theirmetrics to reach that number. For example,in ancient times (that is, a couple of yearsago), one of our competitors was bringing alarge FPGA to market with a claimed ca-pacity of 22,000 gates; the device had evenbeen named to reflect that claim. ThenXilinx announced and started sampling the“25,000 gate” XC4025. Suddenly, the com-peting device somehow “grew” an addi-tional 4,000 gates and was renamed andbrought to market as a “26,000 gate” FPGA.
With the advent of FPGAs like theXC4000 Series that offer on-chip memoryas well as logic resources, the issue isfurther complicated by the use of “memorygates” in addition to “logic gates”. Each bitof memory counts as four gates. This factorcan quickly inflate gate counts. For ex-ample, a single 4-input look-up table (LUT)
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GUEST EDITORIAL
3
30
One Size Does Not Fit All:Development System Products & Strategies
by KENN PERRY ◆ Director of Software Marketing
One design tool configuration cannot meet the needs of all program-mable logic designers. Overall, today’s designers are looking for top-down,language-driven design support that enables system-level integration withintheir programmable logic design methodologies. However, user requirementsand expectations vary considerably, dependent on their design methodologies,cost considerations and time-to-market pressures.
Xilinx is addressing the needs of the low-, mid- and high-density classes ofdesigners with three XACTstep™ software solutions: the Foundation Series™,Alliance Series™ and System Level Integration (SLI)™ options. Thus, Xilinx userscan choose between a complete, tightly integrated design system supportingindustry-leading HDLs, schematic capture and simulation (the FoundationSeries), or the integration of Xilinx implementation tools into their chosen EDAenvironment, leveraging defacto industry standards (the Alliance Series). Addition-ally, comprehensive system-level design is supported by SLI options, such asLogiCore™ modules, that enable users to achieve high density and performancewhile greatly reducing time-to-market. These products are available today.
Foundation SeriesDesigners of low-density FPGAs and CPLDs, the largest group of users, typically
are cost-sensitive and prefer easy-to-use, push-button, integrated software solutionsthat support both schematic and language-based entry methods. Intolerant ofdelays, defects or risks, these users desire a complete, “shrink-wrapped” solution.The Foundation Series solutions provide the technological “foundation” upon whichsupport for higher-density Xilinx devices can be built.
Xilinx is the first programmable logic vendor to offer a low-cost, shrink-wrappedsolution that integrates schematic entry, HDL synthesis and gate-level simulation forboth CPLDs and FPGAs. The goal of the Foundation Series solution is to provide anenvironment where the user can open the box, install the software, get up-to-speedquickly and complete designs successfully without assistance — although support isreadily available if needed. From a single environment, users have access to HDLsynthesis (VHDL and ABEL initially), schematic entry, gate simulation and core imple-mentation tools, making PLD development simple and easy without compromisingdesign flexibility or performance. The Xilinx continuum of software functionality anddevice technology enables users to expand their Foundation Series system capabilitieswith the changing demands of their design requirements.
Alliance Series and the Alliance ProgramThe mainstream segment of programmable logic, encompassing mid-range den-
sity users (10K to 15K gates), is the fastest growing segment in the programmable logicmarket. With decreasing market windows and increasing technology demands, main-
Continued on the next page
❝Xilinxis addressing the needs
of the low-, mid- and
high-density classes of
designers.❞
XILINX ALLIANCE-EDA CONTACTS-NOVEMBER 1996COMPANY NAME CONTACT NAME PHONE NUMBER E-MAIL ADDRESS
Accolade Design Automation Dave Pellerin (800) 470-2686 [email protected]
ACEO Technology, Inc. Ray Wei (510) 656-2189 [email protected]
Acugen Software, Inc. Nancy Hudson (603) 881-8821
Aldec David Rinehart (702) 456-1222 x12 [email protected]
ALPS LSI Technologies, Inc. David Blagden 441489571562
Alta Group Paul Ekas (408) 523-4135 [email protected]
Aptix Corporation Henry Verheyen (408) 428-6209 [email protected]
Aster Ingenierie S.A. Christopher Lotz +33-99537171
Cadence Ann Heilmann (408) 944-7016 [email protected]
Capilano Computing Chris Dewhurst (604) 522-6200 [email protected]
Chronology Corporation MikeMcClure (206) 869-4227 x116 [email protected]
CINA-Computer Integrated Network Analysis Brad Ashmore (415) 940-1723 [email protected]
Compass Design Automation Marcia Murray (408) 474-5002
Epsilon Design Systems, Inc. Cuong Do (408) 934-1536 [email protected]
Escalade Rod Dudzinski (408) 654-1651
Exemplar Logic Shubha Shukla (510) 337-3741 [email protected]
Flynn Systems Matt Van Wagner (603) 598-4444 [email protected]
Fujitsu LSI Masato Tsuru +81-4-4812-8043
Harmonix Corporation Shigeaki Hakusui (617) 935-8335
IK Technology Co. Tsutomu Someya +81-3-3839-0606 [email protected]
IKOS Systems Brad Roberts (408) 366-8509 [email protected]
INCASES Engineering GmbH Christian Kerscher +49-89-839910 [email protected]
ISDATA Ralph Remme +49-72-1751087 [email protected]
Logic Modeling Corp. (Synopsis Division) Marnie McCollow (503) 531-2412 [email protected]
Logical Devices Chip Willman (303) 279-6868 [email protected]
Memec Design Services Maria Agular (602) 491-4311 [email protected]
Mentor Graphics Sam Picken (503) 685-1298 [email protected]
MINC Kevin Bush (719) 590-1155
Minelec Marketing Department +32-02-4603175
Model Technology Greg Seltzer (503) 526-5465 [email protected]
OrCAD Mike Jingozian (503) 671-9500 [email protected]
Protel Technology Luise Markham (408) 243-8143
Quad Design Technology, Inc. Britta Sullivan (805) 988-8250
SimuCad Richard Jones (510) 487-9700 [email protected]
Sophia Sys & Tech Tom Tilbon (408) 232-4764
Summit Design Corporation Ed Sinclair (503) 643-9281
Synario Design Automation Jacquelin Taylor (206) 867-6257 [email protected]
Synopsys Lynn Fiance (415) 694-4289 [email protected]
Synplicity, Inc. Alisa Yaffa (415) 961-4962 [email protected]
Teradyne Mike Jew (617) 422-3753 [email protected]
Tokyo Electron Limited Shige Ohtani +81-3-334-08198 [email protected]
TopDown Design Solutions Art Pisani (603) 888-8811
Trans EDA Limited James Douglas +44-703-255118
VEDA DESIGN AUTOMATION INC Kathie O’Toole (408) 496-4515
Veribest Mike O’Donohue (303) 581-2330 [email protected]
Viewlogic John Dube (508) 480-0881 [email protected]
Visual Software Solutions, Inc. Riky Escoto (800) 208-1051 [email protected]
Zuken Makato Ikeda +81-4-594-27787
Zycad Charlene Locke (510) 623-4451 [email protected]
Inquiries about the Xilinx Alliance Program can be e-mailed to [email protected]
Changes since last issue (XCell 22) printed in color. • The following two entries deleted: ITS, The Rockland Group
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EMERALDRUBY
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996-2
OF 24
GUEST EDITORIAL
Continued fromthe previous page stream designers have critical business issues to
solve. To remain competitive in today’s market-place, they have developed their own designmethodologies employing tools and technologyprovided by EDA vendors. They prefer toleverage their previous investments and experi-ences by using the appropriate combination oftools from their EDA and programmable logicsuppliers. Therefore, it is critical that theirprogrammable logic design solutions aretightly-integrated with their established meth-odologies and support industry standards. TheAlliance Series, based on the industry’s mostpowerful set of third-party EDA integration
solutions and partnerships, pro-vides the benefits of an “opensystem”. Alliance Series productssupport industry standard designinterfaces, such as EDIF, VHDL,Verilog and LPM, and allowdesigners to create and verifydesigns in their chosen third-party EDA environment.
Through the Xilinx AllianceProgram, integrated design solu-tions for the design of Xilinx de-
vices are available from a broad array of third-party EDA suppliers. The Alliance Program isstructured to assure that Xilinx users have accessto the widest variety of high-quality third-partytools, certified to work with Xilinx products.Currently, the Xilinx Alliance Program includesmore than 100 partners, representing over 160products, who have been selected for their contri-bution to Xilinx development and their respon-siveness to customer needs. The Alliance Programsupports these partners with technical informationand assistance on an ongoing basis and, in turn,the partners provide Xilinx with input regardingproduct interfaces and directions.
System Level Integration (SLI)High-density users, typically the early
adopters, require leading-edge technology tohelp solve their very large, complex and per-formance-driven design problems. These usersfocus on advanced functionality and need thenewest, most advanced technologies. As pro-
grammable logic devices increase in density,designing at the gate level is no longer a real-istic approach.
SLI tools go far beyond just delivering supportfor higher-gate-count designs. Xilinx SLI optionsfacilitate the design of system-level functions inhigh-density, high-performance programmablelogic devices. Intended as “add-ons” to the Alli-ance and Foundation Series products, current SLItools include the LogiCore modules. LogiCoremodules are fully-verified, drop-in system levelmodules, such as target and initiator PCI businterfaces. These tools can dramatically shortendesign cycles and facilitate complex, system-levelintegration within programmable logic devices.
Next Generation Core Software PlatformThe upcoming upgrade to the XACTstep
software platform incorporates our next-gen-eration core software environment, leveragingthe industry-leading technologies from themerger between Xilinx and NeoCAD. Thisnew core technology includes timing-drivenoptimization, mapping, FPGA placement androuting and CPLD fitting algorithms; it will bethe software platform for all existing and fu-ture Xilinx IC product development and sup-port. This new release will still incorporatemany aspects of the popular XACTstep version6 software environment, providing users withan easy migration path and protecting previ-ous tool and training investments.
In summary, upcoming releases of theXACTstep product series are being developed toinclude the latest technological advancements,including enhanced SLI product offerings, value-added EDA technologies and additional Xilinxdevice support.. These advancements will deliverincreased ease-of-use benefits for rapid designimplementation flows, enhanced integration andhigh-quality results. In addition, Xilinx integratededucational tools will round out the technologiesbeing delivered.
Future programmable logic design solutionsfrom Xilinx will place more emphasis on mak-ing users of programmable logic better overallsystem designers, as well as ensuring rapiddesign implementation into Xilinx silicon. ◆
❝The upcomingupgrade to the
XACTstep softwareplatform incorporatesour next-generation
core software.❞ Dia
mon
d: T
hese
par
tner
s ha
ve s
trong
stra
tegi
c re
latio
n-sh
ips
with
Xili
nx a
nd h
ave
a di
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impa
ct o
n ou
r re
-le
ases
. Typ
ical
ly, X
ilinx
is d
irect
ly in
volv
ed in
the
deve
l-op
men
t and
test
ing
of th
e in
terfa
ce to
XAC
Tste
p so
ftwar
efo
r th
ese
prod
ucts
.
Ruby
: The
se p
artn
ers
have
a h
igh
degr
ee o
f com
patib
ility
and
have
rep
eate
dly
show
n th
emse
lves
to b
e si
gnifi
cant
cont
ribut
ors
to o
ur u
sers
’ dev
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men
t sol
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Emer
ald:
Pro
ven
Xilin
x co
mpa
tibili
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Item
s th
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col
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The
follo
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was
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: The
Roc
klan
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.
29
28
5
Continued from page 2can account for anywhere from one tonine “gates” when used to implement alogic function, depending on the type offunction that is implemented. However,when that same look-up table is used as16 bits of ROM or RAM memory, it now isimplementing 16 x 4 = 64 “equivalentgates.” Thus, FPGA gate counts rapidlyinflate when the capacity metric assumes asignificant amount of on-chip memoryusage; it’s important to know what assump-tions about memory usage apply to aclaimed gate density in these devices.
For example, the device names in theXC4000E and XC4000EX families are basedon our “maximum logic gates” metric —a measure of logic capacity only thatassumes no memory usage. However, amajor competitor has named its competingfamily based on a metric they call “typicalgates” that includes both types of gates,and further assumes up to 35% on-chipmemory utilization. Superficially, basedon the device names alone, it appears thattheir devices are much larger than ours.However, even a cursory examination ofdevice resources reveals a quite differentstory. For example, their “20,000-gate”device includes 1,152 4-input look-uptables, 1,344 registers and a maximummemory capacity of 12K bits. In contrast,the Xilinx “13,000-gate” XC4013E includes1,152 4-input lookup tables, an additional576 3-input lookup tables, 1,536 registers,and a maximum memory capacity of18K bits.
This is not to say that Xilinx has not, attimes, been guilty of “gate-inflation.”. How-ever, we have been more consistent overthe years than most of our competitors. Werecently reviewed and slightly revised ourmethodology for assigning gate counts forXC4000 Series and XC5200 family FPGAs.The results of that effort can be seen in theproduct specifications included in our latestdata book. Xilinx application note #059,
“Gate Count Capacity Metrics for FPGAs,”explains our capacity metrics and themethodology used to obtain them; theapplication note can be viewed at ourWebLINX web site (www.xilinx.com).
Besides being subject to statisticalmanipulation, gate counts used as capac-ity metrics suffer from another severedrawback – they usually take only logicblock and on-chip memory resources intoaccount. Modern FPGAs include a host ofother important features. For example,architectural features in the XC4000 Seriesthat are not reflected in our capacitymetrics include wide-edge decoders, dedi-cated arithmetic carry logic, registers andlogic in the I/O blocks, global buffers andclock distributionnetworks, and internalthree-state buffers.These important fea-tures can considerablyboost the capacity andsystem integrationcapabilities of thesedevices.
Experienced CPLDand FPGA users realize that there can beconsiderable variation in the logic capac-ity of a given device dependent on factorssuch as how well the application’s logicfunctions match the target device’s archi-tecture, the efficiency of the developmenttools, and the knowledge and skill of thedesigner. So, my advice is to apply ahealthy dose of skepticism to CPLD andFPGA manufacturers’ gate count metrics(yes, even ours). Examine the assump-tions behind the “gate counting methodol-ogy.” Better yet, take the time to examineand compare all the internal resources ofthe various devices being considered for adesign. Fortunately, with a little experi-ence, most designers can get a goodintuitive feel for the logic capacity of thedevices that they use. ◆
❝Take the time toexamine and compare all the
internal resources of thevarious devices being
considered for a design.❞
THE FAWCETT (con’t)
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6
FPGA CUSTOMER SUCCESS STORY
Designers at Supercomputing SystemsAG (Zürich, Switzerland) took a novelapproach in designing the GigaBoosterparallel computer system — combiningmultiple processing elements built fromstandard components with a fast, low-
latency communicationscheme implemented inhardware. To implementthe critical communica-tions control logic, theychose the world’s leadingFPGA family — theXC4000 Series.
Based on the “alpha7,”a prototype system de-signed at the electronics
laboratory of the ETH (the Swiss FederalInstitute of Technology), the GigaBoosteris a parallel computer containing seven
individual processing elements (PEs) on asingle board. Each PE is constructed froma DECchip 21066 Alpha processor, oneMbyte of cache memory, up to 128 Mbytesof DRAM memory (256 Mbytes in the“root” PE), a SCSI controller, and twospecial registers that control clock, reset,interrupts and similar functions. Each PE isaccompanied by two banks of FIFO buff-ers dedicated to interprocessor communi-cation and connected to a common 72-bitbus. All the special registers and FIFObuffers are controlled by a central commu-nications controller realized within threeXC4013 FPGAs. All the PEs run the DigitalUNIX operating system, providing accessto over 3000 applications.
A new communications protocol calledIntelligent Communication was developed toprovide fast communications and communi-
cation control, enabling thesystem to take full advantage ofthe processing power in each PE.This protocol, implementeddirectly in hardware using theFPGAs, allows fast, low-latencydata exchange among the pro-cessors, and a programmingmodel with simple and efficientcode. The in-system program-mable nature of the XC4013FPGAs was key to the develop-ment of this protocol; duringdevelopment, various ap-proaches were tested and com-pared simply by reconfiguringthe FPGA devices.
In the original alpha7 sys-tem design, the communica-tions controller was squeezedinto just two XC4013 devices.
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Swiss Engineers Use FPGAs to Link
❝To implementthe critical communications
control logic, they chose the
world’s leading FPGA family
— the XC4000 Series.❞
26
7
PROGRAMMER SUPPORT FOR XILINX XC7200/XC7300 CPLDS — NOVEMBER 1996MANUFACTURER MODEL 7236A 7272A 7318 7336 7336Q 7354 7372 73108 73144
ADVANTECH PC-UPROGLABTOOL-48 V1.31A V1.31A V1.31A V1.31A V1.31A V1.31A V1.31A V1.31A
ADVIN SYSTEMS PILOT-U40 10.84B 10.84B 10.84B 10.84B 10.84BPILOT-U84 10.84B 10.84B 10.84B 10.84B 10.84B 10.84B 10.84B 10.84B 10.84B
B&C MICROSYSTEMS, INC. Proteus 1Q97 1Q97 1Q97 1Q97 1Q97 1Q97 1Q97 1Q97 1Q97
BP MICROSYSTEMS BP-1200 V3.15 V3.15 V3.15 V3.18 V3.15 V3.15 V3.15 V3.15BP-2100 V3.15 V3.15 V3.15 V3.18 V3.15 V3.15 V3.15 V3.15
DATAMAN DATAMAN-48 V1.30 V1.30 V1.30 V1.30 V1.30 V1.30 V1.30 V1.30
DATA I/O 2900 BBS BBS BBS BBS3900/AutoSite BBS BBS BBS BBS BBS BBS BBSUniSite BBS BBS BBS BBS BBS BBS BBS
DEUS EX MACHINA ENGINEERING XPGM V1.40 V1.40 V1.40 V1.40 V1.40 V1.40 V1.40 V1.40 V1.50
ELECTRONIC ENGINEERING TOOLS ALLMAX/ALLMAX+ V2.4U V2.4U V2.4U V2.4U V2.4U V2.4U V2.4U V2.4UMEGAMAX V1.1E V1.1E V1.1E V1.1E V1.1E V1.1E V1.1E V1.1E
ELAN 6000 APS DISQUALIFIED
HI-LO SYSTEMS RESEARCH All-03A V3.09 V3.09 V3.09 V3.09 V3.09 V3.09 V3.09 V3.09All-07 V3.09 V3.09 V3.09 V3.09 V3.09 V3.09 V3.09 V3.09
ICE TECHNOLOGY LTD Micromaster 1000/E V1.1 V1.1 V1.1 V1.1 V1.1 V1.1 V3.1 V1.1 V1.1Speedmaster 1000/E V1.1 V1.1 V1.1 V1.1 V1.1 V1.1 V3.1 V1.1 V1.1Micromaster LV V1.1 V1.1 V1.1 V1.1 V1.1 V1.1 V3.1 V1.1 V1.1Speedmaster LV V1.1 V1.1 V1.1 V1.1 V1.1 V1.1 V3.1 V1.1 V1.1
LEAP ELECTRONIC CO., LTD. LEAPER-10 V3.2 V3.2 V3.2 V3.2 V3.2 V3.2 V3.2 V3.2 V3.2LP U4 V2.1 V2.1 V2.1 V2.1 V2.1 V2.1 V2.1 V2.1 V2.1
LOGICAL DEVICES ALLPRO-88 DISQUALIFIEDALLPRO-88XR DISQUALIFIEDALLPRO-96 6.4.26 6.4.26 6.4.26 6.4.26 6.4.26 6.4.26 6.4.26 6.4.26Chipmaster 2000 V2.4U V2.4U V2.4U V2.4U V2.4U V2.4U V2.4U V2.4UChipmaster 6000 V1.31A V1.31A V1.31A V1.31A V1.31A V1.31A V1.31A V1.31AXPRO-1 DISQUALIFIED
MICROPROSS ROM9000
MQP ELECTRONICS SYSTEM 2000 Nov-96 Nov-96 Nov-96 Nov-96 Nov-96 Nov-96 Nov-96 Nov-96 Nov-96PIN-MASTER 48 Nov-96 Nov-96 Nov-96 Nov-96 Nov-96 Nov-96 Nov-96 Nov-96 Nov-96
NEEDHAM’S ELECTRONICS EMP20 V3.10 V3.10 V3.10 V3.10 V3.10 V3.10 V3.10 V3.10
SMS EXPERTOPTIMA
STAG ECLIPSE 6.4.26 6.4.26 6.4.26 6.4.26 6.4.26 6.4.26 6.4.26 6.4.26 6.8.9
SUNRISE T-10 UDPT-10 ULC
SUNSHINE POWER-100 V8.40 V8.40 V8.40 V8.40 V8.40 V8.40 V8.40EXPRO-60/80 V8.40 V8.40 V8.40 V8.40 V8.40 V8.40 V8.40
SYSTEM GENERAL TURPRO-1/FX V2.30 V2.30 V2.30 V2.30 V2.30 V2.30 V2.30 V2.30 V2.30MULTI-APRO V3.02 V3.02 V3.02 V3.02 V3.02 V3.02 V3.02 V3.02 V3.02
TRIBAL MICROSYSTEMS Flex-700 V3.09 V3.09 V3.09 V3.09 V3.09 V3.09 V3.09 V3.09TUP-300 V3.09 V3.09 V3.09 V3.09 V3.09 V3.09 V3.09TUP-400 V3.09 V3.09 V3.09 V3.09 V3.09 V3.09 V3.09
XELTEK SUPERPROSUPERPRO II 2.4B 2.4B 2.4B 2.4B 2.4B 2.4B 2.4B 2.4B 2.4BSUPERPRO II/P 2.4B 2.4B 2.4B 2.4B 2.4B 2.4B 2.4B 2.4B 2.4B
XILINX HW-130 1.14 1.04 1.15 1.15 1.06 1.16 1.07 1.07 1.02
Changes since last issue are noted in color. Note: The XC7200 and XC7300 CPLD charts have been combined since the last issue.
PROGRAMMER SUPPORT FOR XC9500 — NOVEMBER 1996 — TOP THREE BY REGION
UNITED STATES EUROPE SOUTHEAST ASIA/JAPAN
MANUFACTURER DATE MANUFACTURER DATE MANUFACTURER DATE
BP MICROSYSTEMS 11/15/96 DATA I/O NOW DATA I/O NOW
DATA I/O NOW SMS 12/31/96 SYSTEM GENERAL 12/15/96
LOGICAL DEVICES 12/15/96 STAG 1/17/97 HI-LO 11/6/96
XILINX HW-130 V3.02 XILINX HW-130 V3.02 XILINX HW-130 V3.02
Supercomputing ProcessorsIn the GigaBooster system, the controllerwas redesigned into three XC4013 FPGAs toallow room for expansion. One FPGA holdsseveral small state machines, an abundanceof control registers, and other glue andinterface logic; this design uses about half ofthe available logic blocks, but all of the I/Opins. The other two FPGAs implement thelogic directly involved in the gathering andredistribution of data from the processingelements, including a 42-bit counter and alarge register/comparator file for each PE.The first of theseFPGAs is morethan 90% utilized,and connects tofive of the processing elements.
About 40% of the second FPGA containsthe identical logic for the remaining twoPEs. Additional logic is dedicated to moni-toring the communications behavior ofapplications running on the system, and theremainder of this FPGA can be used tosupport a module slot for an additionalprocessing element or an interface to anoptical high-speed network. The XC4000architecture’s built-in carry logic was criticalto attaining acceptable performance fromthe large counters and comparators in thisimplementation. The design runs at 20 MHz.
The FPGA designs were developedon a Sun workstation using Viewlogic’sPowerview tools and the XACT® develop-
ment system. This combination “forms avery comfortable development environ-ment,” according to Hansruedi VonderMüehll, the design engineer at the SwissFederal Institute of Technology who wasresponsible for the original design of thecommunications controller. Somefloorplanning was required, and both func-tional and timing simulation were used todebug and verify system operation.
The FPGA’s readback capability alsowas exploited during system debug, and isnow used to “dump” the state of the
communications controller in the event ofa communication failure. Using readback,the values of internal counters, registers,and state machines can be extractedand analyzed.
In summary, the use of reconfigurableXC4013 FPGAs was key to the imple-mentation of interprocessor communicationprotocols directly in hardware, as opposedto the more-traditional software approaches.The resulting high-performance communi-cations management allows the system totap the full processing power of each of itsAlpha processors, delivering 1.6 Gigaflopsof peak performance in an affordable andcompact system. ◆
❝The use of reconfigurable XC4013 FPGAs was
key to the implementation of interprocessor communication
protocols direclty in the hardware.❞
25
8ability, and hardware-implemented parallelprocessing. It’s a sophisticated, highlyportable architecture based on Xilinxreconfigurable FPGAs and banks of high-speed RAM.
As the tendency towards more complexDSP systems continues to grow, designersare constantly seeking new ways to reachhigher performance and to unravel bottle-necks while reducing development costs.“What is unique with our X-CIM is itsimplementation in an IEEE standard andoff-the-shelf product packaging,” notedMiroTech President and CEO PierrePopovic. “The X-CIM module can deliveracceleration up to 100 times that of a gen-eral-purpose DSP processor for highlyrepetitive ‘inner loops’ within algorithms.”
The marriage of the X-CIM module withSpectrum’s products allows the design ofvery compute-intensive systems whilestaying within Spectrum’s C40 environmentand DSP development tools. X-CIM mod-ules are supported by a comprehensivesuite of software tools referred to asCOREKIT. With these tools, developerscan transparently accelerate a wide rangeof DSP functions in applications such asradar, sonar, voice and image processing.
For more information on the X-CIMproduct line, contact MiroTechMicrosystems Inc. at 514-956-0060 orat [email protected]. ◆
PIN
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6
NOVEMBER 1996
PLASTIC LCC PC44
PLASTIC QFP PQ44
PLASTIC VQFP VQ44
CERAMIC LCC WC44
PLASTIC DIP PD48
PLASTIC VQFP VQ64
PLASTIC LCC PC68
CERAMIC LCC WC68
CERAMIC PGA PG68
PLASTIC LCC PC84
CERAMIC LCC WC84
CERAMIC PGA PG84
CERAMIC QFP CQ100
PLASTIC PQFP PQ100
PLASTIC TQFP TQ100
PLASTIC VQFP VQ100
TOP BRZ. CQFP CB100
CERAMIC PGA PG120
PLASTIC PGA PP132
CERAMIC PGA PG132
PLASTIC TQFP TQ144
CERAMIC PGA PG144
CERAMIC PGA PG156
PLASTIC PQFP PQ160
CERAMIC QFP CQ164
TOP BRZ. CQFP CB164
PLASTIC PGA PP175
CERAMIC PGA PG175
PLASTIC TQFP TQ176
CERAMIC PGA PG184
CERAMIC PGA PG191
TOP BRZ. CQFP CB196
PLASTIC PQFP PQ208
METAL MQFP MQ208
HI-PERF QFP HQ208
CERAMIC PGA PG223
PLASTIC BGA BG225
WINDOWED BGA WB225
TOP BRZ. CQFP CB228
PLASTIC PQFP PQ240
METAL MQFP MQ240
HI-PERF QFP HQ240
CERAMIC PGA PG299
HI-PERF. QFP HQ304
PLASTIC BGA BG352
CERAMIC PGA PG411
PLASTIC BGA BG432
CERAMIC PGA PG499
PLASTIC BGA BG596
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◆ = Product currently shippingor planned
❖ = New since last issue of XCell
RC COMPANY OF THE QUARTER
Our congratulations to the develop-ment team at MiroTech Microsystems Inc.(Montreal, Canada). MiroTech Micro-systems has released a commercial prod-uct that uses reconfigurable computing toadvance the state-of-the-art for DSP accel-
eration. At the most recentICSPAT/DSP World Exposition inBoston, MiroTech Microsystemsannounced an exclusive NorthAmerican agreement withSpectrum Signal ProcessingInc. to distributeMiroTech’s FPGA-basedDSP acceleration mod-ule. MiroTech’s X-CIMmodule complementsSpectrum’s exten-sive PCI, VXI andVME C4x-basedDSP productline. Togetherthese prod-ucts provide
substantial acceleration forselected compute-intensive, high-perfor-mance applications.
X-CIM is an FPGA-based reconfigurablecomputer in a TIM form factor that isfully-compliant with Texas Instruments’TMS320C40 DSP processor. The modulefeatures 80 Mbytes/s communication portbandwidth, 30 ms on-the-fly reconfigur-
MiroTech Microsystems:Real-Time Reconfigurability for DSP Acceleration
The Xilinx Reconfigurable Computing Developer’s Program is promot-
ing the commercial use of FPGAs in reconfigurable computing applica-
tions. These systems add significant value by dynamically changing
FPGA designs, in real-time, while the system is operating. Applications
that can exploit the benefits of the RC concept include graphics and
image processing, audio processing, and data communications.
For more information on the XilinxDeveloper’s Program and our recon-figurable computing efforts, please seeour web site at www.xilinx.com, or callJohn Watson at 408-879-6584.
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Xilinx LogiCore Alliance), and reusablemodules from his/her previous designs.
SLMs from all sources will be designedto common standards, much like physicalcomponents that are mixed-and-matchedtoday on a printed circuit board. TheseVSI-compliant SLMs can be viewed as“virtual components” that, throughcommon interface standards, fit quicklyinto “virtual sockets.” In order to rapidlyprovide a solution, the design data stan-dards will be based on open formatscommonly supported by all EDA vendors.
High-quality SLMs are a key componentfor high-performance and high-density pro-grammable logic design. The use of pre-defined and pre-verified SLMs can dramati-cally reduce system development cost andtime, resulting in faster time-to-market and agreater competitive advantage.
For further information about the VSIAlliance, see their web site at www.ip-net.org. For additional information about theLogiCore products and LogiCore AllianceProgram, see the WebLINX web site atwww.xilinx.com/products/logicore/logicore.htm. ◆
PIN
S
TY
PE
CO
DE
XC
30
20
A
XC
30
30
A
XC
30
42
A
XC
30
64
A
XC
30
90
A
XC
30
20
L
XC
30
30
L
XC
30
42
L
XC
30
64
L
XC
30
90
L
XC
31
42
L
XC
31
90
L
XC
31
20
A
XC
31
30
A
XC
31
42
A
XC
31
64
A
XC
31
90
A
XC
31
95
A
XC
40
03
E
XC
40
05
E
XC
40
06
E
XC
40
08
E
XC
40
10
E
XC
40
13
E
XC
40
20
E
XC
40
25
E
XC
40
28
EX
XC
40
36
EX
XC
40
44
EX
XC
40
52
XL
XC
40
62
XL
PLASTIC LCC PC44
PLASTIC QFP PQ44
PLASTIC VQFP VQ44
CERAMIC LCC WC44
PLASTIC DIP PD48
PLASTIC VQFP VQ64
PLASTIC LCC PC68
CERAMIC LCC WC68
CERAMIC PGA PG68
PLASTIC LCC PC84
CERAMIC LCC WC84
CERAMIC PGA PG84
CERAMIC QFP CQ100
PLASTIC PQFP PQ100
PLASTIC TQFP TQ100
PLASTIC VQFP VQ100
TOP BRZ. CQFP CB100
CERAMIC PGA PG120
PLASTIC PGA PP132
CERAMIC PGA PG132
PLASTIC TQFP TQ144
CERAMIC PGA PG144
CERAMIC PGA PG156
PLASTIC PQFP PQ160
CERAMIC QFP CQ164
TOP BRZ. CQFP CB164
PLASTIC PGA PP175
CERAMIC PGA PG175
PLASTIC TQFP TQ176
CERAMIC PGA PG184
CERAMIC PGA PG191
TOP BRZ. CQFP CB196
PLASTIC PQFP PQ208
METAL MQFP MQ208
HI-PERF QFP HQ208
CERAMIC PGA PG223
PLASTIC BGA BG225
WINDOWED BGA WB225
TOP BRZ. CQFP CB228
PLASTIC PQFP PQ240
METAL MQFP MQ240
HI-PERF QFP HQ240
CERAMIC PGA PG299
HI-PERF. QFP HQ304
PLASTIC BGA BG352
CERAMIC PGA PG411
PLASTIC BGA BG432
CERAMIC PGA PG475
PLASTIC BGA BG560
COMPONENT AVAILABILITY CHART
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48
64
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84
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120
132
144
156
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Xilinx Joins Virtual Socket Interface AllianceLast September, a group of more than
35 leading electronics firms announced theformation of the Virtual Socket Interface(VSI) alliance. This open alliance is dedi-cated to promoting the growth of the sys-tem level integration (SLI) chip industry bydeveloping the technical standards requiredto enable the “mix and match” of systemlevel modules (SLMs). Xilinx has enteredthe VSI alliance, and is actively participat-ing in standardization efforts affecting pro-grammable logic technologies. Our partici-pation augments our current programs forthe development of a diverse set of high-quality SLMs, called LogiCore™ modules, forthe various Xilinx FPGA and CPLD families.
The goal is to establish a set of openSLM design interface and productizationstandards. Through use of the developedstandards, design engineers will be able touse SLMs from several sources in the de-sign of highly-integrated programmablelogic devices. For example, a designercould construct a system combining SLMssupplied by Xilinx (such as the LogiCorePCI master/slave), SLMs from third-partyproviders (such as the members of the
New AppLINX CD-ROM ShippedAn updated AppLINX CD-ROM has
been shipped to all registered Xilinx users.The CD contains a complete collection ofXilinx applications and product informa-tion. Access to the AppLINX CD is anotherbenefit of maintenance support for theXilinx development system.
The AppLINX CD-ROM includes:• Updated September 1996 data book• All Xilinx application notes and their
corresponding design files• Development system documentation• The last six issues of the XCell journal• Adobe Acrobat® Reader™ with full
content-searching capabilities
• Presentation notes for the Xilinx 1996Fall Seminar
The AppLINX CD merges the best aspectsof the Xilinx WebLINX web site and the XilinxFTP site. Users with access to an HTMLbrowser can navigate the files quickly andeasily off-line, while links are available tofind the latest information on-line.
The AppLINX CD will be updated on aregular basis. Make sure you visit the XilinxWebLINX web site at www.xilinx.com forthe latest information.
Regarding the fall seminar, contact yourlocal Xilinx sales office to inquire about apresentation to your company. ◆
10
23
Learn about the newest Xilinx products and services through our extensive library ofproduct literature. The most recent pieces are listed below. To order or to obtain a com-plete list of all available literature, please contact your local Xilinx sales representative. ◆
New ProductLiterature
Corporate
Product Overview Brochure Features & Benefits 0010130-05Software Solutions Brochure Features & Benefits 0010304
TITLE DESCRIPTION NUMBER
Design SuperConJan. 21–23Santa Clara, California
ACM/SIGDA 5th InternationalSymposium on FPGAsFeb. 9–11Monterey, California
International IntegratedCircuits ConferenceMarch 13–14Beijing, China
Look for Xilinx technical papers and/or product exhibits at these upcoming industryforums. For further information about any of these conferences, please contact KathleenPizzo (Tel: 408-879-5377 FAX: 408-879-4676). ◆
UPCOMING EVENTS
Intellectual Propertyin ElectronicsSeminarMarch 17–18Santa Clara, California
SemiconductorSolutionsMarch 18–20Birmingham,United Kingdom
InternationalIntegrated CircuitsConferenceMarch 17–18Shanghai, China
European Designand Test ConferenceMarch 17–20Paris, France
FINANCIAL RESULTS
QWhat is happening whenQuicksim issues this warning
on every primitive in a design:// Warning: Instance
’/GIVE_ME_AN_E’// Could not find a
registered simulation modelwith label: ’xc4000’
// NULL model will beinserted. (from: Analysis/Digital/SimulationUtilities/Dsim 85)
This is caused by an incorrectly-writtensimulation viewpoint for the design, whichcan result when a design is retargeted to anew device family. The solution is to delete
that default viewpoint, then runPLD_DVE_SIM on the design, specifyingthe correct part family. If done from thecommand line, an XC4000 design, forexample, might use:
delete_objectblanking_design/default
pld_dve_sim blanking_designxc4000
Note: If Timsim8 -o was used to createthe simulation model, be sure to runTimsim8 instead of PLD_DVE_SIM.Timsim8 -o runs PLD_DVE_SIM, then addslinks to timing information into the view-point afterwards.
Runscript for compiling the XC4000/XC4000EBSCAN Verilog Example:
PART = 4025ehq240-3TOP = example
read -format verilog “bscan4k.v”
set_port_is_pad “*”insert_pads
set_dont_touch u1set_dont_touch u2set_dont_touch u3set_dont_touch u4set_dont_touch u5
compile
replace_fpga
set_attribute TOP “part” -type stringPART
write -f xnf -h -o “bscan4k.sxnf”
For the first time, Xilinx Inc. quarterlysales revenues declined from both theprior quarter and the year ago period.Revenues for the September-ending quar-ter were $130.6 million, a decrease of13.1% from the immediately precedingquarter and 7.5% from the same quarterone year ago.
“The September quarter was a difficultquarter for the overall programmable logicindustry and Xilinx in particular,” statedCEO Wim Roelandts. “We believe thisrevenue shortfall can be attributed toseveral factors, including increased pres-sure from selected customers to reduce
their own inventory, a seasonably weakersummer quarter in Europe, and new cus-tomer programs that have not ramped upas quickly as initially forecasted.”
Roelandts continued, “However, we areencouraged by the nearly 1,400 new soft-ware seats that we sold this quarter, 70%of which are versions of our new, shrink-wrapped, low-cost Foundation™ software,”Roelandts added. “We are also optimisticthat our new XC9500 and XC4000EX fami-lies will provide meaningful contributionsto revenues before our fiscal year end.”
Xilinx Inc. stock is traded on NASDAQunder the symbol XLNX. ◆
ADifficultQuarter
MentorGraphics(continued)
SynopsysQHow are Boundary Scan com-ponents for the XC4000 family
instantiated in Verilog-based designs?
To use Boundary Scan components inXC4000 Series devices, instantiate theboundary scan symbol (BSCAN) and theassociated dedicated I/O. Use the“dont_touch” attribute; otherwise, BSCAN
may be deleted by the Synopsys compiler.The Verilog code for instantiating
BSCAN in the XC4000 is shown below.VHDL and Verilog examples for both theXC4000 and XC5000 can be found on theXilinx Web site (www.xilinx.com), or canbe emailed to users via the Xdocs mailserver (email [email protected]).
XC4000/XC4000E example ofinstantiating the BSCAN symbol:
module example (a,b,c);
input a, b;output c;reg c;
wire tck_net;wire tdi_net;wire tms_net;wire tdo_net;
BSCAN u1 (.TDI(tdi_net), .TMS(tms_net),.TCK(tck_net), .TDO(tdo_net));
TDI u2 (.I(tdi_net));TMS u3 (.I(tms_net));TCK u4 (.I(tck_net));
TDO u5 (.O(tdo_net));
always@(posedge b)c<=a;
endmodule
22
11
That’s it! This will create an agent thatwill notify you whenever Xilinx posts anew application note to the site. Remem-ber that you can create an agent for any-thing you can search for, and they are notlimited to the Xilinx site. ◆
WebLINX (www.xilinx.com) hasbecome a popular stopping place on theinformation superhighway. Based on recenttraffic reports, more than 5,000 people visitthe Xilinx World Wide Web site eachweek. Some of the most popular areas ofour web include SmartSearch, ProductInformation pages, Application Notes andthe Data Book page.
We’re constantly adding new informa-tion to WebLINX. In fact, over the last fewmonths we have added many new applica-tion notes and application briefs to the site,as listed here.
If you are interested in keeping up-to-date with new technical information beingposted to WebLINX, then SmartSearchAgents are for you. A SmartSearch Agentwill automatically notify you via e-mailwhen a document of interest to you isposted to any of the 50 or so sites that weindex. For example, you can create aSmartSearch Agent that will alert you re-garding any new application notes postedto the Xilinx site by following these steps:
WebLINX and SmartSearchAgents Keep You Up-to-Date
1. Using your browser, go towww.xilinx.com
2. Click on the “Register Now for Agents!”hyperlink near the bottom of the page.
3. Click on the “register” hyperlink4. Fill out the registration questionnaire.5. After you have successfully registered
for Agents, go to SmartSearch byclicking on the SmartSearch logo ortext at the bottom of the page.
6. Click on the “Xilinx Only” link.7. Leave the text box blank but select the
“application notes” check box.8. Click on the Start Search button. On the
results page, in the upper right corneris a text box with the label “AgentName:”
9. Type “Xilinx Application Notes” into theagent name box and click on the CreateAgent button.
The following XAPP application notes and XBRF application
briefs have recently been added to WebLINX. You can find
these by first going to the application notes page and
selecting XAPP application notes or application briefs.
• XAPP051 Synchronous/Asynchronous FIFOs
• XAPP052 Efficient Shift Registers, LFSR Counters, etc.
• XAPP053 Implementing FIFOs in XC4000 Series RAM
• XAPP054 Constant Coefficient Multipliers for the XC4000E
• XAPP055 Block Adaptive Filter
• XAPP056 System Design with New XC4000EX I/O Features
• XAPP057 Using Select-RAM Memory in XC4000 Series FPGAs
• XAPP058 XC9500 In-System Programming Using an 8051 Microcontroller
• XAPP059 Gate Count Capacity Metrics for FPGAs
• XAPP060 Design Migration from XC4000 to XC5200
• XAPP062 Design Migration from XC4000 to XC4000E
• XAPP063 Interfacing XC6200 to Microprocessors (MC68020 Example)
• XAPP064 Interfacing XC6200 to Microprocessors (TMS320C50 Example)
• XAPP065 XC4000 Series Edge-Triggered and Dual-Port RAM Capability
In addition, the following application notes have been updated:
• XAPP013 Using the Dedicated Carry Logic in XC4000E
• XAPP018 Estimating the Performance of XC4000E Adders and Counters
Xilinx Application Briefs are technical papers describing
the advantages of Xilinx products, especially versus
alternative solutions:
• XBRF001 XC4000E Select-RAM: Flexibility with Speed
• XBRF002 XC4000E Low Power Consumption: At High Speed
• XBRF003 XC4000E Select-RAM: Maximum Configurability
• XBRF005 XC4000EX Routing: A Comparison with XC4000E and ORCA
• XBRF006 PLL Design Techniques and Usage in FPGA Design
• XBRF007 XC4000-Series FPGAs: The Best Choice for Delivering Logic Cores
• XBRF009 XC9500 Pin Locking Capability and Benchmarks
TECHNICAL QUESTIONS & ANSWERS
QBesides the CD-ROM supplied withthe product, are there any sources
of additional information about usingthe Xilinx Foundation Series software?
The Foundation Documentation UpdatePack contains application notes about the
Foundation Logic Simulator, FoundationXVHDL compiler, and a new simulationtutorial. Get FND_DOC1.EXE (self-extract-ing ZIP file) from the Xilinx FTP site(ftp.xilinx.com/pub/swhelp/foundation) orthe Xilinx BBS (Software Help ➡ Aldec).
Foundation
ENWrite (Mentor’s EDIF netlister) looksat the XC4000 version of OFD in the sche-matic. This component has attached to it aCOMP=OFD property, indicating that thiscomponent is a primitive and should bewritten as such in the EDIF file. EDIF2XNFthen takes this primitive description andlooks for the corresponding ofd.eds file inthe $LCA/data/unified/edif4000e directory,that contains EDIF descriptions forXC4000E primitives. Since OFD is not aprimitive in the XC4000E family, theofd.eds file does not exist in the directory,resulting in the error.
The correct OFD from the XC4000Elibrary has no COMP=OFD property at-tached to it, since the COMP property isreserved for primitives. Therefore, if thecorrect XC4000E component had beenused, ENWrite would have written out thehierarchy below OFD. Then, EDIF2XNFwould have never seen the OFD “primi-tive” and would have never tried to lookfor a non-existent ofd.eds file in theXC4000E data directory.
The proper way to retarget the designto a new device family is to use the Con-vert Design utility in PLD_DA before run-ning the implementation flow. ConvertDesign replaces the library components ina schematic or set of schematics so thatthey come from the proper library. Forinstructions on how to use Convert Design,see Solution 798, “Retargeting a design inMentor Design Architect (Convert Design),”from the Xilinx Solutions Database:
http://www.xilinx.com/techdocs/798.htm
MentorGraphics QCan XACTstep 5.2.1 be used with
Mentor Graphics’ B.x release?
A: Under Mentor B.x, Gen_sch8 andXBLXGS may fail with either “call to un-defined procedure” (SunOS) or “unresolvedpropagate symbol” (HP-UX) error messagesdue to problems with dynamically linkingto Mentor’s Design Data Port (DDP). Apatch is available to fix these problems andmake XACTstep 5.2.1 interface smoothlywith Mentor B.x. The patch may be down-loaded from the Xilinx FTP site at:
ftp://ftp.xilinx.com/pub/swhelp/mentor/b1_521s.tar.Z(SunOS)
ftp://ftp.xilinx.com/pub/swhelp/mentor/b1_521h.tar.Z(HP-UX)
QA schematic originally targetedfor the XC4000 family is now
targeting an XC4000E device. DuringMen2XNF8, the following erroroccurs when running EDIF2XNF:
Error: 6 EDIF data “ofd.eds”not found in directory“/usr/xact/data/unified/edif4000e”
In this case, the schematic was createdusing the XC4000 library, but the design isnow targeted to an XC4000E device. (Otherfamily combinations may also cause thiserror.) Certain symbols are primitives in theschematic library with which the design wasbuilt (XC4000), but are macros in the libraryassociated with the device being targeted(XC4000E). In this example, OFD is a primi-tive in the XC4000 library but is a macro inthe XC4000E library (since it has, under-neath it, the clock-enabled OFDX symbol).
21
12
site at ftp://ftp.xilinx.com/pub/swhelp/xact-pc and on our BBS (408-559-9327) inthe Software Help ➡ XACT-PC area. Thename of the file is PREP_NT.ZIP. Afterunzipping this file, place the XNFPREP.EXEfile in C:\XACT, overwriting the existingXNFPREP.EXE. This new version, 5.2.1c,fixes a bug where the .PRP file would notbe written.
Setting the EnvironmentNext, you must modify the environment
variables. Keep in mind that you must haveadministrator privileges to modify existingsystem environment variables and to adddrivers.
In the Main program group, double-click on Control Panel and then System(NT 3.51) or right click on My Computer(NT 4.0). In the System Environment Vari-ables area, select Path. In the Value field atthe bottom of the screen, add
C:\XACT;C:\WVOFFICE;
before the existing path, so it looks likeC:\XACT;C:\WVOFFICE;<rest_of_path>.
Hit the Set button, then create a new vari-able; the Variable is XACT and the Value is
C:\XACT;C:\WVOFFICE
Then bring C:\WINNT\SYSTEM32\AUTOEXEC.NT into a text editor. Add thisline at the end:
SET XACT=C:\XACT;C:\WVOFFICE
You can verify that these settings havebeen applied (after rebooting Windows NT)by typing SET in the DOS window. Leave allthe C:\WVOFFICE statements out if you arenot using the Workview Office tools.
DriversNext, you must install the Rainport
driver, which is also located on our FTPsite at ftp://ftp.xilinx.com/pub/swhelp/xact-pc and on our BBS in the SoftwareHelp ➡ XACT-PC area. The file is calledRAINPORT.EXE. This driver is required toenable Windows NT to recognize the
hardware key. The RAINPORT.EXEcontains a readme about how toinstall the driver. This driver can alsobe found in the SENTINEL directory onthe Workview Office 7.2 CD. ChooseControl Panels ➡ Drivers ➡ Add toinstall this. This version is only for usewith Windows NT 3.51.
Windows NT 4.0 users will install thenewer version of Rainport mentioned inthe Windows Setup section. A readmewithin the ZIP file explains how to installthis driver.
Running the toolsYou will be running the tools in an
MS-DOS session. Take a look at theReference Guide Volumes 1, 2 and 3 forspecific information about using thesetools in a DOS environment.
You will see that some of the Windowstools will work. Besides the SimulationUtility and the Memory Generator, youcan create a new icon for the TimingAnalyzer. The Command Line for this toolis c:\xact\timingan.exe and the WorkingDirectory is c:\xact. There have beencases where these Windows tools havehad problems, and the workaround is touse the DOS equivalent. Tools that willnot work are the Design Manager, FlowEngine, and Floorplanner.
If you have any problems using theAdobe Acrobat reader, you can downloada copy of Acrobat 2.1 for Windows 95/NTfrom their Web site, www.adobe.com/acrobat/windows.html.
Hopefully, these hints will get you upand running within your Windows NTenvironment. There are some differenceswith different installations of WindowsNT, so results may certainly vary. Pleasekeep in mind that these tools were neverintended to run in Windows NT, but ifyou do run into problems, please contactXilinx Technical Support for assistance. ◆
One-Day VHDL Seminar Now Available
TECHNICAL TRAINING UPDATE
seminars have been added to the scheduleto meet demand.
Each attendee receives an evaluation kitof the Xilinx software. This provides ampleopportunity to practice the skills and know-ledge obtained at the seminar. The kitincludes the Foundation Series software, anintegrated tool set of schematic entry, VHDLsynthesis, functional and timing simulationand design implementation tools – every-thing needed to create an entire design.
Xilinx, its distributors and representa-tives, together with Esperan, are sponsor-ing these seminars. Contact your localXilinx representative to inquire aboutVHDL training seminars in your area.
In related news, electronics distributorsHamilton Hallmark, Marshall and Insightare in the process of creating VHDL work-shops as well. In each case, Xilinx FPGAdevices and the Foundation Series toolshave been selected for use in the labexercises. ◆
Updated TrainingCourses Available
The basic Xilinx technical trainingcourses have been updated to reflect allthe features of the latest developmentsoftware. XACTstep™ version 6.0.1 softwareis fully incorporated into the schematic-based design course. The course examinesa complete design scenario for the Foun-dation Series software user. The updatedsynthesis-based design course providesVHDL/Verilog designers with an intimateworking knowledge of the XACTstepv5.2.1/6.0.1 synthesis software. Both ofthese courses are available worldwide.
The current schedule of schematic-and synthesis-based courses, as well ascourse registration information, can befound at the WebLINX web site(www.xilinx.com). ◆
Xilinx is sponsoring a series of one-day introductory VHDL seminars conducted
by qualified instructors fromEsperan Inc. Esperan specializesin technical training and haseducated thousands of VHDLusers since 1992. This one-daycourse, a must for new users,emphasizes the basics of theVHDL language.
A full day of lecture andhands-on labs, the seminaruses the VHDL tool of-fered by Xilinx in theFoundation Series™. The
tuition fee is $99. Feedback from partici-pants has been extremely positive; extra
First Hands-On Workshop onReconfigurable ComputingThe Xilinx University Program (XUP) has had an active training
schedule with nine recent workshops in four countries. XUP workshopsare designed to train university instructors on the basics of usingprogrammable logic for undergraduate courses, graduate courses andresearch.
In addition to the standard workshops, and in response to a grow-ing interest in dynamically-reconfigurable logic, a unique, leading-edgeworkshop was held at Cornell University (Ithaca, NY).
The Cornell workshop was the first to examine both the hardwareand software issues associated with dynamically-reconfigurable com-puting, including hands-on laboratory exercises. Participating lecturersincluded representatives from Xilinx, the Virginia Institute of Technol-ogy, ETZ Zurich, Cornell University, and Imperial College (UK). Mr.Nick Treddinick, an IEEE fellow, presented the keynote address.
Xilinx is committed to addressing the needs of the reconfigurablelogic market, and the Xilinx University Program is committed to furtheracademic support of this exciting area of study. Proceedings from theworkshop are available to XUP participants, and further informationabout this workshop and future XUP workshops can be obtained on theweb at www.xilinx.com/programs/univ.htm. ◆
Windows NT Environment
VHDL SEMINAR ATTENDEES LEARN:
• The benefits of using VHDL design
to reduce time-to-market
• VHDL’s general structure and syntax
• How to write good VHDL code that
will synthesize efficiently
• How to effectively target CPLD and
FPGA architectures
• How to implement state machines,
combinatorial logic and arithmetic
functions in VHDL
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Running XACTstep™ v5.2.1 in a
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PRODUCT INFORMATION-COMPONENTS
New XC9500 ISP Products in Volume Production
Five Million and CountingXC4000 device #5,000,000 shipped in September.
The recipient, Acuson Corporation, a manufacturer ofmedical electronics systems, was featured at a com-memoration ceremony.
Since its introduction in the early 1990s, theXC4000 family has quickly grown to become theworld’s most successful FPGA product line. The addi-tion of XC4000E devices (and now the XC4000EXversions) to the product family have acceleratedXC4000 unit shipments since mid-1994, when thefamily reached the million-unit milestone.
“As medical technology continues to advance at aphenomenal rate, the success of Acuson more andmore depends on our ability to design and deliver thebest products possible in the shortest amount of time,”stated Robert Gallagher, Acuson president. “TheXC4000 has greatly contributed to our technologicalvision and has helped us provide cost-effective solu-tions for the needs of our dynamic marketplace. Weare delighted to share in the XC4000’s success.” ◆
Please contact your local Xilinx sales representative for furthertechnical information, price and availability information, or requestsfor samples of these new ISP CPLD products. ◆
Four new XC9500 ISP (In-SystemProgrammable) CPLD devices are now involume production. The XC9536, XC9572,XC95108 and XC95216 CPLDs are readyfor designers looking for the best, most-flexible ISP solution. These 36-, 72-, 108-and 216-macrocell devices, respectively,feature fast, guaranteed performance, theindustry’s best pin-locking architecture, atrue JTAG-compliant interface, and ad-vanced flash memory technology with upto 10,000 program/erase cycles. Theresulting benefits include reduced overallcosts, faster time-to-market and the flex-ibility needed to make design changesanytime during the product life cycle.
Feature XC9536 XC9572 XC95108 XC95216
Macrocells 36 72 108 216Usable Gates 800 1600 2400 4800tPD
(ns) 5/7.5/10/15 7.5/10/15 7.5/10/15 10/15/20Registers 36 72 108 216Pin-locking ✓ ✓ ✓ ✓JTAG (1149.1) ✓ ✓ ✓ ✓Max. User I/Os 34 72 108 166
Packages PC44/VQ44PC84 PC84
PQ100/TQ100 PQ100/TQ100PQ160 PQ160
HQ208
THE XC4000 SERIES OF FPGAS:
XC4000EX Family Enters ProductionThe world’s most popular FPGA series just got bigger! Xilinxbegan shipments of production-qualifed XC4036EX devices inNovember. The XC4036EX offers 36,000 maximum logic gates anda typical gate range (logic and memory) of 22,000 to 65,000 gates.Planned devices in the XC4000EX family will range from 28,000 to128,000 logic gates.
The XC4000EX FPGAs contain all the advanced features of thepopular XC4000 and XC4000E architectures. However, severalsignificant enhancements to the architecture address the routing,clock distribution, and I/O needs of higher density devices (SeeXCell #20, page 21).
Development system software for the XC4000EX family willstart shipping in late December. The initial software offering willsupport Synopsys, Mentor Graphics and Viewlogic EDA environ-ments, as well as workstations from Sun (both SunOS and Solaris)and HP. Please contact your local Xilinx sales representative forthe latest availability status. ◆
this self-extracting file in a temporarydirectory and run it in DOS. It will expandlots of files into this directory. Then,within Windows NT 3.51, choose File ➡Run Update.exe from within this tempo-rary directory and the update installprogram will run.
Windows NT 4.0: You will need todownload two items from the RainbowTechnologies Web site. (Rainbow Tech-nologies is the manufacturer of the hard-ware key.) At their site, www.rnbo.com/tech/drivers/drivers.htm, download“Patch for Windows NT 4.0” and “RainportDriver for Windows NT”. The formeris a single executable, NTVDM.EXE.Replace the existing version in yourC:\WINNT\SYSTEM32 directory andreboot. This file will be included inWindows NT 4.0 Service Pack 1 whenit is built. The latter is the Rainport driverthat is explained in the Drivers section.
InstallationThe first thing that must be done is the
Xilinx install; simply perform a Windowsinstall. Assuming that D:\ is your CDdrive, just select File ➡ Run (or Start ➡Run) and type D:\Wn1\Install\Winstall.exeat the prompt. If you are using Viewlogictools that support Windows NT,(Workview Office, NOT PROseries),choose the DS-VL-STD-PC1 product (notthe Stand-alone) from a Custom install.Select the products you would like toinstall, but keep in mind that you will beusing the DOS tools, so programs like theFloorplanner should be de-selected.Change the target path so the interfacetools are copied to C:\WVOFFICE insteadof C:\PROSER.
Next, copy the kernel32.dll file fromD:\PROSER to both C:\XACT andC:\WVOFFICE.
Then, install the patched version ofXNFPREP. This file is located on our FTP
XACTstep™ version 6.0.x (theWindows tools) was compiled and testedfor Windows 3.x. It was not compiled forWindows NT. Unlike Windows 95, there
is no work-aroundto enable theWindows tools towork. This releasedoes NOT supportWindows NT.
However, wehave had somesuccess usingXACTstep v5.2.1 (theDOS tools) within aDOS session underWindows NT. Thereare a few things thatmust be done to set
up the environment, as described below.Please note that the next full release of
Xilinx software will support Windows NT4.0. The solution described here should beconsidered a tactical work-around forWindows NT 3.51 and a temporary work-around for Windows NT 4.0.
All of the instructions apply to bothWindows NT versions 3.51 and 4.0, unlessotherwise noted.
Windows SetupWindows NT 3.51: Make sure that
your Windows NT 3.51 is up-to-date withthe latest set of patches and bug fixes,known as Service Pack 4. To check thestatus of your system, open the Adminis-trative Tools program group and double-click on the Windows NT Diagnosticsicon. Select the OS Version button andcheck the number next to Service Pack. Ifit is less than 4, you will need to upgrade.This free upgrade can be found atMicrosoft’s Web site: www.microsoft.com/kb/softlib/winnt.htm. Select “ServicePacks” then “Windows NT 3.51 ServicePack 4 for Intel (x86)” to download. Place
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Keeping Up with Changing StandardsThere are many benefits to embedded
in-system programming. Products can beupdated to the “leading edge” just beforeshipping and then updated in the field astechnology changes, rather than wait toship until all expected upgrades are com-plete. For example, this capability couldallow a manufacturer to ship productsbased on new and evolving standardsbecause once a standard has been estab-lished, previously shipped systems can beupdated in the field to maintain compli-ance (see Figure 1).
To accommodate potential field up-grades, choose a CPLD device with arobust architecture to ensure that amplespeed and capacity are available to toler-ate future changes. The XC9500 architec-ture is specifically designed to tolerate awide range of changes while retaining thepinouts initially dictated by the PCB de-sign. By choosing the right XC9500 deviceand including embedded programmingcapabilities in the system, embeddeddownload success is assured.
During its first 12 years, Xilinx hascontinued to maintain every componentproduct line it successfully introduced. Wetake pride in that. However, as processesmigrate to smaller geometries with lowercosts, and architectures continue to im-prove, the economics of overlapping prod-ucts dictates that some product life cyclesshould end.
We are aware that IC users are verywary of product obsolescence. All toooften, products are discontinued as a resultof business decisions that do not ad-equately include the customers’ perspec-tive. To ensure that we get it right the firsttime we discontinue a product, Xilinx hastaken a different approach and solicitedcustomer input to assist in designing ourproduct obsolescence program.
Our goal is to provide users with amplenotification of product discontinuancesand ensure adequate supplies of affectedproducts for as long as possible. The pro-gram includes “customer advisory” noticesas a preview of future product changesand discontinuances, generous last-time-buy periods to allow ample planning and/
or redesign time, and relationships withend-of-life suppliers that ensure productavailability beyond the Xilinx last-time-buyand last-time-ship periods.Xilinx Product Discontinuance Policy —The Xilinx Product Discontinuance Policyaddresses two situations—where a replace-ment device exists (PDN1) and where areplacement does not exist (PDN2).
PDN1 — When a form, fit, function replace-ment exists, the last-time-buy (LTB) period isone year and last-time-ship is 90 days afterthe LTB period. The one-year period shouldprovide ample time for users to determine ifthey prefer to exercise a last-time buy or re-qualify with the replacement device.
PDN2 — When no form fit or functionreplacement exists, the last-time-buy is twoyears to allow users the time necessary tocompletely redesign the board or perform adetailed analysis of LTB requirements.
End-of-Life Supplier — At the end of PDN1or PDN2, all remaining inventory will beshipped to an end-of-life supplier. The sup-plier will be able to deliver Xilinx discontin-ued products to those users that choose notto exercise the last-time-buy option, or havean unexpected need.
In summary, Xilinx has attempted totake a user-sensitive approach to productobsolescence. Early notification, extendedlast-time-buy periods and the use of end-of-life suppliers give the user a variety ofoptions to explore and ease any problemsresulting from a product discontinuance.
Your comments and suggestions re-garding this policy are welcome. Pleasesend all comments to Daniel Chan, XilinxMarketing, at [email protected]. ◆
Xilinx To Discontinue Older XC4000A/H FPGA Devices
ProductObsolescence
Policy
Xilinx has announced that it will stop production oftwo families of field programmable gate arrays devices in1997 — the XC4000A and the XC4000H families (oldervariations of the XC4000 Series of products). The XC4000E,XC4000EX and XC4000D families will not be affected.
Users of these devices can replace them withnewer Xilinx XC4000E and XC5200 FPGA family products;these newer devices provide footprint-compatible solutions
with substantial cost and performance advantages overthe older devices.
This marks the first obsolescence of mature Xilinx FPGAdevices, and it begins the implementation of one of theindustry’s most customer-friendly product discontinuationpolicies. Last-time orders to buy the XC4000A and XC4000Hdevices will be accepted until September 30, 1997. Last-timeshipments will be made until March 31, 1998. ◆
XILINX OBSOLECESNCE POLICYNotify Last Time
Form, Fit Obsolete to Last Buy (LTB)and Function Ordering Time Buy to Last TimeAlternative Code (LTB) Ship (LTS) Example
PCN* (Product Product XC4000Change Notice) Yes No changes after process
90 days† migration
PDN 1 (Product XC4000A/HDiscontinuance Yes Yes 1 year 90 days discon-Notification) tinuation
PDN 2 No Yes 2 years 90 days
*Specification control document (SCD) available to stay with old product for one year.†90 days from latter of qualification data or evaluation sample availability.
Embedded Download App NoteXilinx has developed the tools needed
to deliver this powerful capability todesigners. The package includes a thor-oughly tested, transportable C program, adetailed application note on its use, andthe Xilinx EZTag™ software. The designwas initially developed for an 80C51-typemicrocontroller, but the processor-specificaspects are kept to a minimum, with asimple assembler level call. This keeps allJTAG protocols at the fully transportableANSI C level, for which there is anabundance of available compilers. Thepackage covers all the necessary details,including the conversion of intermediatefiles to formats compatible with EPROMprogrammers.
To obtain the embedded downloadapplication note and software, simplyaccess the WebLINX web site atwww.xilinx.com and look for theCPLD applications section. Alternately,make your request via e-mail [email protected]. ◆
TECHNICAL SUPPORT RESOURCES
X-TALK: The Xilinx Network of Electronic Services
E-mail addresses for questions on specific applications:Digital Signal Processing applications ........................... [email protected] applications .......................................................... [email protected] and Play ISA applications ....................................... [email protected] card applications ....................................... [email protected] Transfer Mode applications ................ [email protected] Computing applications ............ [email protected] Programmable CPLD applications ............... [email protected] Serial Bus applications .................................... [email protected]
Xilinx home page on the World Wide Web ... www.xilinx.com.
Electronic Technical Bulletin Board (U.S.) ........... 408-559-9327
XDOCS E-mail document server- send an E-mail [email protected] with ‘help’ as the only item in the subjectheader. You will automatically receive full instructions via E-mail.
XFACTS fax document server available by calling 408-879-4400.
HOTLINE SUPPORT, U.S.
Customer Support Hotline: 800-255-7778Hrs: 8:00 a.m.-5:00 p.m. Pacific time
Customer Support Fax Number: 408-879-4442Avail: 24 hrs/day-7 days/week
E-mail Address: [email protected]
Customer Service*: 408-559-7778, ask for customer service
* Call for software updates, authorization codes, documentation updates, etc.
HOTLINE SUPPORT, INTERNATIONAL
Germany, Munich Officetelephone: (49) 89 991 54930fax: (49) 89 904 4748e-mail: [email protected]
Japan, Tokyo Officetelephone: (81) 3 3297 9163fax: (81) 3 3297 0067e-mail: [email protected]
UK, London Officetelephone: (44) 1932 820821fax: (44) 1932 828522Bulletin Board Service:
(44) 1932 333540e-mail: [email protected]
France, Paris Officetelephone: (33) 1 3463 0100fax: (33) 1 3463 0959e-mail: [email protected]
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PRODUCT INFORMATION-DEVELOPMENT SYSTEMS
With its FastFLASH™ technologysupporting up to 10,000 program/erasecycles, Xilinx XC9500 CPLDs bring all theadvantages of in-system programming(ISP) to an advanced CPLD architecture.Embedded processors can be used tocontrol CPLD in-system programming,resulting in considerable benefits through-out the product life cycle, from initialdesign to field updates.
Why embedded downloading?Generally, designers download their
CPLD patterns through a serial port drivenfrom a PC or workstation during systemdevelopment and debug. Once the designis stable and high-volume production
begins, production-level programming canbe switched to third-party programmers(such as those from Data I/O and BPMicrosystems) or third-party ATE systems(such as those from HP, GenRAD andTeradyne). Increasingly, however, design-ers need to program parts directly usingthe onboard microprocessor in an embed-ded system.
Having the microprocessor handledesign changes on its “own” board fits the“embedded” paradigm. Embedded systemsshould be designed with a single, unifiedinformation port for the programming ofall reconfigurable devices on the board. In
the case of CPLD devices, the most-frequently used access port is the JTAGboundary scan interface (that same portcan provide “double duty” as both a pro-gramming and test access port).
With the embedded processor control-ling the JTAG interface, the board’s CPLDscan be reconfigured by providing newprogramming information to the processor.As a result, changes can be easily imple-mented during design, prototyping, manu-facturing or in the field. With sufficientprior planning, extensive design changescan be implemented (if needed) withoutmaking external physical changes in thesystem, such as modifications to the printedcircuit board — perhaps even withoutopening the system enclosure!
This approach allows changes after fieldinstallation with minimal risk to overallsystem behavior. End users can update theirown hardware. For systems with a floppydisk or CD drive, field upgrades can beimplemented just like a software update.Remote updating is possible using a modemor other communication link — the embed-ded controller would capture update infor-mation from an external data stream andchannel it to the ISP CPLDs on the board,as well as on-board flash memories (orvolatile memories).
The non-volatile XC9500 CPLDs do notneed reloading with each power cycle.However, because they can coexist in thesame JTAG download chain with FPGAs, itmay be easier and more convenient toreload their configurations during everypower-up sequence. The 10,000 reprogram-ming cycles offered by XC9500 CPLDFastFLASH™ technology makes that strategypossible. By using the advanced JTAG capa-bilities contained in the XC9500 devices, theinternal UserCode register can maintain areprogramming counter, if needed.
New CPLD Software Updates
HW-130 Device Programmer Update
New device support and enhance-ments have been added to the XilinxXC9500 CPLD software. Both the corefitter and EZTag™ download software havebeen enhanced to support XC9500 CPLDfamily designs.
The latest updates feature:1. JEDEC programming file generation for
the newest member of the XC9500family, the XC9572-7.
2. Refined fitter optimization algorithmsfor improved fitting efficiency
3. Netlist reader improvements to acceptExemplar™ generated netlists
4. ISP algorithm enhancements5. Faster download time from a PC
The names of the enhanced fitter and EZTag files:
Platform Fitter File EZTag File
PC FITTERPC.ZIP EZTAG_PC.ZIP
Sun FITTERSN.TAR.Z EZTAG_SN.TAR.Z
HP FITTERHP.TAR.Z EZTAG_HP.TAR.Z
The PC files are accessible from the Xilinx BBS and FTP sites:BBS: Software Help ➡ CPLD Software
FTP: ftp://ftp.xilinx.com/pub/swhelp/cpld
Since the UNIX versions of these files are compressed for the conve-nience of our workstation users, they are available only on the FTP site.A detailed description of each file is contained in CPLD.LST, also lo-cated at these sites. Download these files NOW to take advantage ofthe industry’s best software for the industry’s best pin-locking CPLD. ◆
board systems. Several other programmermanufacturers have scheduled XC9500family support in late 1996 and early 1997.The XC9500 family has been added to thecharts located near the back of this news-letter that list programmers supportingXilinx products. ◆
We work closely with third-partyprogrammer manufacturers to supportour products with standard programmersolutions. Our own HW-130 programmerfor Xilinx SPROMs and CPLDs supportssystem development and low-volumeprogramming requirements.
Updated HW-130 interface software isnow available for both PC and work-station platforms (DOS, Windows 3.1,Windows 95, Windows NT, Sun OS,Solaris, HP9000/700 and IBM RS6000environments). Users can download thefiles from the bulletin board system, orrequest the upgrade by contacting a localXilinx sales representative. The upgrade isfree-of-charge to current HW-130 owners.
Programming support for the XC9500family is available now on the HW-130 forthe XC9536 and the XC95108 CPLD de-vices. The XC9500 family also is supportedby BP Microelectronics’ and Data I/O’slatest updates, available from their bulletin
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VITAL Model Support for XC9500 CPLDs
VITAL model support for the XC9500 CPLD family is now
available from Topdown Design Solutions. These models allow the
designer to generate timing-accurate, gate-level VHDL from Xilinx
XNF files. VBAK/VITAL models are designed to work with the Model
Technology V-System simulator. These models are designed, imple-
mented, sold and supported by Topdown Systems.
For additional information, contact Topdown Systems
by telephone at 800-438-8435 or by electronic mail at
[email protected]. Topdown Systems’ web site is located
at www.topdown.com. ◆
Downloading CPLDs with an Embedded Processor
Figure 1: Simplehardware interface forfield upgrades.
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DESIGN HINTS AND ISSUES
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The median filter is a popular imageprocessing technique for removing saltand pepper (“shot”) noise from images.With this technique, the eight direct neigh-bors and center point of a sliding 3-by-3array are examined. The median value ofthe nine elements replaces the originalcenter pixel. The median of the 3-by-3array is the fifth element in the sorted listof nine elements; thus, the algorithmrequires a high-speed sort of the ninepixel values.
The graph of Figure 1 shows the mini-mum exchange network required to pro-
duce a medianfrom nine inputpixels by perform-ing a partial sort.Each node is a twoelement sort, withthe lower inputexiting the nodeon the left, thehigher input leav-ing on the right.The triangulargroups of nodesperform a full sorton three elements.
The high-speedcarry logic of theXC4000E FPGA is
used to implement an efficient compare/swap function. The carry logic in eachCLB is set up for an A-B subtract function,while the function generators are used toimplement a 2:1 multiplexer. The multi-plexer is controlled by the carry out of thesubtraction (Figure 2). Nodes where bothoutputs are used may be implemented innine CLBs (eight for the mux, 1/2 for carrychain initialization, and 1/2 for carry outtest); nodes where one output is discardedrequire only five CLBs.
Implementing Median Filters in XC4000E FPGAsby JOHN L. SMITH,
Univision Technologies Inc.,Billerica, MA
When the circuit is implemented,pipelining can be used so that only threepixels are clocked in at once, eliminatingtwo of the three full sort node groups at thetop of the graph (Figure 3). In a systemwith eight-bit pixels, total CLB usage for thisreal-time median sort circuit is 85 CLBs. ◆
Figure 1: Minimum exchangenetwork required to produce amedian from nine input pixelsby performing a partial sort
Figure 2: Using carrylogic to perform high-speed compare functions
XC9500 ISP on theHP3070 Tester
Generating an HP 3070 ISP ProgramUse the SVF file(s) as input to the
“gen_hp” tool. This tool takes the SVF file(s)and creates a complete HP3070 test program.
This tool runs on the HP workstationthat acts as the controller for the HP 3070.The “gen_hp” program translates the SVFfiles to the appropriate number of digitalVector Control Language (VCL) files. VCL isthe HP3070 stimulus description language.
After generating the VCL file, “gen_hp”invokes the HP 3070 “dcomp” compiler togenerate the “.o” object file from each VCLfile. The object file is the executable ATEused to perform ISP on a XC9500 device onthe HP3070.
The “gen_hp” program also creates atestplan file that drives the test program onthe HP 3070. This testplan file can then beincorporated into an existing testplan file tohave the in-system program-ming function executed at theappropriately chosen point inthe ATE test flow.
This software and methodol-ogy will also work on the fol-lowing HP testers: the HP3072,HP3073, HP3074, HP3075,HP3079CT, HP3172, HP3173 andHP3175 systems.
AvailabilityThe gen_hp software and
accompanying documentationis available via the XilinxWebLINX™ (www.xilinx.com) web site, FTPsite (/pub/swhelp/cpld) and BBS (SofwareHelp ➡ CPLD). The SVF to VCL translationtool is currently supported on HP700,SunOS 4.X, Windows NT and Windows 95platforms. ◆
With in-system-programming (ISP),programmable logic devices such asXC9500 CPLDs can be programmed andreprogrammed even though they aresoldered on a system board. ISP devicescan facilitate prototype development,streamline manufacturing flows andenable remote system updates.
The XC9500 family implements ISPfunctionality using the IEEE 1149.1 (JTAG)Test Access Port (TAP), and without requir-ing externally applied “supervoltages.”Thus, automatic test equipment (ATE) thatsupports the JTAG TAP can be used toprogram XC9500 CPLDs.
HP3070 Configuration and FixturingOne such ATE platform, the Hewlett
Packard HP3070 Board Test System, canperform ISP as an integrated part of themanufacturing test process. The XilinxEZTag™ software, the Xilinx-suppliedvector translation tool (gen_hp) and anHP3070 ATE system equipped with aControl-Plus card are required in orderto integrate XC9500 device programminginto the system test flow.
Using EZTag to Generate an SVF fileFirst, run EZTag to generate a Serial
Vector Format (SVF) file from the JEDECprogramming file of the target design. TheSVF file is in an ASCII format and describesTAP operations. The file encodes the entireprogramming algorithm for the selecteddevice in the system as a series of TAPinstructions. If a readback/verify operationis required after the program step, a sepa-rate SVF file with the verification vectorsspecified should be generated.
Procedure used to create an SVF file:1. Create the design using XABEL-
CPLD or any compatible third-partydesign entry tool.
2. Fit the design and save it to aJEDEC output file.
3. Invoke the EZTag software from theXACT® command line with the SVFoption specified.
4. Generate an SVF file to “program,”“erase” or “verify” the selected partin the boundary-scan chain.
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Figure 3: Pipelinefor clocking in threepixels at a time
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DESIGN HINTS AND ISSUES
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The median filter is a popular imageprocessing technique for removing saltand pepper (“shot”) noise from images.With this technique, the eight direct neigh-bors and center point of a sliding 3-by-3array are examined. The median value ofthe nine elements replaces the originalcenter pixel. The median of the 3-by-3array is the fifth element in the sorted listof nine elements; thus, the algorithmrequires a high-speed sort of the ninepixel values.
The graph of Figure 1 shows the mini-mum exchange network required to pro-
duce a medianfrom nine inputpixels by perform-ing a partial sort.Each node is a twoelement sort, withthe lower inputexiting the nodeon the left, thehigher input leav-ing on the right.The triangulargroups of nodesperform a full sorton three elements.
The high-speedcarry logic of theXC4000E FPGA is
used to implement an efficient compare/swap function. The carry logic in eachCLB is set up for an A-B subtract function,while the function generators are used toimplement a 2:1 multiplexer. The multi-plexer is controlled by the carry out of thesubtraction (Figure 2). Nodes where bothoutputs are used may be implemented innine CLBs (eight for the mux, 1/2 for carrychain initialization, and 1/2 for carry outtest); nodes where one output is discardedrequire only five CLBs.
Implementing Median Filters in XC4000E FPGAsby JOHN L. SMITH,
Univision Technologies Inc.,Billerica, MA
When the circuit is implemented,pipelining can be used so that only threepixels are clocked in at once, eliminatingtwo of the three full sort node groups at thetop of the graph (Figure 3). In a systemwith eight-bit pixels, total CLB usage for thisreal-time median sort circuit is 85 CLBs. ◆
Figure 1: Minimum exchangenetwork required to produce amedian from nine input pixelsby performing a partial sort
Figure 2: Using carrylogic to perform high-speed compare functions
XC9500 ISP on theHP3070 Tester
Generating an HP 3070 ISP ProgramUse the SVF file(s) as input to the
“gen_hp” tool. This tool takes the SVF file(s)and creates a complete HP3070 test program.
This tool runs on the HP workstationthat acts as the controller for the HP 3070.The “gen_hp” program translates the SVFfiles to the appropriate number of digitalVector Control Language (VCL) files. VCL isthe HP3070 stimulus description language.
After generating the VCL file, “gen_hp”invokes the HP 3070 “dcomp” compiler togenerate the “.o” object file from each VCLfile. The object file is the executable ATEused to perform ISP on a XC9500 device onthe HP3070.
The “gen_hp” program also creates atestplan file that drives the test program onthe HP 3070. This testplan file can then beincorporated into an existing testplan file tohave the in-system program-ming function executed at theappropriately chosen point inthe ATE test flow.
This software and methodol-ogy will also work on the fol-lowing HP testers: the HP3072,HP3073, HP3074, HP3075,HP3079CT, HP3172, HP3173 andHP3175 systems.
AvailabilityThe gen_hp software and
accompanying documentationis available via the XilinxWebLINX™ (www.xilinx.com) web site, FTPsite (/pub/swhelp/cpld) and BBS (SofwareHelp ➡ CPLD). The SVF to VCL translationtool is currently supported on HP700,SunOS 4.X, Windows NT and Windows 95platforms. ◆
With in-system-programming (ISP),programmable logic devices such asXC9500 CPLDs can be programmed andreprogrammed even though they aresoldered on a system board. ISP devicescan facilitate prototype development,streamline manufacturing flows andenable remote system updates.
The XC9500 family implements ISPfunctionality using the IEEE 1149.1 (JTAG)Test Access Port (TAP), and without requir-ing externally applied “supervoltages.”Thus, automatic test equipment (ATE) thatsupports the JTAG TAP can be used toprogram XC9500 CPLDs.
HP3070 Configuration and FixturingOne such ATE platform, the Hewlett
Packard HP3070 Board Test System, canperform ISP as an integrated part of themanufacturing test process. The XilinxEZTag™ software, the Xilinx-suppliedvector translation tool (gen_hp) and anHP3070 ATE system equipped with aControl-Plus card are required in orderto integrate XC9500 device programminginto the system test flow.
Using EZTag to Generate an SVF fileFirst, run EZTag to generate a Serial
Vector Format (SVF) file from the JEDECprogramming file of the target design. TheSVF file is in an ASCII format and describesTAP operations. The file encodes the entireprogramming algorithm for the selecteddevice in the system as a series of TAPinstructions. If a readback/verify operationis required after the program step, a sepa-rate SVF file with the verification vectorsspecified should be generated.
Procedure used to create an SVF file:1. Create the design using XABEL-
CPLD or any compatible third-partydesign entry tool.
2. Fit the design and save it to aJEDEC output file.
3. Invoke the EZTag software from theXACT® command line with the SVFoption specified.
4. Generate an SVF file to “program,”“erase” or “verify” the selected partin the boundary-scan chain.
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Figure 3: Pipelinefor clocking in threepixels at a time
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PRODUCT INFORMATION-DEVELOPMENT SYSTEMS
With its FastFLASH™ technologysupporting up to 10,000 program/erasecycles, Xilinx XC9500 CPLDs bring all theadvantages of in-system programming(ISP) to an advanced CPLD architecture.Embedded processors can be used tocontrol CPLD in-system programming,resulting in considerable benefits through-out the product life cycle, from initialdesign to field updates.
Why embedded downloading?Generally, designers download their
CPLD patterns through a serial port drivenfrom a PC or workstation during systemdevelopment and debug. Once the designis stable and high-volume production
begins, production-level programming canbe switched to third-party programmers(such as those from Data I/O and BPMicrosystems) or third-party ATE systems(such as those from HP, GenRAD andTeradyne). Increasingly, however, design-ers need to program parts directly usingthe onboard microprocessor in an embed-ded system.
Having the microprocessor handledesign changes on its “own” board fits the“embedded” paradigm. Embedded systemsshould be designed with a single, unifiedinformation port for the programming ofall reconfigurable devices on the board. In
the case of CPLD devices, the most-frequently used access port is the JTAGboundary scan interface (that same portcan provide “double duty” as both a pro-gramming and test access port).
With the embedded processor control-ling the JTAG interface, the board’s CPLDscan be reconfigured by providing newprogramming information to the processor.As a result, changes can be easily imple-mented during design, prototyping, manu-facturing or in the field. With sufficientprior planning, extensive design changescan be implemented (if needed) withoutmaking external physical changes in thesystem, such as modifications to the printedcircuit board — perhaps even withoutopening the system enclosure!
This approach allows changes after fieldinstallation with minimal risk to overallsystem behavior. End users can update theirown hardware. For systems with a floppydisk or CD drive, field upgrades can beimplemented just like a software update.Remote updating is possible using a modemor other communication link — the embed-ded controller would capture update infor-mation from an external data stream andchannel it to the ISP CPLDs on the board,as well as on-board flash memories (orvolatile memories).
The non-volatile XC9500 CPLDs do notneed reloading with each power cycle.However, because they can coexist in thesame JTAG download chain with FPGAs, itmay be easier and more convenient toreload their configurations during everypower-up sequence. The 10,000 reprogram-ming cycles offered by XC9500 CPLDFastFLASH™ technology makes that strategypossible. By using the advanced JTAG capa-bilities contained in the XC9500 devices, theinternal UserCode register can maintain areprogramming counter, if needed.
New CPLD Software Updates
HW-130 Device Programmer Update
New device support and enhance-ments have been added to the XilinxXC9500 CPLD software. Both the corefitter and EZTag™ download software havebeen enhanced to support XC9500 CPLDfamily designs.
The latest updates feature:1. JEDEC programming file generation for
the newest member of the XC9500family, the XC9572-7.
2. Refined fitter optimization algorithmsfor improved fitting efficiency
3. Netlist reader improvements to acceptExemplar™ generated netlists
4. ISP algorithm enhancements5. Faster download time from a PC
The names of the enhanced fitter and EZTag files:
Platform Fitter File EZTag File
PC FITTERPC.ZIP EZTAG_PC.ZIP
Sun FITTERSN.TAR.Z EZTAG_SN.TAR.Z
HP FITTERHP.TAR.Z EZTAG_HP.TAR.Z
The PC files are accessible from the Xilinx BBS and FTP sites:BBS: Software Help ➡ CPLD Software
FTP: ftp://ftp.xilinx.com/pub/swhelp/cpld
Since the UNIX versions of these files are compressed for the conve-nience of our workstation users, they are available only on the FTP site.A detailed description of each file is contained in CPLD.LST, also lo-cated at these sites. Download these files NOW to take advantage ofthe industry’s best software for the industry’s best pin-locking CPLD. ◆
board systems. Several other programmermanufacturers have scheduled XC9500family support in late 1996 and early 1997.The XC9500 family has been added to thecharts located near the back of this news-letter that list programmers supportingXilinx products. ◆
We work closely with third-partyprogrammer manufacturers to supportour products with standard programmersolutions. Our own HW-130 programmerfor Xilinx SPROMs and CPLDs supportssystem development and low-volumeprogramming requirements.
Updated HW-130 interface software isnow available for both PC and work-station platforms (DOS, Windows 3.1,Windows 95, Windows NT, Sun OS,Solaris, HP9000/700 and IBM RS6000environments). Users can download thefiles from the bulletin board system, orrequest the upgrade by contacting a localXilinx sales representative. The upgrade isfree-of-charge to current HW-130 owners.
Programming support for the XC9500family is available now on the HW-130 forthe XC9536 and the XC95108 CPLD de-vices. The XC9500 family also is supportedby BP Microelectronics’ and Data I/O’slatest updates, available from their bulletin
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VITAL Model Support for XC9500 CPLDs
VITAL model support for the XC9500 CPLD family is now
available from Topdown Design Solutions. These models allow the
designer to generate timing-accurate, gate-level VHDL from Xilinx
XNF files. VBAK/VITAL models are designed to work with the Model
Technology V-System simulator. These models are designed, imple-
mented, sold and supported by Topdown Systems.
For additional information, contact Topdown Systems
by telephone at 800-438-8435 or by electronic mail at
[email protected]. Topdown Systems’ web site is located
at www.topdown.com. ◆
Downloading CPLDs with an Embedded Processor
Figure 1: Simplehardware interface forfield upgrades.
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Keeping Up with Changing StandardsThere are many benefits to embedded
in-system programming. Products can beupdated to the “leading edge” just beforeshipping and then updated in the field astechnology changes, rather than wait toship until all expected upgrades are com-plete. For example, this capability couldallow a manufacturer to ship productsbased on new and evolving standardsbecause once a standard has been estab-lished, previously shipped systems can beupdated in the field to maintain compli-ance (see Figure 1).
To accommodate potential field up-grades, choose a CPLD device with arobust architecture to ensure that amplespeed and capacity are available to toler-ate future changes. The XC9500 architec-ture is specifically designed to tolerate awide range of changes while retaining thepinouts initially dictated by the PCB de-sign. By choosing the right XC9500 deviceand including embedded programmingcapabilities in the system, embeddeddownload success is assured.
During its first 12 years, Xilinx hascontinued to maintain every componentproduct line it successfully introduced. Wetake pride in that. However, as processesmigrate to smaller geometries with lowercosts, and architectures continue to im-prove, the economics of overlapping prod-ucts dictates that some product life cyclesshould end.
We are aware that IC users are verywary of product obsolescence. All toooften, products are discontinued as a resultof business decisions that do not ad-equately include the customers’ perspec-tive. To ensure that we get it right the firsttime we discontinue a product, Xilinx hastaken a different approach and solicitedcustomer input to assist in designing ourproduct obsolescence program.
Our goal is to provide users with amplenotification of product discontinuancesand ensure adequate supplies of affectedproducts for as long as possible. The pro-gram includes “customer advisory” noticesas a preview of future product changesand discontinuances, generous last-time-buy periods to allow ample planning and/
or redesign time, and relationships withend-of-life suppliers that ensure productavailability beyond the Xilinx last-time-buyand last-time-ship periods.Xilinx Product Discontinuance Policy —The Xilinx Product Discontinuance Policyaddresses two situations—where a replace-ment device exists (PDN1) and where areplacement does not exist (PDN2).
PDN1 — When a form, fit, function replace-ment exists, the last-time-buy (LTB) period isone year and last-time-ship is 90 days afterthe LTB period. The one-year period shouldprovide ample time for users to determine ifthey prefer to exercise a last-time buy or re-qualify with the replacement device.
PDN2 — When no form fit or functionreplacement exists, the last-time-buy is twoyears to allow users the time necessary tocompletely redesign the board or perform adetailed analysis of LTB requirements.
End-of-Life Supplier — At the end of PDN1or PDN2, all remaining inventory will beshipped to an end-of-life supplier. The sup-plier will be able to deliver Xilinx discontin-ued products to those users that choose notto exercise the last-time-buy option, or havean unexpected need.
In summary, Xilinx has attempted totake a user-sensitive approach to productobsolescence. Early notification, extendedlast-time-buy periods and the use of end-of-life suppliers give the user a variety ofoptions to explore and ease any problemsresulting from a product discontinuance.
Your comments and suggestions re-garding this policy are welcome. Pleasesend all comments to Daniel Chan, XilinxMarketing, at [email protected]. ◆
Xilinx To Discontinue Older XC4000A/H FPGA Devices
ProductObsolescence
Policy
Xilinx has announced that it will stop production oftwo families of field programmable gate arrays devices in1997 — the XC4000A and the XC4000H families (oldervariations of the XC4000 Series of products). The XC4000E,XC4000EX and XC4000D families will not be affected.
Users of these devices can replace them withnewer Xilinx XC4000E and XC5200 FPGA family products;these newer devices provide footprint-compatible solutions
with substantial cost and performance advantages overthe older devices.
This marks the first obsolescence of mature Xilinx FPGAdevices, and it begins the implementation of one of theindustry’s most customer-friendly product discontinuationpolicies. Last-time orders to buy the XC4000A and XC4000Hdevices will be accepted until September 30, 1997. Last-timeshipments will be made until March 31, 1998. ◆
XILINX OBSOLECESNCE POLICYNotify Last Time
Form, Fit Obsolete to Last Buy (LTB)and Function Ordering Time Buy to Last TimeAlternative Code (LTB) Ship (LTS) Example
PCN* (Product Product XC4000Change Notice) Yes No changes after process
90 days† migration
PDN 1 (Product XC4000A/HDiscontinuance Yes Yes 1 year 90 days discon-Notification) tinuation
PDN 2 No Yes 2 years 90 days
*Specification control document (SCD) available to stay with old product for one year.†90 days from latter of qualification data or evaluation sample availability.
Embedded Download App NoteXilinx has developed the tools needed
to deliver this powerful capability todesigners. The package includes a thor-oughly tested, transportable C program, adetailed application note on its use, andthe Xilinx EZTag™ software. The designwas initially developed for an 80C51-typemicrocontroller, but the processor-specificaspects are kept to a minimum, with asimple assembler level call. This keeps allJTAG protocols at the fully transportableANSI C level, for which there is anabundance of available compilers. Thepackage covers all the necessary details,including the conversion of intermediatefiles to formats compatible with EPROMprogrammers.
To obtain the embedded downloadapplication note and software, simplyaccess the WebLINX web site atwww.xilinx.com and look for theCPLD applications section. Alternately,make your request via e-mail [email protected]. ◆
TECHNICAL SUPPORT RESOURCES
X-TALK: The Xilinx Network of Electronic Services
E-mail addresses for questions on specific applications:Digital Signal Processing applications ........................... [email protected] applications .......................................................... [email protected] and Play ISA applications ....................................... [email protected] card applications ....................................... [email protected] Transfer Mode applications ................ [email protected] Computing applications ............ [email protected] Programmable CPLD applications ............... [email protected] Serial Bus applications .................................... [email protected]
Xilinx home page on the World Wide Web ... www.xilinx.com.
Electronic Technical Bulletin Board (U.S.) ........... 408-559-9327
XDOCS E-mail document server- send an E-mail [email protected] with ‘help’ as the only item in the subjectheader. You will automatically receive full instructions via E-mail.
XFACTS fax document server available by calling 408-879-4400.
HOTLINE SUPPORT, U.S.
Customer Support Hotline: 800-255-7778Hrs: 8:00 a.m.-5:00 p.m. Pacific time
Customer Support Fax Number: 408-879-4442Avail: 24 hrs/day-7 days/week
E-mail Address: [email protected]
Customer Service*: 408-559-7778, ask for customer service
* Call for software updates, authorization codes, documentation updates, etc.
HOTLINE SUPPORT, INTERNATIONAL
Germany, Munich Officetelephone: (49) 89 991 54930fax: (49) 89 904 4748e-mail: [email protected]
Japan, Tokyo Officetelephone: (81) 3 3297 9163fax: (81) 3 3297 0067e-mail: [email protected]
UK, London Officetelephone: (44) 1932 820821fax: (44) 1932 828522Bulletin Board Service:
(44) 1932 333540e-mail: [email protected]
France, Paris Officetelephone: (33) 1 3463 0100fax: (33) 1 3463 0959e-mail: [email protected]
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Running XACTstep™ v5.2.1 in a
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PRODUCT INFORMATION-COMPONENTS
New XC9500 ISP Products in Volume Production
Five Million and CountingXC4000 device #5,000,000 shipped in September.
The recipient, Acuson Corporation, a manufacturer ofmedical electronics systems, was featured at a com-memoration ceremony.
Since its introduction in the early 1990s, theXC4000 family has quickly grown to become theworld’s most successful FPGA product line. The addi-tion of XC4000E devices (and now the XC4000EXversions) to the product family have acceleratedXC4000 unit shipments since mid-1994, when thefamily reached the million-unit milestone.
“As medical technology continues to advance at aphenomenal rate, the success of Acuson more andmore depends on our ability to design and deliver thebest products possible in the shortest amount of time,”stated Robert Gallagher, Acuson president. “TheXC4000 has greatly contributed to our technologicalvision and has helped us provide cost-effective solu-tions for the needs of our dynamic marketplace. Weare delighted to share in the XC4000’s success.” ◆
Please contact your local Xilinx sales representative for furthertechnical information, price and availability information, or requestsfor samples of these new ISP CPLD products. ◆
Four new XC9500 ISP (In-SystemProgrammable) CPLD devices are now involume production. The XC9536, XC9572,XC95108 and XC95216 CPLDs are readyfor designers looking for the best, most-flexible ISP solution. These 36-, 72-, 108-and 216-macrocell devices, respectively,feature fast, guaranteed performance, theindustry’s best pin-locking architecture, atrue JTAG-compliant interface, and ad-vanced flash memory technology with upto 10,000 program/erase cycles. Theresulting benefits include reduced overallcosts, faster time-to-market and the flex-ibility needed to make design changesanytime during the product life cycle.
Feature XC9536 XC9572 XC95108 XC95216
Macrocells 36 72 108 216Usable Gates 800 1600 2400 4800tPD
(ns) 5/7.5/10/15 7.5/10/15 7.5/10/15 10/15/20Registers 36 72 108 216Pin-locking ✓ ✓ ✓ ✓JTAG (1149.1) ✓ ✓ ✓ ✓Max. User I/Os 34 72 108 166
Packages PC44/VQ44PC84 PC84
PQ100/TQ100 PQ100/TQ100PQ160 PQ160
HQ208
THE XC4000 SERIES OF FPGAS:
XC4000EX Family Enters ProductionThe world’s most popular FPGA series just got bigger! Xilinxbegan shipments of production-qualifed XC4036EX devices inNovember. The XC4036EX offers 36,000 maximum logic gates anda typical gate range (logic and memory) of 22,000 to 65,000 gates.Planned devices in the XC4000EX family will range from 28,000 to128,000 logic gates.
The XC4000EX FPGAs contain all the advanced features of thepopular XC4000 and XC4000E architectures. However, severalsignificant enhancements to the architecture address the routing,clock distribution, and I/O needs of higher density devices (SeeXCell #20, page 21).
Development system software for the XC4000EX family willstart shipping in late December. The initial software offering willsupport Synopsys, Mentor Graphics and Viewlogic EDA environ-ments, as well as workstations from Sun (both SunOS and Solaris)and HP. Please contact your local Xilinx sales representative forthe latest availability status. ◆
this self-extracting file in a temporarydirectory and run it in DOS. It will expandlots of files into this directory. Then,within Windows NT 3.51, choose File ➡Run Update.exe from within this tempo-rary directory and the update installprogram will run.
Windows NT 4.0: You will need todownload two items from the RainbowTechnologies Web site. (Rainbow Tech-nologies is the manufacturer of the hard-ware key.) At their site, www.rnbo.com/tech/drivers/drivers.htm, download“Patch for Windows NT 4.0” and “RainportDriver for Windows NT”. The formeris a single executable, NTVDM.EXE.Replace the existing version in yourC:\WINNT\SYSTEM32 directory andreboot. This file will be included inWindows NT 4.0 Service Pack 1 whenit is built. The latter is the Rainport driverthat is explained in the Drivers section.
InstallationThe first thing that must be done is the
Xilinx install; simply perform a Windowsinstall. Assuming that D:\ is your CDdrive, just select File ➡ Run (or Start ➡Run) and type D:\Wn1\Install\Winstall.exeat the prompt. If you are using Viewlogictools that support Windows NT,(Workview Office, NOT PROseries),choose the DS-VL-STD-PC1 product (notthe Stand-alone) from a Custom install.Select the products you would like toinstall, but keep in mind that you will beusing the DOS tools, so programs like theFloorplanner should be de-selected.Change the target path so the interfacetools are copied to C:\WVOFFICE insteadof C:\PROSER.
Next, copy the kernel32.dll file fromD:\PROSER to both C:\XACT andC:\WVOFFICE.
Then, install the patched version ofXNFPREP. This file is located on our FTP
XACTstep™ version 6.0.x (theWindows tools) was compiled and testedfor Windows 3.x. It was not compiled forWindows NT. Unlike Windows 95, there
is no work-aroundto enable theWindows tools towork. This releasedoes NOT supportWindows NT.
However, wehave had somesuccess usingXACTstep v5.2.1 (theDOS tools) within aDOS session underWindows NT. Thereare a few things thatmust be done to set
up the environment, as described below.Please note that the next full release of
Xilinx software will support Windows NT4.0. The solution described here should beconsidered a tactical work-around forWindows NT 3.51 and a temporary work-around for Windows NT 4.0.
All of the instructions apply to bothWindows NT versions 3.51 and 4.0, unlessotherwise noted.
Windows SetupWindows NT 3.51: Make sure that
your Windows NT 3.51 is up-to-date withthe latest set of patches and bug fixes,known as Service Pack 4. To check thestatus of your system, open the Adminis-trative Tools program group and double-click on the Windows NT Diagnosticsicon. Select the OS Version button andcheck the number next to Service Pack. Ifit is less than 4, you will need to upgrade.This free upgrade can be found atMicrosoft’s Web site: www.microsoft.com/kb/softlib/winnt.htm. Select “ServicePacks” then “Windows NT 3.51 ServicePack 4 for Intel (x86)” to download. Place
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site at ftp://ftp.xilinx.com/pub/swhelp/xact-pc and on our BBS (408-559-9327) inthe Software Help ➡ XACT-PC area. Thename of the file is PREP_NT.ZIP. Afterunzipping this file, place the XNFPREP.EXEfile in C:\XACT, overwriting the existingXNFPREP.EXE. This new version, 5.2.1c,fixes a bug where the .PRP file would notbe written.
Setting the EnvironmentNext, you must modify the environment
variables. Keep in mind that you must haveadministrator privileges to modify existingsystem environment variables and to adddrivers.
In the Main program group, double-click on Control Panel and then System(NT 3.51) or right click on My Computer(NT 4.0). In the System Environment Vari-ables area, select Path. In the Value field atthe bottom of the screen, add
C:\XACT;C:\WVOFFICE;
before the existing path, so it looks likeC:\XACT;C:\WVOFFICE;<rest_of_path>.
Hit the Set button, then create a new vari-able; the Variable is XACT and the Value is
C:\XACT;C:\WVOFFICE
Then bring C:\WINNT\SYSTEM32\AUTOEXEC.NT into a text editor. Add thisline at the end:
SET XACT=C:\XACT;C:\WVOFFICE
You can verify that these settings havebeen applied (after rebooting Windows NT)by typing SET in the DOS window. Leave allthe C:\WVOFFICE statements out if you arenot using the Workview Office tools.
DriversNext, you must install the Rainport
driver, which is also located on our FTPsite at ftp://ftp.xilinx.com/pub/swhelp/xact-pc and on our BBS in the SoftwareHelp ➡ XACT-PC area. The file is calledRAINPORT.EXE. This driver is required toenable Windows NT to recognize the
hardware key. The RAINPORT.EXEcontains a readme about how toinstall the driver. This driver can alsobe found in the SENTINEL directory onthe Workview Office 7.2 CD. ChooseControl Panels ➡ Drivers ➡ Add toinstall this. This version is only for usewith Windows NT 3.51.
Windows NT 4.0 users will install thenewer version of Rainport mentioned inthe Windows Setup section. A readmewithin the ZIP file explains how to installthis driver.
Running the toolsYou will be running the tools in an
MS-DOS session. Take a look at theReference Guide Volumes 1, 2 and 3 forspecific information about using thesetools in a DOS environment.
You will see that some of the Windowstools will work. Besides the SimulationUtility and the Memory Generator, youcan create a new icon for the TimingAnalyzer. The Command Line for this toolis c:\xact\timingan.exe and the WorkingDirectory is c:\xact. There have beencases where these Windows tools havehad problems, and the workaround is touse the DOS equivalent. Tools that willnot work are the Design Manager, FlowEngine, and Floorplanner.
If you have any problems using theAdobe Acrobat reader, you can downloada copy of Acrobat 2.1 for Windows 95/NTfrom their Web site, www.adobe.com/acrobat/windows.html.
Hopefully, these hints will get you upand running within your Windows NTenvironment. There are some differenceswith different installations of WindowsNT, so results may certainly vary. Pleasekeep in mind that these tools were neverintended to run in Windows NT, but ifyou do run into problems, please contactXilinx Technical Support for assistance. ◆
One-Day VHDL Seminar Now Available
TECHNICAL TRAINING UPDATE
seminars have been added to the scheduleto meet demand.
Each attendee receives an evaluation kitof the Xilinx software. This provides ampleopportunity to practice the skills and know-ledge obtained at the seminar. The kitincludes the Foundation Series software, anintegrated tool set of schematic entry, VHDLsynthesis, functional and timing simulationand design implementation tools – every-thing needed to create an entire design.
Xilinx, its distributors and representa-tives, together with Esperan, are sponsor-ing these seminars. Contact your localXilinx representative to inquire aboutVHDL training seminars in your area.
In related news, electronics distributorsHamilton Hallmark, Marshall and Insightare in the process of creating VHDL work-shops as well. In each case, Xilinx FPGAdevices and the Foundation Series toolshave been selected for use in the labexercises. ◆
Updated TrainingCourses Available
The basic Xilinx technical trainingcourses have been updated to reflect allthe features of the latest developmentsoftware. XACTstep™ version 6.0.1 softwareis fully incorporated into the schematic-based design course. The course examinesa complete design scenario for the Foun-dation Series software user. The updatedsynthesis-based design course providesVHDL/Verilog designers with an intimateworking knowledge of the XACTstepv5.2.1/6.0.1 synthesis software. Both ofthese courses are available worldwide.
The current schedule of schematic-and synthesis-based courses, as well ascourse registration information, can befound at the WebLINX web site(www.xilinx.com). ◆
Xilinx is sponsoring a series of one-day introductory VHDL seminars conducted
by qualified instructors fromEsperan Inc. Esperan specializesin technical training and haseducated thousands of VHDLusers since 1992. This one-daycourse, a must for new users,emphasizes the basics of theVHDL language.
A full day of lecture andhands-on labs, the seminaruses the VHDL tool of-fered by Xilinx in theFoundation Series™. The
tuition fee is $99. Feedback from partici-pants has been extremely positive; extra
First Hands-On Workshop onReconfigurable ComputingThe Xilinx University Program (XUP) has had an active training
schedule with nine recent workshops in four countries. XUP workshopsare designed to train university instructors on the basics of usingprogrammable logic for undergraduate courses, graduate courses andresearch.
In addition to the standard workshops, and in response to a grow-ing interest in dynamically-reconfigurable logic, a unique, leading-edgeworkshop was held at Cornell University (Ithaca, NY).
The Cornell workshop was the first to examine both the hardwareand software issues associated with dynamically-reconfigurable com-puting, including hands-on laboratory exercises. Participating lecturersincluded representatives from Xilinx, the Virginia Institute of Technol-ogy, ETZ Zurich, Cornell University, and Imperial College (UK). Mr.Nick Treddinick, an IEEE fellow, presented the keynote address.
Xilinx is committed to addressing the needs of the reconfigurablelogic market, and the Xilinx University Program is committed to furtheracademic support of this exciting area of study. Proceedings from theworkshop are available to XUP participants, and further informationabout this workshop and future XUP workshops can be obtained on theweb at www.xilinx.com/programs/univ.htm. ◆
Windows NT Environment
VHDL SEMINAR ATTENDEES LEARN:
• The benefits of using VHDL design
to reduce time-to-market
• VHDL’s general structure and syntax
• How to write good VHDL code that
will synthesize efficiently
• How to effectively target CPLD and
FPGA architectures
• How to implement state machines,
combinatorial logic and arithmetic
functions in VHDL
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That’s it! This will create an agent thatwill notify you whenever Xilinx posts anew application note to the site. Remem-ber that you can create an agent for any-thing you can search for, and they are notlimited to the Xilinx site. ◆
WebLINX (www.xilinx.com) hasbecome a popular stopping place on theinformation superhighway. Based on recenttraffic reports, more than 5,000 people visitthe Xilinx World Wide Web site eachweek. Some of the most popular areas ofour web include SmartSearch, ProductInformation pages, Application Notes andthe Data Book page.
We’re constantly adding new informa-tion to WebLINX. In fact, over the last fewmonths we have added many new applica-tion notes and application briefs to the site,as listed here.
If you are interested in keeping up-to-date with new technical information beingposted to WebLINX, then SmartSearchAgents are for you. A SmartSearch Agentwill automatically notify you via e-mailwhen a document of interest to you isposted to any of the 50 or so sites that weindex. For example, you can create aSmartSearch Agent that will alert you re-garding any new application notes postedto the Xilinx site by following these steps:
WebLINX and SmartSearchAgents Keep You Up-to-Date
1. Using your browser, go towww.xilinx.com
2. Click on the “Register Now for Agents!”hyperlink near the bottom of the page.
3. Click on the “register” hyperlink4. Fill out the registration questionnaire.5. After you have successfully registered
for Agents, go to SmartSearch byclicking on the SmartSearch logo ortext at the bottom of the page.
6. Click on the “Xilinx Only” link.7. Leave the text box blank but select the
“application notes” check box.8. Click on the Start Search button. On the
results page, in the upper right corneris a text box with the label “AgentName:”
9. Type “Xilinx Application Notes” into theagent name box and click on the CreateAgent button.
The following XAPP application notes and XBRF application
briefs have recently been added to WebLINX. You can find
these by first going to the application notes page and
selecting XAPP application notes or application briefs.
• XAPP051 Synchronous/Asynchronous FIFOs
• XAPP052 Efficient Shift Registers, LFSR Counters, etc.
• XAPP053 Implementing FIFOs in XC4000 Series RAM
• XAPP054 Constant Coefficient Multipliers for the XC4000E
• XAPP055 Block Adaptive Filter
• XAPP056 System Design with New XC4000EX I/O Features
• XAPP057 Using Select-RAM Memory in XC4000 Series FPGAs
• XAPP058 XC9500 In-System Programming Using an 8051 Microcontroller
• XAPP059 Gate Count Capacity Metrics for FPGAs
• XAPP060 Design Migration from XC4000 to XC5200
• XAPP062 Design Migration from XC4000 to XC4000E
• XAPP063 Interfacing XC6200 to Microprocessors (MC68020 Example)
• XAPP064 Interfacing XC6200 to Microprocessors (TMS320C50 Example)
• XAPP065 XC4000 Series Edge-Triggered and Dual-Port RAM Capability
In addition, the following application notes have been updated:
• XAPP013 Using the Dedicated Carry Logic in XC4000E
• XAPP018 Estimating the Performance of XC4000E Adders and Counters
Xilinx Application Briefs are technical papers describing
the advantages of Xilinx products, especially versus
alternative solutions:
• XBRF001 XC4000E Select-RAM: Flexibility with Speed
• XBRF002 XC4000E Low Power Consumption: At High Speed
• XBRF003 XC4000E Select-RAM: Maximum Configurability
• XBRF005 XC4000EX Routing: A Comparison with XC4000E and ORCA
• XBRF006 PLL Design Techniques and Usage in FPGA Design
• XBRF007 XC4000-Series FPGAs: The Best Choice for Delivering Logic Cores
• XBRF009 XC9500 Pin Locking Capability and Benchmarks
TECHNICAL QUESTIONS & ANSWERS
QBesides the CD-ROM supplied withthe product, are there any sources
of additional information about usingthe Xilinx Foundation Series software?
The Foundation Documentation UpdatePack contains application notes about the
Foundation Logic Simulator, FoundationXVHDL compiler, and a new simulationtutorial. Get FND_DOC1.EXE (self-extract-ing ZIP file) from the Xilinx FTP site(ftp.xilinx.com/pub/swhelp/foundation) orthe Xilinx BBS (Software Help ➡ Aldec).
Foundation
ENWrite (Mentor’s EDIF netlister) looksat the XC4000 version of OFD in the sche-matic. This component has attached to it aCOMP=OFD property, indicating that thiscomponent is a primitive and should bewritten as such in the EDIF file. EDIF2XNFthen takes this primitive description andlooks for the corresponding ofd.eds file inthe $LCA/data/unified/edif4000e directory,that contains EDIF descriptions forXC4000E primitives. Since OFD is not aprimitive in the XC4000E family, theofd.eds file does not exist in the directory,resulting in the error.
The correct OFD from the XC4000Elibrary has no COMP=OFD property at-tached to it, since the COMP property isreserved for primitives. Therefore, if thecorrect XC4000E component had beenused, ENWrite would have written out thehierarchy below OFD. Then, EDIF2XNFwould have never seen the OFD “primi-tive” and would have never tried to lookfor a non-existent ofd.eds file in theXC4000E data directory.
The proper way to retarget the designto a new device family is to use the Con-vert Design utility in PLD_DA before run-ning the implementation flow. ConvertDesign replaces the library components ina schematic or set of schematics so thatthey come from the proper library. Forinstructions on how to use Convert Design,see Solution 798, “Retargeting a design inMentor Design Architect (Convert Design),”from the Xilinx Solutions Database:
http://www.xilinx.com/techdocs/798.htm
MentorGraphics QCan XACTstep 5.2.1 be used with
Mentor Graphics’ B.x release?
A: Under Mentor B.x, Gen_sch8 andXBLXGS may fail with either “call to un-defined procedure” (SunOS) or “unresolvedpropagate symbol” (HP-UX) error messagesdue to problems with dynamically linkingto Mentor’s Design Data Port (DDP). Apatch is available to fix these problems andmake XACTstep 5.2.1 interface smoothlywith Mentor B.x. The patch may be down-loaded from the Xilinx FTP site at:
ftp://ftp.xilinx.com/pub/swhelp/mentor/b1_521s.tar.Z(SunOS)
ftp://ftp.xilinx.com/pub/swhelp/mentor/b1_521h.tar.Z(HP-UX)
QA schematic originally targetedfor the XC4000 family is now
targeting an XC4000E device. DuringMen2XNF8, the following erroroccurs when running EDIF2XNF:
Error: 6 EDIF data “ofd.eds”not found in directory“/usr/xact/data/unified/edif4000e”
In this case, the schematic was createdusing the XC4000 library, but the design isnow targeted to an XC4000E device. (Otherfamily combinations may also cause thiserror.) Certain symbols are primitives in theschematic library with which the design wasbuilt (XC4000), but are macros in the libraryassociated with the device being targeted(XC4000E). In this example, OFD is a primi-tive in the XC4000 library but is a macro inthe XC4000E library (since it has, under-neath it, the clock-enabled OFDX symbol).
10
23
Learn about the newest Xilinx products and services through our extensive library ofproduct literature. The most recent pieces are listed below. To order or to obtain a com-plete list of all available literature, please contact your local Xilinx sales representative. ◆
New ProductLiterature
Corporate
Product Overview Brochure Features & Benefits 0010130-05Software Solutions Brochure Features & Benefits 0010304
TITLE DESCRIPTION NUMBER
Design SuperConJan. 21–23Santa Clara, California
ACM/SIGDA 5th InternationalSymposium on FPGAsFeb. 9–11Monterey, California
International IntegratedCircuits ConferenceMarch 13–14Beijing, China
Look for Xilinx technical papers and/or product exhibits at these upcoming industryforums. For further information about any of these conferences, please contact KathleenPizzo (Tel: 408-879-5377 FAX: 408-879-4676). ◆
UPCOMING EVENTS
Intellectual Propertyin ElectronicsSeminarMarch 17–18Santa Clara, California
SemiconductorSolutionsMarch 18–20Birmingham,United Kingdom
InternationalIntegrated CircuitsConferenceMarch 17–18Shanghai, China
European Designand Test ConferenceMarch 17–20Paris, France
FINANCIAL RESULTS
QWhat is happening whenQuicksim issues this warning
on every primitive in a design:// Warning: Instance
’/GIVE_ME_AN_E’// Could not find a
registered simulation modelwith label: ’xc4000’
// NULL model will beinserted. (from: Analysis/Digital/SimulationUtilities/Dsim 85)
This is caused by an incorrectly-writtensimulation viewpoint for the design, whichcan result when a design is retargeted to anew device family. The solution is to delete
that default viewpoint, then runPLD_DVE_SIM on the design, specifyingthe correct part family. If done from thecommand line, an XC4000 design, forexample, might use:
delete_objectblanking_design/default
pld_dve_sim blanking_designxc4000
Note: If Timsim8 -o was used to createthe simulation model, be sure to runTimsim8 instead of PLD_DVE_SIM.Timsim8 -o runs PLD_DVE_SIM, then addslinks to timing information into the view-point afterwards.
Runscript for compiling the XC4000/XC4000EBSCAN Verilog Example:
PART = 4025ehq240-3TOP = example
read -format verilog “bscan4k.v”
set_port_is_pad “*”insert_pads
set_dont_touch u1set_dont_touch u2set_dont_touch u3set_dont_touch u4set_dont_touch u5
compile
replace_fpga
set_attribute TOP “part” -type stringPART
write -f xnf -h -o “bscan4k.sxnf”
For the first time, Xilinx Inc. quarterlysales revenues declined from both theprior quarter and the year ago period.Revenues for the September-ending quar-ter were $130.6 million, a decrease of13.1% from the immediately precedingquarter and 7.5% from the same quarterone year ago.
“The September quarter was a difficultquarter for the overall programmable logicindustry and Xilinx in particular,” statedCEO Wim Roelandts. “We believe thisrevenue shortfall can be attributed toseveral factors, including increased pres-sure from selected customers to reduce
their own inventory, a seasonably weakersummer quarter in Europe, and new cus-tomer programs that have not ramped upas quickly as initially forecasted.”
Roelandts continued, “However, we areencouraged by the nearly 1,400 new soft-ware seats that we sold this quarter, 70%of which are versions of our new, shrink-wrapped, low-cost Foundation™ software,”Roelandts added. “We are also optimisticthat our new XC9500 and XC4000EX fami-lies will provide meaningful contributionsto revenues before our fiscal year end.”
Xilinx Inc. stock is traded on NASDAQunder the symbol XLNX. ◆
ADifficultQuarter
MentorGraphics(continued)
SynopsysQHow are Boundary Scan com-ponents for the XC4000 family
instantiated in Verilog-based designs?
To use Boundary Scan components inXC4000 Series devices, instantiate theboundary scan symbol (BSCAN) and theassociated dedicated I/O. Use the“dont_touch” attribute; otherwise, BSCAN
may be deleted by the Synopsys compiler.The Verilog code for instantiating
BSCAN in the XC4000 is shown below.VHDL and Verilog examples for both theXC4000 and XC5000 can be found on theXilinx Web site (www.xilinx.com), or canbe emailed to users via the Xdocs mailserver (email [email protected]).
XC4000/XC4000E example ofinstantiating the BSCAN symbol:
module example (a,b,c);
input a, b;output c;reg c;
wire tck_net;wire tdi_net;wire tms_net;wire tdo_net;
BSCAN u1 (.TDI(tdi_net), .TMS(tms_net),.TCK(tck_net), .TDO(tdo_net));
TDI u2 (.I(tdi_net));TMS u3 (.I(tms_net));TCK u4 (.I(tck_net));
TDO u5 (.O(tdo_net));
always@(posedge b)c<=a;
endmodule
24
9
Xilinx LogiCore Alliance), and reusablemodules from his/her previous designs.
SLMs from all sources will be designedto common standards, much like physicalcomponents that are mixed-and-matchedtoday on a printed circuit board. TheseVSI-compliant SLMs can be viewed as“virtual components” that, throughcommon interface standards, fit quicklyinto “virtual sockets.” In order to rapidlyprovide a solution, the design data stan-dards will be based on open formatscommonly supported by all EDA vendors.
High-quality SLMs are a key componentfor high-performance and high-density pro-grammable logic design. The use of pre-defined and pre-verified SLMs can dramati-cally reduce system development cost andtime, resulting in faster time-to-market and agreater competitive advantage.
For further information about the VSIAlliance, see their web site at www.ip-net.org. For additional information about theLogiCore products and LogiCore AllianceProgram, see the WebLINX web site atwww.xilinx.com/products/logicore/logicore.htm. ◆
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PLASTIC LCC PC44
PLASTIC QFP PQ44
PLASTIC VQFP VQ44
CERAMIC LCC WC44
PLASTIC DIP PD48
PLASTIC VQFP VQ64
PLASTIC LCC PC68
CERAMIC LCC WC68
CERAMIC PGA PG68
PLASTIC LCC PC84
CERAMIC LCC WC84
CERAMIC PGA PG84
CERAMIC QFP CQ100
PLASTIC PQFP PQ100
PLASTIC TQFP TQ100
PLASTIC VQFP VQ100
TOP BRZ. CQFP CB100
CERAMIC PGA PG120
PLASTIC PGA PP132
CERAMIC PGA PG132
PLASTIC TQFP TQ144
CERAMIC PGA PG144
CERAMIC PGA PG156
PLASTIC PQFP PQ160
CERAMIC QFP CQ164
TOP BRZ. CQFP CB164
PLASTIC PGA PP175
CERAMIC PGA PG175
PLASTIC TQFP TQ176
CERAMIC PGA PG184
CERAMIC PGA PG191
TOP BRZ. CQFP CB196
PLASTIC PQFP PQ208
METAL MQFP MQ208
HI-PERF QFP HQ208
CERAMIC PGA PG223
PLASTIC BGA BG225
WINDOWED BGA WB225
TOP BRZ. CQFP CB228
PLASTIC PQFP PQ240
METAL MQFP MQ240
HI-PERF QFP HQ240
CERAMIC PGA PG299
HI-PERF. QFP HQ304
PLASTIC BGA BG352
CERAMIC PGA PG411
PLASTIC BGA BG432
CERAMIC PGA PG475
PLASTIC BGA BG560
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Xilinx Joins Virtual Socket Interface AllianceLast September, a group of more than
35 leading electronics firms announced theformation of the Virtual Socket Interface(VSI) alliance. This open alliance is dedi-cated to promoting the growth of the sys-tem level integration (SLI) chip industry bydeveloping the technical standards requiredto enable the “mix and match” of systemlevel modules (SLMs). Xilinx has enteredthe VSI alliance, and is actively participat-ing in standardization efforts affecting pro-grammable logic technologies. Our partici-pation augments our current programs forthe development of a diverse set of high-quality SLMs, called LogiCore™ modules, forthe various Xilinx FPGA and CPLD families.
The goal is to establish a set of openSLM design interface and productizationstandards. Through use of the developedstandards, design engineers will be able touse SLMs from several sources in the de-sign of highly-integrated programmablelogic devices. For example, a designercould construct a system combining SLMssupplied by Xilinx (such as the LogiCorePCI master/slave), SLMs from third-partyproviders (such as the members of the
New AppLINX CD-ROM ShippedAn updated AppLINX CD-ROM has
been shipped to all registered Xilinx users.The CD contains a complete collection ofXilinx applications and product informa-tion. Access to the AppLINX CD is anotherbenefit of maintenance support for theXilinx development system.
The AppLINX CD-ROM includes:• Updated September 1996 data book• All Xilinx application notes and their
corresponding design files• Development system documentation• The last six issues of the XCell journal• Adobe Acrobat® Reader™ with full
content-searching capabilities
• Presentation notes for the Xilinx 1996Fall Seminar
The AppLINX CD merges the best aspectsof the Xilinx WebLINX web site and the XilinxFTP site. Users with access to an HTMLbrowser can navigate the files quickly andeasily off-line, while links are available tofind the latest information on-line.
The AppLINX CD will be updated on aregular basis. Make sure you visit the XilinxWebLINX web site at www.xilinx.com forthe latest information.
Regarding the fall seminar, contact yourlocal Xilinx sales office to inquire about apresentation to your company. ◆
25
8ability, and hardware-implemented parallelprocessing. It’s a sophisticated, highlyportable architecture based on Xilinxreconfigurable FPGAs and banks of high-speed RAM.
As the tendency towards more complexDSP systems continues to grow, designersare constantly seeking new ways to reachhigher performance and to unravel bottle-necks while reducing development costs.“What is unique with our X-CIM is itsimplementation in an IEEE standard andoff-the-shelf product packaging,” notedMiroTech President and CEO PierrePopovic. “The X-CIM module can deliveracceleration up to 100 times that of a gen-eral-purpose DSP processor for highlyrepetitive ‘inner loops’ within algorithms.”
The marriage of the X-CIM module withSpectrum’s products allows the design ofvery compute-intensive systems whilestaying within Spectrum’s C40 environmentand DSP development tools. X-CIM mod-ules are supported by a comprehensivesuite of software tools referred to asCOREKIT. With these tools, developerscan transparently accelerate a wide rangeof DSP functions in applications such asradar, sonar, voice and image processing.
For more information on the X-CIMproduct line, contact MiroTechMicrosystems Inc. at 514-956-0060 orat [email protected]. ◆
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NOVEMBER 1996
PLASTIC LCC PC44
PLASTIC QFP PQ44
PLASTIC VQFP VQ44
CERAMIC LCC WC44
PLASTIC DIP PD48
PLASTIC VQFP VQ64
PLASTIC LCC PC68
CERAMIC LCC WC68
CERAMIC PGA PG68
PLASTIC LCC PC84
CERAMIC LCC WC84
CERAMIC PGA PG84
CERAMIC QFP CQ100
PLASTIC PQFP PQ100
PLASTIC TQFP TQ100
PLASTIC VQFP VQ100
TOP BRZ. CQFP CB100
CERAMIC PGA PG120
PLASTIC PGA PP132
CERAMIC PGA PG132
PLASTIC TQFP TQ144
CERAMIC PGA PG144
CERAMIC PGA PG156
PLASTIC PQFP PQ160
CERAMIC QFP CQ164
TOP BRZ. CQFP CB164
PLASTIC PGA PP175
CERAMIC PGA PG175
PLASTIC TQFP TQ176
CERAMIC PGA PG184
CERAMIC PGA PG191
TOP BRZ. CQFP CB196
PLASTIC PQFP PQ208
METAL MQFP MQ208
HI-PERF QFP HQ208
CERAMIC PGA PG223
PLASTIC BGA BG225
WINDOWED BGA WB225
TOP BRZ. CQFP CB228
PLASTIC PQFP PQ240
METAL MQFP MQ240
HI-PERF QFP HQ240
CERAMIC PGA PG299
HI-PERF. QFP HQ304
PLASTIC BGA BG352
CERAMIC PGA PG411
PLASTIC BGA BG432
CERAMIC PGA PG499
PLASTIC BGA BG596
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◆ = Product currently shippingor planned
❖ = New since last issue of XCell
RC COMPANY OF THE QUARTER
Our congratulations to the develop-ment team at MiroTech Microsystems Inc.(Montreal, Canada). MiroTech Micro-systems has released a commercial prod-uct that uses reconfigurable computing toadvance the state-of-the-art for DSP accel-
eration. At the most recentICSPAT/DSP World Exposition inBoston, MiroTech Microsystemsannounced an exclusive NorthAmerican agreement withSpectrum Signal ProcessingInc. to distributeMiroTech’s FPGA-basedDSP acceleration mod-ule. MiroTech’s X-CIMmodule complementsSpectrum’s exten-sive PCI, VXI andVME C4x-basedDSP productline. Togetherthese prod-ucts provide
substantial acceleration forselected compute-intensive, high-perfor-mance applications.
X-CIM is an FPGA-based reconfigurablecomputer in a TIM form factor that isfully-compliant with Texas Instruments’TMS320C40 DSP processor. The modulefeatures 80 Mbytes/s communication portbandwidth, 30 ms on-the-fly reconfigur-
MiroTech Microsystems:Real-Time Reconfigurability for DSP Acceleration
The Xilinx Reconfigurable Computing Developer’s Program is promot-
ing the commercial use of FPGAs in reconfigurable computing applica-
tions. These systems add significant value by dynamically changing
FPGA designs, in real-time, while the system is operating. Applications
that can exploit the benefits of the RC concept include graphics and
image processing, audio processing, and data communications.
For more information on the XilinxDeveloper’s Program and our recon-figurable computing efforts, please seeour web site at www.xilinx.com, or callJohn Watson at 408-879-6584.
26
7
PROGRAMMER SUPPORT FOR XILINX XC7200/XC7300 CPLDS — NOVEMBER 1996MANUFACTURER MODEL 7236A 7272A 7318 7336 7336Q 7354 7372 73108 73144
ADVANTECH PC-UPROGLABTOOL-48 V1.31A V1.31A V1.31A V1.31A V1.31A V1.31A V1.31A V1.31A
ADVIN SYSTEMS PILOT-U40 10.84B 10.84B 10.84B 10.84B 10.84BPILOT-U84 10.84B 10.84B 10.84B 10.84B 10.84B 10.84B 10.84B 10.84B 10.84B
B&C MICROSYSTEMS, INC. Proteus 1Q97 1Q97 1Q97 1Q97 1Q97 1Q97 1Q97 1Q97 1Q97
BP MICROSYSTEMS BP-1200 V3.15 V3.15 V3.15 V3.18 V3.15 V3.15 V3.15 V3.15BP-2100 V3.15 V3.15 V3.15 V3.18 V3.15 V3.15 V3.15 V3.15
DATAMAN DATAMAN-48 V1.30 V1.30 V1.30 V1.30 V1.30 V1.30 V1.30 V1.30
DATA I/O 2900 BBS BBS BBS BBS3900/AutoSite BBS BBS BBS BBS BBS BBS BBSUniSite BBS BBS BBS BBS BBS BBS BBS
DEUS EX MACHINA ENGINEERING XPGM V1.40 V1.40 V1.40 V1.40 V1.40 V1.40 V1.40 V1.40 V1.50
ELECTRONIC ENGINEERING TOOLS ALLMAX/ALLMAX+ V2.4U V2.4U V2.4U V2.4U V2.4U V2.4U V2.4U V2.4UMEGAMAX V1.1E V1.1E V1.1E V1.1E V1.1E V1.1E V1.1E V1.1E
ELAN 6000 APS DISQUALIFIED
HI-LO SYSTEMS RESEARCH All-03A V3.09 V3.09 V3.09 V3.09 V3.09 V3.09 V3.09 V3.09All-07 V3.09 V3.09 V3.09 V3.09 V3.09 V3.09 V3.09 V3.09
ICE TECHNOLOGY LTD Micromaster 1000/E V1.1 V1.1 V1.1 V1.1 V1.1 V1.1 V3.1 V1.1 V1.1Speedmaster 1000/E V1.1 V1.1 V1.1 V1.1 V1.1 V1.1 V3.1 V1.1 V1.1Micromaster LV V1.1 V1.1 V1.1 V1.1 V1.1 V1.1 V3.1 V1.1 V1.1Speedmaster LV V1.1 V1.1 V1.1 V1.1 V1.1 V1.1 V3.1 V1.1 V1.1
LEAP ELECTRONIC CO., LTD. LEAPER-10 V3.2 V3.2 V3.2 V3.2 V3.2 V3.2 V3.2 V3.2 V3.2LP U4 V2.1 V2.1 V2.1 V2.1 V2.1 V2.1 V2.1 V2.1 V2.1
LOGICAL DEVICES ALLPRO-88 DISQUALIFIEDALLPRO-88XR DISQUALIFIEDALLPRO-96 6.4.26 6.4.26 6.4.26 6.4.26 6.4.26 6.4.26 6.4.26 6.4.26Chipmaster 2000 V2.4U V2.4U V2.4U V2.4U V2.4U V2.4U V2.4U V2.4UChipmaster 6000 V1.31A V1.31A V1.31A V1.31A V1.31A V1.31A V1.31A V1.31AXPRO-1 DISQUALIFIED
MICROPROSS ROM9000
MQP ELECTRONICS SYSTEM 2000 Nov-96 Nov-96 Nov-96 Nov-96 Nov-96 Nov-96 Nov-96 Nov-96 Nov-96PIN-MASTER 48 Nov-96 Nov-96 Nov-96 Nov-96 Nov-96 Nov-96 Nov-96 Nov-96 Nov-96
NEEDHAM’S ELECTRONICS EMP20 V3.10 V3.10 V3.10 V3.10 V3.10 V3.10 V3.10 V3.10
SMS EXPERTOPTIMA
STAG ECLIPSE 6.4.26 6.4.26 6.4.26 6.4.26 6.4.26 6.4.26 6.4.26 6.4.26 6.8.9
SUNRISE T-10 UDPT-10 ULC
SUNSHINE POWER-100 V8.40 V8.40 V8.40 V8.40 V8.40 V8.40 V8.40EXPRO-60/80 V8.40 V8.40 V8.40 V8.40 V8.40 V8.40 V8.40
SYSTEM GENERAL TURPRO-1/FX V2.30 V2.30 V2.30 V2.30 V2.30 V2.30 V2.30 V2.30 V2.30MULTI-APRO V3.02 V3.02 V3.02 V3.02 V3.02 V3.02 V3.02 V3.02 V3.02
TRIBAL MICROSYSTEMS Flex-700 V3.09 V3.09 V3.09 V3.09 V3.09 V3.09 V3.09 V3.09TUP-300 V3.09 V3.09 V3.09 V3.09 V3.09 V3.09 V3.09TUP-400 V3.09 V3.09 V3.09 V3.09 V3.09 V3.09 V3.09
XELTEK SUPERPROSUPERPRO II 2.4B 2.4B 2.4B 2.4B 2.4B 2.4B 2.4B 2.4B 2.4BSUPERPRO II/P 2.4B 2.4B 2.4B 2.4B 2.4B 2.4B 2.4B 2.4B 2.4B
XILINX HW-130 1.14 1.04 1.15 1.15 1.06 1.16 1.07 1.07 1.02
Changes since last issue are noted in color. Note: The XC7200 and XC7300 CPLD charts have been combined since the last issue.
PROGRAMMER SUPPORT FOR XC9500 — NOVEMBER 1996 — TOP THREE BY REGION
UNITED STATES EUROPE SOUTHEAST ASIA/JAPAN
MANUFACTURER DATE MANUFACTURER DATE MANUFACTURER DATE
BP MICROSYSTEMS 11/15/96 DATA I/O NOW DATA I/O NOW
DATA I/O NOW SMS 12/31/96 SYSTEM GENERAL 12/15/96
LOGICAL DEVICES 12/15/96 STAG 1/17/97 HI-LO 11/6/96
XILINX HW-130 V3.02 XILINX HW-130 V3.02 XILINX HW-130 V3.02
Supercomputing ProcessorsIn the GigaBooster system, the controllerwas redesigned into three XC4013 FPGAs toallow room for expansion. One FPGA holdsseveral small state machines, an abundanceof control registers, and other glue andinterface logic; this design uses about half ofthe available logic blocks, but all of the I/Opins. The other two FPGAs implement thelogic directly involved in the gathering andredistribution of data from the processingelements, including a 42-bit counter and alarge register/comparator file for each PE.The first of theseFPGAs is morethan 90% utilized,and connects tofive of the processing elements.
About 40% of the second FPGA containsthe identical logic for the remaining twoPEs. Additional logic is dedicated to moni-toring the communications behavior ofapplications running on the system, and theremainder of this FPGA can be used tosupport a module slot for an additionalprocessing element or an interface to anoptical high-speed network. The XC4000architecture’s built-in carry logic was criticalto attaining acceptable performance fromthe large counters and comparators in thisimplementation. The design runs at 20 MHz.
The FPGA designs were developedon a Sun workstation using Viewlogic’sPowerview tools and the XACT® develop-
ment system. This combination “forms avery comfortable development environ-ment,” according to Hansruedi VonderMüehll, the design engineer at the SwissFederal Institute of Technology who wasresponsible for the original design of thecommunications controller. Somefloorplanning was required, and both func-tional and timing simulation were used todebug and verify system operation.
The FPGA’s readback capability alsowas exploited during system debug, and isnow used to “dump” the state of the
communications controller in the event ofa communication failure. Using readback,the values of internal counters, registers,and state machines can be extractedand analyzed.
In summary, the use of reconfigurableXC4013 FPGAs was key to the imple-mentation of interprocessor communicationprotocols directly in hardware, as opposedto the more-traditional software approaches.The resulting high-performance communi-cations management allows the system totap the full processing power of each of itsAlpha processors, delivering 1.6 Gigaflopsof peak performance in an affordable andcompact system. ◆
❝The use of reconfigurable XC4013 FPGAs was
key to the implementation of interprocessor communication
protocols direclty in the hardware.❞
27
6
FP
GA
CU
STO
MER
SU
CC
ESS S
TO
RY
Designers at Supercom
puting Systems
AG (Zürich, Sw
itzerland) took a novelapproach in designing the G
igaBoosterparallel com
puter system —
combining
multiple processing elem
ents built fromstandard com
ponents with a fast, low
-latency com
munication
scheme im
plemented in
hardware. To im
plement
the critical comm
unica-tions control logic, theychose the w
orld’s leadingFPG
A family —
theXC4000 Series.
Based on the “alpha7,”a prototype system
de-signed at the electronics
laboratory of the ETH (the Sw
iss FederalInstitute of Technology), the G
igaBoosteris a parallel com
puter containing seven
individual processing elements (PEs) on a
single board. Each PE is constructed froma D
ECchip 21066 Alpha processor, oneM
byte of cache mem
ory, up to 128 Mbytes
of DRAM
mem
ory (256 Mbytes in the
“root” PE), a SCSI controller, and two
special registers that control clock, reset,interrupts and sim
ilar functions. Each PE isaccom
panied by two banks of FIFO
buff-ers dedicated to interprocessor com
muni-
cation and connected to a comm
on 72-bitbus. All the special registers and FIFObuffers are controlled by a central com
mu-
nications controller realized within three
XC4013 FPGAs. All the PEs run the D
igitalU
NIX operating system
, providing accessto over 3000 applications.
A new com
munications protocol called
Intelligent Comm
unication was developed to
provide fast comm
unications and comm
uni-cation control, enabling thesystem
to take full advantage ofthe processing pow
er in each PE.This protocol, im
plemented
directly in hardware using the
FPGAs, allow
s fast, low-latency
data exchange among the pro-
cessors, and a programm
ingm
odel with sim
ple and efficientcode. The in-system
program-
mable nature of the XC4013
FPGAs w
as key to the develop-m
ent of this protocol; duringdevelopm
ent, various ap-proaches w
ere tested and com-
pared simply by reconfiguring
the FPGA devices.
In the original alpha7 sys-tem
design, the comm
unica-tions controller w
as squeezedinto just tw
o XC4013 devices.
Changes since last issue printed in color; 1736A, 1765 and 17128 columns eliminated since last issue
PROGRAMMER SUPPORT FOR XILINX XC1700 SERIAL PROMS-NOVEMBER 1996XC1718DXC1736D XC1718L XC17128D XC17128L
MANUFACTURER MODEL XC1765D XC1765L XC17256D XC17256L
ADVANTECH PC-UPROGLABTOOL-48
ADVIN PILOT-U24 10.84B 10.84BPILOT-U28 10.84B 10.84BPILOT-U32 10.84B 10.84BPILOT-U40 10.84B 10.84BPILOT-U84 10.84B 10.84BPILOT-142 10.84B 10.84BPILOT-143 10.84B 10.84BPILOT-144 10.84B 10.84BPILOT-145 10.84B 10.84B
B&C MICROSYSTEMS INC. Proteus-UP40 3.7Q 3.7Q
BP MICROSYSTEMS CP-1128EP-1140BP-1200 V3.15 V3.15 V3.15BP-2100 V3.15 V3.15 V3.15
BYTEK 135H-FT/UMTK-1000MTK-2000MTK-4000
DATAMAN DATAMAN-48 V1.30 V1.30
DATA I/O UniSite BBS BBS BBS Oct-962900 BBS BBS BBS Oct-963900 BBS BBS BBS Oct-96AutoSite BBS BBS BBS Oct-96ChipLab BBS BBS BBS Oct-962700 BBS BBS BBS Oct-96
DEUS EX MACHINA XPGM V1.40 V1.40 V1.40 V1.40
E E TOOLS ALLMAX/ALLMAX+ V2.4U V2.4U V2.4UMEGAMAX V1.1E V1.1E V1.1E
ELAN DIGITAL SYSTEMS 3000-1455000-1456000 APS Disqualified
HI-LO SYSTEMS RESEARCH All-03A V3.19 V3.19 V3.19 V3.19All-07 V3.19 V3.19 V3.19 V3.19
ICE TECHNOLOGY LTD Micromaster 1000/E V3.17 V3.17 V3.17 V3.17Speedmaster 1000/E V3.17 V3.17 V3.17 V3.17Micromaster LV V3.17 V3.17 V3.17 V3.17LV40 Portable V3.17 V3.17 V3.17 V3.17Speedmaster LV V3.17 V3.17 V3.17 V3.17
LEAP ELECTRONICS LEAPER-10 V2.0 V2.0LP U4 V2.0 V2.0
XC1718DXC1736D XC1718L XC17128D XC17128L
MANUFACTURER MODEL XC1765D XC1765L XC17256D XC17256L
LINK COMPUTER GRAPHICS CLK-3100 V5.61 V5.61
LOGICAL DEVICES ALLPRO-40ALLPRO-88 V2.7 V2.7ALLPRO-88XR V2.7 V2.7ALLPRO-96 6.5.10 6.5.10 6.5.10 6.5.10CHIPMASTER 2000 V2.4U V2.4UCHIPMASTER 6000 V1.31A V1.31AXPRO-1 SPROM.310 SPROM.310
MICRO PROSS ROM 5000 BROM 3000 UROM9000
MQP ELECTRONICS MODEL 200 6.46 6.46 6.46SYSTEM 2000 2.25 2.25 2.25PIN-MASTER 48
NEEDHAM’S ELECTRONICS EMP20 V3.10 V3.10
RED SQUARE IQ-180 disqualifiedIQ-280 disqualifiedUniwriter 40 disqualifiedChipmaster 5000 disqualified
SMS ExpertOptimaMultisyteSprint Plus48
STAG Eclipse 6.5.10 6.5.10 6.5.10 6.5.10Quasar
SUNRISE T-10 UDPT-10 ULC
SUNSHINE POWER-100 V8.40 V8.40EXPRO-60/80 V8.40 V8.40
SYSTEM GENERAL TURPRO-1 V2.26H V2.26H V2.26HTURPRO-1 F/X V2.26H V2.26H V2.26HTURPRO-1 T/XAPRO V1.24MULTI-APRO V1.16 V1.16 V1.16 V1.16
TRIBAL MICROSYSTEMS TUP-300 V3.19 V3.19 V3.19 V3.19TUP-400 V3.19 V3.19 V3.19 V3.19FLEX-700 V3.19 V3.19 V3.19 V3.19
XELTEK SuperPROSuperPRO II 2.4B 2.4BSuperPRO II/P 2.4B 2.4B
XILINX HW-112 5.20 5.20HW-130 2.01 2.01 2.01 1.00
Swiss Engineers Use FPG
As to Link
❝To implem
entthe critical com
munications
control logic, they chose the
world’s leading FPG
A family
— the XC4000 Series. ❞
28
5
Continued from page 2
can account for anywhere from
one tonine “gates” w
hen used to implem
ent alogic function, depending on the type offunction that is im
plemented. H
owever,
when that sam
e look-up table is used as16 bits of RO
M or RAM
mem
ory, it now is
implem
enting 16 x 4 = 64 “equivalentgates.” Thus, FPG
A gate counts rapidlyinflate w
hen the capacity metric assum
es asignificant am
ount of on-chip mem
oryusage; it’s im
portant to know w
hat assump-
tions about mem
ory usage apply to aclaim
ed gate density in these devices.For exam
ple, the device names in the
XC4000E and XC4000EX families are based
on our “maxim
um logic gates” m
etric —a m
easure of logic capacity only thatassum
es no mem
ory usage. How
ever, am
ajor competitor has nam
ed its competing
family based on a m
etric they call “typicalgates” that includes both types of gates,and further assum
es up to 35% on-chip
mem
ory utilization. Superficially, basedon the device nam
es alone, it appears thattheir devices are m
uch larger than ours.H
owever, even a cursory exam
ination ofdevice resources reveals a quite differentstory. For exam
ple, their “20,000-gate”device includes 1,152 4-input look-uptables, 1,344 registers and a m
aximum
mem
ory capacity of 12K bits. In contrast,the Xilinx “13,000-gate” XC4013E includes1,152 4-input lookup tables, an additional576 3-input lookup tables, 1,536 registers,and a m
aximum
mem
ory capacity of18K bits.
This is not to say that Xilinx has not, attim
es, been guilty of “gate-inflation.”. How
-ever, w
e have been more consistent over
the years than most of our com
petitors. We
recently reviewed and slightly revised our
methodology for assigning gate counts for
XC4000 Series and XC5200 family FPG
As.The results of that effort can be seen in theproduct specifications included in our latestdata book. Xilinx application note #059,
“Gate Count Capacity M
etrics for FPGAs,”
explains our capacity metrics and the
methodology used to obtain them
; theapplication note can be view
ed at ourW
ebLINX w
eb site (ww
w.xilinx.com
).Besides being subject to statistical
manipulation, gate counts used as capac-
ity metrics suffer from
another severedraw
back – they usually take only logicblock and on-chip m
emory resources into
account. Modern FPG
As include a host ofother im
portant features. For example,
architectural features in the XC4000 Seriesthat are not reflected in our capacitym
etrics include wide-edge decoders, dedi-
cated arithmetic carry logic, registers and
logic in the I/O blocks, global buffers and
clock distributionnetw
orks, and internalthree-state buffers.These im
portant fea-tures can considerablyboost the capacity andsystem
integrationcapabilities of thesedevices.
Experienced CPLDand FPG
A users realize that there can beconsiderable variation in the logic capac-ity of a given device dependent on factorssuch as how
well the application’s logic
functions match the target device’s archi-
tecture, the efficiency of the development
tools, and the knowledge and skill of the
designer. So, my advice is to apply a
healthy dose of skepticism to CPLD
andFPG
A manufacturers’ gate count m
etrics(yes, even ours). Exam
ine the assump-
tions behind the “gate counting methodol-
ogy.” Better yet, take the time to exam
ineand com
pare all the internal resources ofthe various devices being considered for adesign. Fortunately, w
ith a little experi-ence, m
ost designers can get a goodintuitive feel for the logic capacity of thedevices that they use. ◆
❝Take the time to
examine and com
pare all theinternal resources of the
various devices beingconsidered for a design. ❞
TH
E F
AW
CETT (c
on
’t)
3K/ XC CPLD UNI PLATFORMSCOMPANY NAME PRODUCT NAME VERSION FUNCTION DESIGNKIT 4K 5200 7K9K LIB PC SUN RS6000 HP7
Aldec Active-CAD 2.2 Schematic Entry, State Machine & HDL Included ✓ ✓ ✓ ✓ ✓Editor, FPGA Synthesis & Simulation
Cadence Verilog 2.4 Simulation Xilinx Front End ✓ ✓ 7k ✓ ✓ ✓ ✓Concept 2.1 Schematic Entry Xilinx Front End ✓ 7k ✓ ✓ ✓ ✓FPGA Designer 9504 Topdown FPGA Synthesis Call Xilinx ✓ ✓ 7k ✓ ✓ ✓ ✓Synergy 2.3 FPGA Synthesis Call Xilinx ✓ ✓ 7k ✓ ✓ ✓ ✓Composer 4.4 Schematic Entry Xilinx Front End ✓ 7k ✓ ✓ ✓ ✓
Mentor Graphics Autologic B.x Synthesis Xilinx Synthesis Lib. ✓ ✓ 7k ✓ ✓ ✓ ✓Design Architect B.x Schematic Entry Call Xilinx ✓ ✓ 7k ✓ ✓ ✓ ✓QuickSim II B.x Simulation Call Xilinx ✓ ✓ 7k ✓ ✓ ✓ ✓QuickHDL B.x Simulation Call Xilinx ✓ ✓ 7k ✓ ✓ ✓ ✓
OrCAD Simulate (Win) 6.10 Simulation Call OrCAD ✓ ✓ 7k ✓VST 386+ (DOS) 1.2 Simulation Call OrCAD ✓ 7k ✓ ✓Capture (Win) 7.0 Schematic Entry Call OrCAD ✓ ✓ 7k ✓ ✓SDT 386+ (DOS) 1.2 Schematic Entry Call OrCAD ✓ 7k ✓ ✓PLD 386+ (DOS) 2.0 Synthesis Call OrCAD ✓ 7k ✓
Synario Design Automation ABEL 6.3 Synthesis, Simulation ABEL-XCPLD ✓ ✓ ✓Synario 2.3 Schematic Entry, Synthesis & Simulation SYRO-LCA, SYRO-XEPLD ✓ ✓ ✓ ✓ ✓
Synopsys FPGA Express 1.0 Synthesis Call Synopsis ✓ ✓ TBD ✓FPGA Compiler 3.5 Synthesis Call Xilinx ✓ ✓ ✓ ✓ ✓ ✓ ✓VSS 3.5 Simulation Call Xilinx ✓ ✓ ✓ ✓ ✓ ✓ ✓Design Compiler 3.5 Synthesis Call Xilinx ✓ ✓ ✓ ✓ ✓ ✓ ✓
Viewlogic WorkView Office 7.1.2/7.2 Schem/Sim/Synth Call Xilinx ✓ XACT6 ✓ ✓ ✓ ✓ ✓ ✓ProSynthesis 5.02 Synthesis Call Xilinx ✓ XACT6 7k ✓ ✓ ✓ ✓ ✓ProSim 6.1 Simulation, Timing Analysis Call Xilinx ✓ XACT6 7k ✓ ✓ ✓ ✓ ✓ProCapture 6.1 Schematic Entry Call Xilinx ✓ XACT6 7k ✓ ✓ ✓ ✓ ✓PowerView 6.0 Schem/Sim/Synth/Timing Analysis Call Xilinx ✓ ✓ ✓ ✓ ✓ ✓ ✓
Capilano Computing Design Works 3.1 Schematic Entry/Sim XD-1 ✓ ✓ ✓
Compass Design ASIC Navigator Schematic Entry Xilinx Design Kit ✓ ✓ 7k ✓ ✓Automation X-Syn Synthesis ✓ ✓ ✓
QSim Simulation ✓ ✓ 7k ✓ ✓
Escalade DesignBook 2.0 Design Entry ✓ ✓ ✓ ✓
Exemplar Logic Galileo 3.2 Synthesis/Timing Analysis Simulation Included ✓ ✓ ✓ ✓ ✓ ✓ ✓
IK Technology Co. ISHIZUE PROFESSIONALS 1.06 Schematic Entry/Simulation Xilinx Design Kit ✓ 4Q ✓ ✓ ✓
IKOS Systems Voyager 2.31 Simulation Xilinx Tool Kit ✓ ✓ ✓ ✓Gemini 1.21 Simulation Xilinx Tool Kit ✓ ✓ ✓ ✓
INCASES Engineering GmbH Theda 4.1 Design Entry Xilinx Kit ✓ ✓
ISDATA LOG/iC Classic 4.2 Synthesis LCA-PP ✓ 7k ✓ ✓ ✓ ✓LOG/iC2 4.2 Synthesis Simulation Xilinx Mapper ✓ ✓ 7k ✓ ✓ ✓ ✓
Logic Modeling Corp. Smart Model Simulation Models In Smart Model Lib. ✓ ✓ 7k,9k ✓ ✓ ✓ ✓(Synopsis Division) LM1200 Hardware Modeler Xilinx Logic Module ✓ 7k,9k ✓ ✓ ✓
Model Technology V-System/VHDL 4.4j (PC) Simulation ✓ ✓ ✓ ✓ ✓ ✓4.6a (WS)
Protel Technology Advanced Schematic 3.2 Schematic Entry Included ✓ ✓ 7k ✓ ✓Advanced PLD 3 PLD/FPGA Design & Simulation Included ✓ ✓ 7k ✓
Quad Design Technology Motive 4.3 Timing Analysis XNF2MTV ✓ ✓ ✓ ✓ ✓
SimuCad Silos III 96.1 Schematic Entry & Simulation Included ✓ ✓ ✓ ✓
Sophia Sys & Tech Vanguard 5.31 Schematic Entry Xilinx I/F Kit ✓ ✓ ✓ ✓ ✓
Summit Design Corp. Visual HDL 3.0 Graphical Design Entry/Simulation/Debug EDIF Interface ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓
Synplicity, Inc. Synplify-Lite 2.6b Synthesis Xilinx Mapper ✓ ✓ 9k ✓ ✓ ✓ ✓Synplify 2.6b Synthesis included ✓ ✓ 9k ✓ ✓ ✓ ✓
TopDown Design Solutions V-BAK 1.1 XNF to VHDL translator XNF interface ✓ ✓ ✓ ✓ ✓ ✓
VEDA DESIGN AUTOMATION INC Vulcan 4.5 Simulation XILINX Tool Kit ✓ ✓ ✓
DIA
MO
ND
RU
BYXILINX ALLIANCE-EDA COMPANIES & PRODUCTS-NOVEMBER 1996-1 OF 2
2K/3K/ XC CPLD UNI PLATFORMSCOMPANY NAME PRODUCT NAME VERSION FUNCTION DESIGNKIT 4K 5200 7K9K LIB PC SUN RS6000 HP7
Veribest Veribest VHDL 14.0 Schematic Entry Xilinx FPGA Design Kit 3k,4k ✓ ✓ ✓ ✓Veribest Verilog 14.0 Simulation Xilinx FPGA Design Kit 3k,4k ✓ ✓ ✓ ✓VeriBest Simulator 14.0 Simulation Xilinx FPGA Design Kit 3k,4k ✓ ✓ ✓ ✓ ✓DMM 14.x Design Management Xilinx FPGA Design Kit 3k,4k ✓ ✓ ✓ ✓ ✓VeriBest Synthesis 14.0 Synthesis Xilinx FPGA Design Kit 3k,4k ✓ ✓ ✓ ✓ ✓Synovation 12.2 Synthesis Xilinx FPGA Design Kit 3k,4k ✓ ✓ ✓ ✓PLDSyn 12.0 Design Entry Synthesis ✓ 7k ✓ ✓ ✓VerBest Design Capture 14.x Design Capture Xilinx FPGA Design Kit 3k,4k ✓ ✓ ✓ ✓ ✓
Accolade Design Automation Peak VHDL 2.21 Simulation Xilinx Plus ✓ ✓ ✓Peak FPGA 2.20 Synthesis Included ✓ ✓ ✓ ✓
ACEO Technology, Inc. Asyn 4.1 Synthesis Included ✓ ✓ ✓ ✓ ✓ ✓ ✓Softwire 3.3 Multi-FPGA Partitioning Included ✓ ✓ ✓ ✓ ✓ ✓ ✓Gatran 3.3 ASIC to FPGA Netlist Mapping Included ✓ ✓ ✓ ✓ ✓ ✓ ✓
Acugen Software, Inc. Sharpeye 2.60 Testability Analysis AALCA interface ✓ ✓ 7k ✓ ✓ ✓ATGEN 2.60 Automatic Test Generation AALCA interface ✓ ✓ 7k ✓ ✓ ✓AAF-SIM 2.60 Fault Simulation AALCA interface ✓ ✓ 7k ✓ ✓ ✓PROGBSDL 2.63 BSDL Customization AALCA interface ✓ ✓ 7k ✓ ✓ ✓TESTBSDL 2.63 Boundary Scan ATG AALCA interface ✓ ✓ 7k ✓ ✓ ✓
ALPS LSI Technologies Edway Design Systems Synthesis/Simlulation ✓ ✓ ✓
Aptix Corporation System Explorer 3.1 System Emulation Axess 3.1 ✓ ✓ ✓ ✓ ✓ASIC Explorer 2.3 ASIC Emulation Axess 2.3 4K ✓ ✓
Aster Ingenierie S.A. XILLAS 4.2 LASAR model generation Worst Case Simulation ✓ 7k ✓ ✓ ✓
Auspy Development Co. APS 1.2.3 Multi-FPGA Partitioning Included ✓ ✓ ✓
Chronology Corporation TimingDesigner 3.0 Timing Specification and Analysis Included ✓ ✓ 7k,9k ✓ ✓ ✓ ✓QuickBench 1.0 Visual Test Bench Generator Included ✓ ✓ 7k,9k ✓ ✓ ✓ ✓
CINA-Computer SmartViewer 1.0e Schematic Generation XNF Interface ✓ 7k ✓Integrated Network Analysis
Epsilon Design Systems Logic Compressor Synthesis optimization ✓ ✓ ✓ ✓ ✓ ✓
Flynn Systems Probe 3.0 Testability Analysis Xilinx Kit ✓ ✓ 7k ✓FS-ATG 3.0 Test Vector Generation Xilinx Kit ✓ ✓ 7k ✓CKTSIM 3.0 Logic Analysis Xilinx Kit ✓ ✓ 7k ✓FS-SIM 3.0 Simulation Xilinx Kit ✓ ✓ 7k ✓
Fujitsu LSI PROVERD Top-Down Design System Included 3k,4k ✓
Harmonix Corporation PARTHENON 2.3 Synthesis 4k 7k ✓ ✓
Logical Devices Total Designer 4.7 Simulation & Synthesis Call Xilinx ✓ ✓ ✓ ✓ ✓Ulysa 1.0 VHDL Synthesis Call Xilinx ✓ ✓ ✓ ✓ ✓
MEMEC Design Services One-Hot State Mach. Lib. Grph. Design for One-Hot S.Mach Xilinx Kit ✓ ✓ ✓ ✓ ✓ ✓ ✓
MINC PLDesigner-XL/PL-Synthesizer 3.3/3.2.2 Synthesis Xilinx Design Module ✓ ✓ ✓ ✓
Teradyne Lasar 6 Simulation Xilinx I/F Kit ✓ ✓ ✓
Tokyo Electron Limited ViewCAD 1.2 FLDL to XNF translator XNFGEN ✓
Trans EDA Limited TransPRO 1.2 Synthesis Xilinx Library ✓ ✓ ✓
Visual Software Solutions Statecad 3.0 Grph. Design Entry, Sim., Debug ✓ ✓ ✓ ✓ ✓ ✓ ✓
Zuken Tsutsuji Synthesis/Simulation XNF Interface 3k,4k ✓ ✓ ✓
Zycad Paradigm RP Rapid Prototyping ✓ ✓ ✓Paradigm XP Gate-level Sim ✓ ✓ ✓
EM
ER
ALD
RU
BY
XILINX ALLIANCE-EDA COMPANIES & PRODUCTS-AUGUST 1996-2 OF 2
4
GU
EST E
DIT
OR
IAL
Continued fromthe previous page
stream designers have critical business issues to
solve. To remain com
petitive in today’s market-
place, they have developed their own design
methodologies em
ploying tools and technologyprovided by ED
A vendors. They prefer toleverage their previous investm
ents and experi-ences by using the appropriate com
bination oftools from
their EDA and program
mable logic
suppliers. Therefore, it is critical that theirprogram
mable logic design solutions are
tightly-integrated with their established m
eth-odologies and support industry standards. TheAlliance Series, based on the industry’s m
ostpow
erful set of third-party EDA integration
solutions and partnerships, pro-vides the benefits of an “opensystem
”. Alliance Series productssupport industry standard designinterfaces, such as ED
IF, VHD
L,Verilog and LPM
, and allowdesigners to create and verifydesigns in their chosen third-party ED
A environment.
Through the Xilinx AllianceProgram
, integrated design solu-tions for the design of Xilinx de-
vices are available from a broad array of third-
party EDA suppliers. The Alliance Program
isstructured to assure that Xilinx users have accessto the w
idest variety of high-quality third-partytools, certified to w
ork with Xilinx products.
Currently, the Xilinx Alliance Program includes
more than 100 partners, representing over 160
products, who have been selected for their contri-
bution to Xilinx development and their respon-
siveness to customer needs. The Alliance Program
supports these partners with technical inform
ationand assistance on an ongoing basis and, in turn,the partners provide Xilinx w
ith input regardingproduct interfaces and directions.
System Level Integration (SLI)
High-density users, typically the early
adopters, require leading-edge technology tohelp solve their very large, com
plex and per-form
ance-driven design problems. These users
focus on advanced functionality and need thenew
est, most advanced technologies. As pro-
gramm
able logic devices increase in density,designing at the gate level is no longer a real-istic approach.
SLI tools go far beyond just delivering supportfor higher-gate-count designs. Xilinx SLI optionsfacilitate the design of system
-level functions inhigh-density, high-perform
ance programm
ablelogic devices. Intended as “add-ons” to the Alli-ance and Foundation Series products, current SLItools include the LogiCore m
odules. LogiCorem
odules are fully-verified, drop-in system level
modules, such as target and initiator PCI bus
interfaces. These tools can dramatically shorten
design cycles and facilitate complex, system
-levelintegration w
ithin programm
able logic devices.
Next G
eneration Core Software Platform
The upcoming upgrade to the XACTstep
software platform
incorporates our next-gen-eration core softw
are environment, leveraging
the industry-leading technologies from the
merger betw
een Xilinx and NeoCAD
. Thisnew
core technology includes timing-driven
optimization, m
apping, FPGA placem
ent androuting and CPLD
fitting algorithms; it w
ill bethe softw
are platform for all existing and fu-
ture Xilinx IC product development and sup-
port. This new release w
ill still incorporatem
any aspects of the popular XACTstep version6 softw
are environment, providing users w
ithan easy m
igration path and protecting previ-ous tool and training investm
ents.In sum
mary, upcom
ing releases of theXACTstep product series are being developed toinclude the latest technological advancem
ents,including enhanced SLI product offerings, value-added ED
A technologies and additional Xilinxdevice support.. These advancem
ents will deliver
increased ease-of-use benefits for rapid designim
plementation flow
s, enhanced integration andhigh-quality results. In addition, Xilinx integratededucational tools w
ill round out the technologiesbeing delivered.
Future programm
able logic design solutionsfrom
Xilinx will place m
ore emphasis on m
ak-ing users of program
mable logic better overall
system designers, as w
ell as ensuring rapiddesign im
plementation into Xilinx silicon. ◆
❝The upcoming
upgrade to theXACTstep softw
areplatform
incorporatesour next-generation
core software.❞
Diamond: These partners have strong strategic relation-ships with Xilinx and have a direct impact on our re-leases. Typically, Xilinx is directly involved in the devel-opment and testing of the interface to XACTstep softwarefor these products.
Ruby: These partners have a high degree of compatibilityand have repeatedly shown themselves to be significantcontributors to our users’ development solutions.
Emerald: Proven Xilinx compatibility
Items that have changed since the last issue (XCell 22) are in color.The following entry was removed: The Rockland Group.
29
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R
GUEST EDITORIAL
3
30
One Size Does Not Fit All:Development System Products & Strategies
by KENN PERRY ◆ Director of Software Marketing
One design tool configuration cannot meet the needs of all program-mable logic designers. Overall, today’s designers are looking for top-down,language-driven design support that enables system-level integration withintheir programmable logic design methodologies. However, user requirementsand expectations vary considerably, dependent on their design methodologies,cost considerations and time-to-market pressures.
Xilinx is addressing the needs of the low-, mid- and high-density classes ofdesigners with three XACTstep™ software solutions: the Foundation Series™,Alliance Series™ and System Level Integration (SLI)™ options. Thus, Xilinx userscan choose between a complete, tightly integrated design system supportingindustry-leading HDLs, schematic capture and simulation (the FoundationSeries), or the integration of Xilinx implementation tools into their chosen EDAenvironment, leveraging defacto industry standards (the Alliance Series). Addition-ally, comprehensive system-level design is supported by SLI options, such asLogiCore™ modules, that enable users to achieve high density and performancewhile greatly reducing time-to-market. These products are available today.
Foundation SeriesDesigners of low-density FPGAs and CPLDs, the largest group of users, typically
are cost-sensitive and prefer easy-to-use, push-button, integrated software solutionsthat support both schematic and language-based entry methods. Intolerant ofdelays, defects or risks, these users desire a complete, “shrink-wrapped” solution.The Foundation Series solutions provide the technological “foundation” upon whichsupport for higher-density Xilinx devices can be built.
Xilinx is the first programmable logic vendor to offer a low-cost, shrink-wrappedsolution that integrates schematic entry, HDL synthesis and gate-level simulation forboth CPLDs and FPGAs. The goal of the Foundation Series solution is to provide anenvironment where the user can open the box, install the software, get up-to-speedquickly and complete designs successfully without assistance — although support isreadily available if needed. From a single environment, users have access to HDLsynthesis (VHDL and ABEL initially), schematic entry, gate simulation and core imple-mentation tools, making PLD development simple and easy without compromisingdesign flexibility or performance. The Xilinx continuum of software functionality anddevice technology enables users to expand their Foundation Series system capabilitieswith the changing demands of their design requirements.
Alliance Series and the Alliance ProgramThe mainstream segment of programmable logic, encompassing mid-range den-
sity users (10K to 15K gates), is the fastest growing segment in the programmable logicmarket. With decreasing market windows and increasing technology demands, main-
Continued on the next page
❝Xilinxis addressing the needs
of the low-, mid- and
high-density classes of
designers.❞
XILINX ALLIANCE-EDA CONTACTS-NOVEMBER 1996COMPANY NAME CONTACT NAME PHONE NUMBER E-MAIL ADDRESS
Accolade Design Automation Dave Pellerin (800) 470-2686 [email protected]
ACEO Technology, Inc. Ray Wei (510) 656-2189 [email protected]
Acugen Software, Inc. Nancy Hudson (603) 881-8821
Aldec David Rinehart (702) 456-1222 x12 [email protected]
ALPS LSI Technologies, Inc. David Blagden 441489571562
Alta Group Paul Ekas (408) 523-4135 [email protected]
Aptix Corporation Henry Verheyen (408) 428-6209 [email protected]
Aster Ingenierie S.A. Christopher Lotz +33-99537171
Cadence Ann Heilmann (408) 944-7016 [email protected]
Capilano Computing Chris Dewhurst (604) 522-6200 [email protected]
Chronology Corporation MikeMcClure (206) 869-4227 x116 [email protected]
CINA-Computer Integrated Network Analysis Brad Ashmore (415) 940-1723 [email protected]
Compass Design Automation Marcia Murray (408) 474-5002
Epsilon Design Systems, Inc. Cuong Do (408) 934-1536 [email protected]
Escalade Rod Dudzinski (408) 654-1651
Exemplar Logic Shubha Shukla (510) 337-3741 [email protected]
Flynn Systems Matt Van Wagner (603) 598-4444 [email protected]
Fujitsu LSI Masato Tsuru +81-4-4812-8043
Harmonix Corporation Shigeaki Hakusui (617) 935-8335
IK Technology Co. Tsutomu Someya +81-3-3839-0606 [email protected]
IKOS Systems Brad Roberts (408) 366-8509 [email protected]
INCASES Engineering GmbH Christian Kerscher +49-89-839910 [email protected]
ISDATA Ralph Remme +49-72-1751087 [email protected]
Logic Modeling Corp. (Synopsis Division) Marnie McCollow (503) 531-2412 [email protected]
Logical Devices Chip Willman (303) 279-6868 [email protected]
Memec Design Services Maria Agular (602) 491-4311 [email protected]
Mentor Graphics Sam Picken (503) 685-1298 [email protected]
MINC Kevin Bush (719) 590-1155
Minelec Marketing Department +32-02-4603175
Model Technology Greg Seltzer (503) 526-5465 [email protected]
OrCAD Mike Jingozian (503) 671-9500 [email protected]
Protel Technology Luise Markham (408) 243-8143
Quad Design Technology, Inc. Britta Sullivan (805) 988-8250
SimuCad Richard Jones (510) 487-9700 [email protected]
Sophia Sys & Tech Tom Tilbon (408) 232-4764
Summit Design Corporation Ed Sinclair (503) 643-9281
Synario Design Automation Jacquelin Taylor (206) 867-6257 [email protected]
Synopsys Lynn Fiance (415) 694-4289 [email protected]
Synplicity, Inc. Alisa Yaffa (415) 961-4962 [email protected]
Teradyne Mike Jew (617) 422-3753 [email protected]
Tokyo Electron Limited Shige Ohtani +81-3-334-08198 [email protected]
TopDown Design Solutions Art Pisani (603) 888-8811
Trans EDA Limited James Douglas +44-703-255118
VEDA DESIGN AUTOMATION INC Kathie O’Toole (408) 496-4515
Veribest Mike O’Donohue (303) 581-2330 [email protected]
Viewlogic John Dube (508) 480-0881 [email protected]
Visual Software Solutions, Inc. Riky Escoto (800) 208-1051 [email protected]
Zuken Makato Ikeda +81-4-594-27787
Zycad Charlene Locke (510) 623-4451 [email protected]
Inquiries about the Xilinx Alliance Program can be e-mailed to [email protected]
Changes since last issue (XCell 22) printed in color. • The following two entries deleted: ITS, The Rockland Group
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FR
OM
TH
E F
AW
CETT
PLD Capacity&
‘Gate Counting’
By BRADLY FAW
CETT◆◆ ◆◆◆
Editor
R
XCell
Please direct all inquiries,com
ments and subm
issions to:
Editor: Bradly Fawcett
Xilinx, Inc.
2100 Logic Drive
San Jose, CA 95124Phone: 408-879-5097FAX
: 408-879-4676E-M
ail:brad.fawcett@
xilinx.com
©1996 Xilinx Inc.
All rights reserved.
XCell is published quarterly forcustom
ers of Xilinx, Inc. Xilinx, theXilinx logo and XACT are registeredtradem
arks; all XC-designatedproducts, XACTstep, LogiCore,Foundation Series, Alliance Series,NeoCAD
, FastFLASH, and EZTag are
trademarks; and “The Program
mable
Logic Company” is a service m
ark ofXilinx, Inc. All other tradem
arks arethe property of their respective ow
ners.
2
Continued on page 5
Every user of program
mable logic at
some point faces the question, “H
ow large a
device will I require to fit m
y design?”O
ne of the most diffi-
cult problems facing those
of us who m
ake, market
and sell programm
ablelogic devices is establish-ing m
eaningful capacitym
etrics for our devices.W
e would like to supply
potential users with
metrics that provide an
accurate indication of theam
ount of logic that can be implem
entedw
ithin a given CPLD or FPG
A device, and,at the sam
e time, reflect the relative capac-
ity of our devices compared to other m
anu-facturers’ com
peting products. Unfortunately,
these two goals are often at odds w
ith oneanother. In fact, a look at the density claim
sthat I see in som
e PLD advertisem
entsthese days rem
inds me of the old saying
that there are three types of falsehoods -lies, dam
ned lies and statistics.O
f course, what is a problem
for us isalso a problem
for potential programm
ablelogic users, w
ho must sift through the com
-peting claim
s of the various vendors and tryto select the m
ost cost-effective solution fortheir application.
At the root of the problem is the m
ulti-plicity of available program
mable logic
architectures. Since each family of devices
tends to have a unique architecture for itslogic resources, direct com
parisons, such asm
erely counting the number of available
logic blocks or macrocells, are not alw
ayssufficient. (H
owever, in som
e instances,direct com
parisons of available resourcesprobably could be used a bit m
ore oftenthan I think they are).
Most vendors, including Xilinx, describe
device capacities in terms of “gate counts”
— the num
ber of 2-input NAN
D gates that
would be required to im
plement the sam
efunction. This m
etric has the advantage ofbeing fam
iliar to ASIC designers and, intheory, allow
s the comparison of program
-m
able logic device capacities to those oftraditional, m
ask-programm
ed gate arrays.But FPG
A and CPLD devices do not
consist of arrays of 2-input NAN
D gates;
they have structures such as look-up tables,m
ultiplexers and flip-flops for implem
entinglogic functions. Thus, “counting gates” is farfrom
an exact science; different vendorsapply varying m
ethodologies to determine
gate counts.All too often, gate counting becom
es agam
e of “one-upmanship” am
ong compet-
ing vendors. In fact, it seems to m
e thatsom
e marketeers decide w
hat gate capacitythey w
ant to claim, and then design their
metrics to reach that num
ber. For example,
in ancient times (that is, a couple of years
ago), one of our competitors w
as bringing alarge FPG
A to market w
ith a claimed ca-
pacity of 22,000 gates; the device had evenbeen nam
ed to reflect that claim. Then
Xilinx announced and started sampling the
“25,000 gate” XC4025. Suddenly, the com-
peting device somehow
“grew” an addi-
tional 4,000 gates and was renam
ed andbrought to m
arket as a “26,000 gate” FPGA.
With the advent of FPG
As like theXC4000 Series that offer on-chip m
emory
as well as logic resources, the issue is
further complicated by the use of “m
emory
gates” in addition to “logic gates”. Each bitof m
emory counts as four gates. This factor
can quickly inflate gate counts. For ex-am
ple, a single 4-input look-up table (LUT)
XILI
NX IN
DIV
IDUA
L PR
OD
UCTS
XIL
INX
PAC
KAG
ES
XILINX RELEASED SOFTWARE STATUS-NOVEMBER 1996XILINX PART CURRENT VERSION BY PLATFORM LAST PREVIOUS
PRODUCT PRODUCT PRODUCT REFERENCE PC1 SN2 HP7 UPDT VERSION NOTES/KEY CATEGORY DESCRIPTION FUNCTION NUMBER 6.2 4.1.X 9.01 COMP RELEASE FEATURES
CORE XEPLD XC7K Support Core Implementation DS-550-xxx 6.0.1 5.2.1 5.2.1 7/96 5.2/6.0 PC update by request only
* XABEL-CPLD XC7K, XC9500 Support Entry/Simulation/Core DS-571-PC1 6.1.1 7/96 6.10 New version w/XC9500; First ship 4/29/96
* XACT-CPLD XC7K, XC9500 Support Core + Interface DS-560-xxx 6.0.1 6.0.1 6.0.1 7/96 6.0
Mentor 8.4=A.4 Interface and Libraries DS-344-xxx 5.2.1 5.2.1 7/96 5.20
OrCAD Interface and Libraries DS-35-PC1 6.0.1 7/96 6.0 Support for SDT+, VST+ v1.2
Synopsys Interface and Libraries DS-401-xxx 5.2.1 5.2.1 7/96 5.20 Includes XC5200 X-BLOX Support
Viewlogic PROcapture Interface and Libraries DS-390-PC1 6.0.1 7/96 5.2/6.0 Includes PRO Series 6.1
Viewlogic PROsim Interface and Libraries DS-290-PC1 6.0.1 7/96 6.0 Includes PRO Series 6.1
Viewlogic Interface and Libraries DS-391-xxx 6.0.1 5.2.1 5.2.1 7/96 6.0
XABEL Entry,Simulation,Lib, Optimizer DS-371-xxx 5.2.1 5.2.1 5.2.1 7/96 5.2/6.0 Now available on HP7
XBLOX Module Generator & Optimizer DS-380-xxx 5.2.1 5.2.1 5.2.1 7/96 5.2/6.0
E Verilog 2K,3K,4K,7K Libraries Models & XNF Translator ES-VERILOG-xxx 1.00 1.00 na na Sun and HP
E XC4000EX XC4000EX Support Core Implementation DS-4EX-WS beta beta na na Available to pre-determined users
SILICON SUPPORT
2K 3K 4K/E 5K 7K 9K
Cadence X X X X X X DS-CDN-STD-xxx 5.2.1 5.2.1 7/96 5.20
Mentor X X X X X X DS-MN8-STD-xxx 5.2.1 5.2.1 7/96 5.20 No AP1 update
Mentor X X X X X X DS-MN8-ADV-xxx 7.00 7.00 na na
U OrCAD X X X X X X DS-OR-BAS-PC1 6.0.1 7/96 6.0 Customer w/v6.0 will receive v6.0.1 update
OrCAD X X X X X X DS-OR-STD-PC1 6.0.1 7/96 6.0
Synopsys X X X X X DS-SY-STD-xxx 5.2.1 5.2.1 7/96 5.20 Includes DS-401 v5.2
Synopsys X X X X X DS-SY-ADV-xxx 7.00 7.00 na na Includes DS-401 v5.2
U Viewlogic X X X X X X DS-VL-BAS-PC1 6.0.1 7/96 6.0 Customer w/v6.0 will receive v6.0.1 update
Viewlogic X X X X X X DS-VL-STD-xxx 6.0.1 5.2.1 5.2.1 7/96 5.26.0 DA1 platform remains at v6.0
Viewlogic X X X X X X DS-VL-ADV-xxx 7.00 7.00 7.00 na na
Viewlogic/S X X X X X X DS-VLS-BAS-PC1 6.0.1 7/96 6.0 Includes PROSeries 6.1
Viewlogic/S X X X X X X DS-VLS-STD-PC1 6.0.1 7/96 6.0 Includes PROSeries 6.1
Viewlogic/S X X X X X X DS-VLS-EXT-PC1 6.0.1 7/96 6.0 Incl PROSeries 6.1/PROsynth 5.02X
Viewllogic/S X X X X X X DS-VLS-ADV-PC1 7.00 na na
U 3rd Party Alliance X X X X X X DS-3PA-BAS-xxx 6.0.1 7/96 na Customer w/v6.0 will receive v6.0.1 update
3rd Party Alliance X X X X X X DS-3PA-STD-xxx 6.0.1 5.2.1 5.2.1 7/96 5.2/6.0 Includes 502/550/380
3rd Party Alliance X X X X X X DS-3PA-ADV-xxx 7.00 7.00 7.00 na na Includes 502/550/380 & Foundry
Foundation Series X X X X X X DS-FND-BAS-PC1 6.0.1 7/96 6.0 Includes support for XC4000E and XC9500
Foundation Series X X X X X X DS-FND-BSV-PC1 6.0.1 7/96 6.0 Includes support for XC4000E and XC9500
Foundation Series X X X X X X DS-FND-STD-PC1 6.0.1 7/96 6.0 Includes support for XC4000E and XC9500
Foundation Series X X X X X X DS-FND-STV-PC1 6.0.1 7/96 6.0 Includes support for XC4000E and XC9500
LogiCore-PCI Slave X LC-DI-PCIS-C 1.10 1.10 1.10 na na Requires signed license agreement
LogiCore-PCI Master X LC-DI-PCIM-C 1.10 1.10 1.10 8/96 1.0 Requires signed license agreement
Evaluation X X X X X X DS-EVAL-XXX-C 2.00 2.00 2.00 na na PC, Sun, HP kits with v5.2.1 and v6.0.1
KEY: N=New Product E= Engineering software for in-warranty users by request only U= Update by request only * = Check BBS or FTP site.
31
Issue 23
Fourth Quarter 1996
GENERALFawcett: PLD Capacity .................................. 2
Guest Editorial: Software Strategies ........... 3
Customer Success Stories
FPGAs: Supercomputing Systems ........ 6
RC Company of the Quarter ................. 8
Xilinx Joins VSI Alliance ................................. 9
New AppLINX CD-ROM ............................... 9
Financial Results ............................................ 10
New Product Literature ............................... 10
Upcoming Events .......................................... 10
WebLINX and SmartSearch ........................ 11
Training Update ............................................. 12
First Hands-On Workshopon Reconfigurable Computing .............. 12
PRODUCTSNew XC9500 ISP Products in Production .. 13
XC4000 Family Update:5 Million Units Sold .................................. 13XC4000EX Family Begins Production .. 13
Xilinx Discontinuance Policy ...................... 14
XC4000A/H FPGA Devices Discontinued . 14
DEVELOPMENT SYSTEMSNew CPLD Software Updates ................... 15
VITAL Model Support for CPLDs ............. 15
HW-130 Update ............................................ 15
HINTS & ISSUESImplementing Median Filters ..................... 16
XC9500 ISP on the HP3070 ...................... 17
Downloading wtih Embedded Processor ... 18
Technical Support Resources .................... 19
Running XACTstep Under Windows NT .... 20
Technical Questions & Answers ......... 22-23
Component Availability Chart ............. 24-25
Programming Support Charts .............. 26-27
Alliance Program Charts ........................ 28-30
Development Systems Chart ..................... 31
Fax Response Form ....................................... 32
The ProgrammableLogic CompanySM
Inside This Issue:
T H E Q U A R T E R L Y J O U R N A L F O R X I L I N X P R O G R A M M A B L E L O G I C U S E R S
R
40
FAX in Your Comments and SuggestionsTo: Brad Fawcett, XCell Editor Xilinx Inc. FAX: 408-879-4676
From: ________________________________________ Date: ____________
❏❏❏❏❏ Please add my name to the XCell mailing list.
NAME
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ADDRESS
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FAX RESPONSE FORM-XCELL 23 4Q96 XCELLCorporateHeadquartersXilinx, Inc.2100 Logic DriveSan Jose, CA 95124Tel: 408-559-7778Fax: 408-559-7114
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R
New AppLINXCD-ROM Released!
Downloading CPLDs Withan Embedded ProcessorAn embedded processor can be used to controlCPLD programming, resulting in considerableflexibility throughout the product life cycle...
See Page 18
5,000,000 and CountingThe world’s most popular FPGA, the XC4000 Series, hits two milestones...5M units shipped and the first production of the XC4000EX family...
See Page 13
The latest AppLINX CD-ROM contains a collectionof applications and product information useful fordesigners working with Xilinx devices...
See Page 9
DESIGN TIPS & HINTS
XC9500 CPLDs inVolume ProductionFour members of the in-system-programmable XC9500 CPLD familyare ready for designers looking for thebest ISP solution...
See Page 13
GENERAL FEATURES
PRODUCT INFORMATION
Xilinx wishes you and your family
a happy and healthy holiday season!