ISSCC 2014 Short Course Transcription Design Strategies for Wearable Sensor Interface Circuits – From Electrodes to Signal

Processing

Instructor: Jerald Yoo

1. Introduction Thank you Prof. Sansen, my name is Jerald Yoo from Masdar Institute of Science and Technology in Abu Dhabi in United Arab Emirates. So today I would like to talk about design strategies for wearable sensor interface circuits.

2. Outline This is the outline of my talk. I’ll first begin with introduction to the wearable sensor environment where you have some different characteristic or environment than the implantable or the conventional instrumentation amplifiers. And I’ll also briefly discuss the design tradeoffs. My talk will be primarily focusing on wearable electronics so it will be a very good complement to the previous speakers’ talks. And then I’ll move on to electrode and interface, where again I would like to emphasize on the wearable side with some fabric electrodes that we have developed, and then move on to the readout circuits and see some topologies. And again, just like the previous speakers, I’ll see the pros and cons of each topology and depending on your application; you can choose your own. And then I’ll move on to the wearable sensor system. In here I would also present an EEG based seizure testing system where you can have the epileptic seizure testing with the EM or machine learning algorithm just like Tim mentioned earlier today, and then I’ll summarize my talk.

3. Continuous Healthcare Before moving on, let’s see what the continuous healthcare concept is. This graph here shows the glucose level of a patient suffering from diabetes throughout the day. If you see this blue line over here, it’s the normal band for the typical blood glucose level. If you sample the blood or went to see a doctor in A or B, then you would be considered as normal. But as you can see from the graph, that’s not the case. You really have to see the glucose levels throughout the day to see if this person is really diabetic or not. That’s why you sample at least five times a day if you’re diabetic. And this thing is really similar in many, many different kind of chronic diseases. For sample, seizure, you don’t when it will happen. And then in order to detect it correctly, you really need

to continuously monitor your seizure activity if it is from EEG, you have to monitor EEG from surface ECG probably, for about one or two weeks or even longer. So here, the characteristic is that the sooner you detect this disease, or chronic diseases, the better prognosis you’ll have, that’s another important thing that you have to remember. That’s why the NIH, has introduced 4Ps of medicine which is predictive, personalized, preemptive, and participatory, so that’s why we need to continuous health monitoring to achieve these 4Ps of medicine.

4. Continuous Health Monitoring: Needs Now, I will also summarize the needs for the continuous health monitoring in this slide, with three different categories. The first is safety and convenience; it seems fairly obvious but let’s go one by one. So safety is to minimize skin irritation, I’m talking about again, the wearable health care here to minimize the skin irritation. If you see the photo over here, this is what happens to many, well I wouldn’t say many, but some of the patients, when you wear the conventional three electrode or the wet electrode over an extended period of time. And this is similar to my case where I wear the three miniature electrodes, in four hours, my skin starts to irritate. So the other important factor here is to remove battery sensor nodes preferably, if not, smallest battery as possible so that you can have the schematic scaling. This is again due to the fact that you need to monitor over an extended period of time, preferably before about two or three days or even weeks, you don’t want to wear the lithium battery on your skin and then take a shower. Or you don’t want to have the perspiration meeting with the lithium batteries. That’s why we need to have these facts. And then the second thing is the convenience where you need to remove annoying wires as much as possible. So if you have experience using the health care monitor, then you will know what I’m talking about here. These wires are really irritating and cumbersome when you are doing the glucose monitoring for two days, you can’t take a shower, and these wires are really cumbersome that it limits your movement, and purely in the electrical point of view, these wires are really a source of making motion artifacts and these wiring artifacts even worse. So you need to have it as short as possible. And another fact is to have a disposable sensor if possible and then of course, they’re easy to use, that’s another important factor. When it comes to reliability and security, it’s something that we also have to emphasize. The vital signals should not be lost after removing the monitor, nor do you want someone to eavesdrop your signal, your vital signal for example, for sure. And of course the fault-tolerance is also very important. So if you want to process it for example, locally, and then if you can use the data within the sensor auto sensors itself, that’s preferable over the data sending over the RF channel and this is also very important because RF, using RF on your body, around your body is not efficient because human body really absorbs the energy from 1GHz to 10GHz range. So it’s preferable to have local processing if possible to minimize the radio usage.

And security is another important fact of course, to have protection of personal health information of course. And a low cost and disposable sensor is very important because you as a user do not want to use the sensor that someone else has used for an extended period of time.

5. Patch Sensors Now in order to make it happen, patch sensors were introduced. Many, many active players are here; I’ve only shown some examples here, but many Japanese, Singapore, Taiwanese, and Chinese groups and even Europe, there are many, many good companies working on it. Toumaz Technology has introduced the sensium, the patch type ECG sensor in 2008 in this conference. KAIST is also an active group here, and also of course IMEC where the second speaker is involved in, it’s producing some very good patch sensors. So these sensors have disposable easy-to-use convenience factors where I summarize as DEC, and you also have to have energy-efficient noise-tolerant I/F integrate circuit to have these patch sensors reasonable. That’s what I’m going to cover in today’s talk.

6. Design Consideration Before moving on, let’s summarize the design consideration as a circuit designer. Not only about the circuit, but also about the patch sensor itself, the first and the foremost important thing is the form factor of course. You want to have a minimum size as much as possible which gives you a lot of challenges that we’re going to discuss in the coming slides. And also practical limitation on power source should be also considered. Well as I said, if possible you want to remove the battery from sensor node or have the minimum power source as possible, minimum size battery as much as possible, which you should consider using wireless powering or energy scavenging. Or you can have the battery or renewable energy or super cap to complement that. Well here we have to think about, one thing to keep in mind is that the core power consumption is not necessarily what the battery actually sees. This is something that we often forget; we have to take care of the IO, as well as the EM of the regulators and these things as well. Also I’d like to address the important fact that the long term monitoring is often not considered and that’s where the wearable healthcare applications are really looking for.

7. Bio-Potential You have seen this slide several times today, but just to summarize once more, just as a refresher, the many bio potential signals lies within 1 kHz range where unfortunately you have the electrode offset, more seriously 1/F noise, flicker noise intruding into that exact same bandwidth. Not to mention this 50Hz, 60Hz noise interference. I don’t know if you have any experience of measuring such interferences with your oscilloscope, but if you have a chance to, please go to your lab and grab the probe of your oscilloscope and see how much 50Hz noise you’re getting that are coupled into it.

In fact, the amount of voltage you’re getting from the screen of your oscilloscope is not in the millivolt region or tens of millivolts, but its volts. Remember the ECG and EMG signals are in microvolts and millivolts region. The common mode interference with 60Hz you’re getting is volt region. That’s why it’s very important to good circuit topology tools to reject those interferences.

8. Wet and Dry Electrodes I’d also like to mention briefly about wet and dry electrodes. Wet electrodes are very effective and very good most of the time, but sometimes it’s not efficient, especially when it comes to the long term monitoring because as I said, primarily because of the skin irritation and also inconvenience related to the electrolyte. So you can also use the dry electrode as a complement not an alternative because obviously except for this less skin irritation, almost all the factors are bad and worse in dry electrodes. So it’s only a complement, not as an alternative. But first and foremost important thing of the dry electrode is that it has the contact impedance much higher than that of the wet electrode and we’ll see that in coming slides. Consequently you’ll have more noise and longer stabilization time as well. And the fact that we have the noise, thermal noise in proportion with the electrode impedance, is also giving challenges to us.

9. Patterned Fabric Electrode How do you make the dry electrode? Well there are many ways of doing it but the way we have implemented is to use the fabric circuit board which you can use this screen printing on fabric itself to generate or fabricate a fast and convenient electrodes and you can use that with adhesive bandages to form the firm connection to your skin and it’s a very fast and easy low cost solution to implement the dry electrode. And you can also do the chip on boarding directly on fabric with the silicon of the chip directly bond wired to have this bandage type sensor that you see in this photo over here.

10. Dry Fabric Electrode: Zelec vs. Time Now before moving on, we have to also see what is the real impedance of this skin-electrode impedance of the dry fabric electrode. As you have seen earlier today, in the morning, how to have the correct measurement environment is really crucial. And just to have a control set, we have used the handcuff to have a uniform pressure on the skin, obviously this is a high pressure but in order to move the artifact, for example, if you pull the wire, you still want to have a firm connection, we used for 3mm, we used all electrodes the same environment to measure it with a load resistance of 4kΩ. If you want to measure the phase of the electrode, you need to have three electrode configurations for just in magnitude; you just need two of them as you can see.

So if you see the time versus impedance plot, as Prof. McAdams mentioned earlier this morning, you need to stabilize the time, that’s what you see over here, and what we’ve observed, you need at least 10 or 20 minutes of stabilizer in time to have a reasonable stable impedance of the dry electrode. And also with respect to the size or the area of the dry electrode, you can see that 8-10cm2 can give you similar impedance as the 3M electrode.

11. Dry Fabric Electrode: Zelec vs. Frequency You can also see the frequency response here, after 20 minutes, which is sufficient stabilizers in time I’ll say, at the same pressure of 40mmHg, and then you can see the difference between the different area of dry electrodes, I’m talking about the dry fabric electrode, versus the skin-electrode showing similar characteristic. The only difference is the magnitude of the impedance. So as a rule of thumb, we have concluded the dry electrode is applicable when monitoring over 20 minutes, meaning that the stabilizing time as you saw in the initial 2 or 3 minutes, is very rapidly dropping and the stabilization time is required. And also area of over 2cm2 is preferable.

12. Annealing Effects We also saw annealing effects after you do your screen printing. It’s better to have annealing to have a firm attachment, as well as the crystalline of the structure of the silver piece. And impedance change is negligible and now we can explain this with Prof. McAdams’ comment, that actually the material is not that important.

13. Electrodes Materials You also see the different materials; this is not in effort to decrease metron itself, in order to have a more stable or firm connection, if you have some rough surface, then you will have a better attachment to the skin, or stretching of the skin, you can counteract better, that’s why we also use some silver paste with tungsten, copper, and all that together.

14. Electrode Materials Here are some different plots for that. We can see that actually the impedance of different powders included have a higher impedance but in terms of motion artifacts, this may be better.

15. Dry Electrode Characteristics: ECG We also briefly measured the distance versus ECG amplitude difference. Obviously the farther you have between two electrodes, the better and stronger signal you will get, but at the same time, you have to care about if you’re talking about the wired electrodes, you have to care about these common mode interference coming from the ceiling from the 50Hz noise.

If you have a wide area between the two wires, that’s the source. The more area you have between the wires, the more common mode interference you will get. So that’s why you twist the wires when you’re doing the instrumentation. But if you’re using patch sensors, or a very small area without wires, then you can minimize it from the first place.

16. Electrode Distance vs. Signal Strength These are the results, the initial results. You can see that the electrode distance between two differential pairs, if it is around 10 cm around the chest, gives you the maximum ECG magnitude after 40 dBm amplification. But it’s not always applicable because you are sometimes limited by the form factor of the patch itself.

17. Fabric Electrode Summary And here is the summary for the fabric electrode. We have used the fabric electrode with the screen printing after annealing. Electrodes areas from 2 to 10cm2, materials you can use, the silver paste on fabric, you can also selectively add copper, tungsten, or the iron itself is an optional for better attached to skin, and the stabilization time as I said, is at least 10 minutes, so this is not good for clinical testing, obviously for long term monitoring. Skin-electrode impedance ranges from 100k up to 1MΩ at DC, and at about 100Hz, 30kΩ up to 200 kΩ after stabilization, so it’s quite large. For the application as I said, it’s long term physiological signal monitoring and recording.

18. Outline Okay, so now we have seen some dry electrodes with a fabric circuit board, so now let’s move on to the readout circuits.

19. Outline - Readout Circuits Which I will first talk about instrumentation amplifier basics for those of some you who are not familiar with instrumentation. And then I’ll move on to the offset and noise cancellation which is very crucial, especially in a wearable environment. And then I’ll talk about circuit topologies for wearable environments as well.

20. Wearable Readout Circuit Challenges Okay, I have summarized some aggressors so to speak in wearable environment for the readout circuits. The most obvious thing is, this is an example of EEG but the signal source from the beginning is very small as you have already seen twice or three times today. It’s at max 100uV, and electrode offset is around +-300mV, and the electrode impedance difference caused by the different area or mismatch of the electrode itself, is also may go up to 100 kΩ which is a big difference. Obviously as I said, 50Hz, 60Hz, common mode noise is very significant, as I said

too, there’s also our friend, 1/F noise which we can’t get rid of, this is something that you have to live with, which as you already know, the 1/F noise is inversely proportional to W times L area of the oxide layer. As you can see, unlike the thermal noise of the amplifier, even if you increase the power consumption or increase the current, your 1/F noise doesn’t change. This is why we have to take care of this in a smart way. And there’s also drift and a limited CMRR/PSRR caused by the topologies most likely or the off-chip devices which we’re going to see one by one in the coming slides.

21. Impact of an Offset Okay, so why is there an offset? We’ve already seen that when you have an amplifier here with zero input, let’s say if you have a shorted differential amplifier, you’re expecting zero, zero volt at the output but in a real situation it’s never the case, you might have to have some compensating voltage to move out the output voltage, and that’s what the core of the offset is. But let’s assume that you have zero offset of this very easy to calculate amplifier where you have the source impedance of to 1 kΩ and a feedback resistance of to 100 kΩ, then you’re expecting gain to be 100, minus 100 of course, so if there’s a zero offset, you’re expecting the offset to be -1000 mV, okay? Now let’s assume you have around 4 mV offset at the input of the negative terminal, then the things change. As you can see this difference between this virtual ground is 6mV, and then you can see that the output is actually -596mV which is around roughly half of what we got before and 4mV of offset is not that pessimistic. If you have an offset matched CMOS differential pair, this may reach up to a millivolt of offset. So unless you have a proper offset cancellation, you will easily lose a lot in gain, which means you’ll lose a lot in CMRR as well.

22. 1-Amp IA So with that in mind, let’s look at the 1-amp instrumentation amplifier. Can we just use 1 amp, 1 opamp instrument for an instrumentation amplifier? Well the answer is yes and no depending on your application. Let’s look at the basics of this 1 op amplifier, as you already know, the differential gain will be the feedback resistance reduced by the input resistance, assuming these R3 and R4 are matched and R1 and R2 are matched, then the differential gain is R4 divided by R2. The good news about this amplifier, is its very simple, and input voltage range is very large, it’s not limited, whereas the down side, especially with the wearable environment, is that the input impedance is limited because it’s subject to the input impedance over here. You can’t increase R1 and R2 too much because then you’ll have to deal with lower gain, otherwise you have to use a larger resistance in the feedback which will limit your area. And there’s no compensation for noise and also this large impedance, I mean large resistance will result in thermal noise. And also CMRR is limited because of the matching.

23. The Classic 3-Amp IA5 Well we have already seen this in the previous speaker’s slides; the classic 3-amp instrumentation amplifier is introduced to overcome the problems of the 1-amp instrumentation amplifier. Now you have A1 and A2 at the input stage as a buffer, at the same time, getting sufficient gain and the gain is controlled by the RG here, so you don’t need to have a complicated gain control here, you just can control the RG value to change the differential gain significantly. And typically the A3 is using the unity gain amplifier with the same resistance in R3 and R4, and then the gain would be 1 + R5 + R6 which are divided by RG over here. As I said, you can control the RG to control the differential gain of the over path, multiplied by R4, divided by R3 which is typically a unity gain. So now the pros are that you have a high input impedance, unlike in the 1 amp case, of a high input impedance because of this buffer amplifier. And the gain control is very easy because you only have to control the RG value. Well what are the down sides? Again you are using the passives here; you’re relying on passives which result in the limited CMRR because of the matching. And since you’re having 3 op pm, separate opms, your cost is a problem as well compared to the 1 amp case, and also the noise.

24. Common Mode Rejection Ratio (1) Okay, so what about CMRR? One thing that I would like to stress here which is all about basics, but just as a brain refresher, I’m talking about this slide. That you have a multi-stage amplifier, let’s assume you have an input over here, the first stage gives you A1 gain, and the output of the first stage is Vo1 which is fed into A2, I mean the second stage with the gain A2, which eventually gets the output of Vout. Now in this case, I’ve split the input component into two components which is differential input and the common mode input which will be suppressed by the CMRR, will be first stage. So the output stage will be A1, I mean multiplied by Vin and Vin can be as I said, divided into two components. With this in mind, if you put this into second stage, what you’re getting is, you have A1 multiplied by A2, which is multiplying the differential component of the input. And the A1 multiplied by A2 is divided by CMRR of the first stage, plus the input gain of the second stage which divides the CMRR2 and that is multiplied by the common mode component of the input. Now the CMRR as a definition is the differential gain divided by the common mode gain, so in this case the CMRR of the amplifier would be CMRR over the first stage, plus the 1 over A1 multiplying by the CMRR2. This is why this implies that the first stage CMRR really dominates the overall signal of the amplifier, that’s not the end of the story.

25. Common Mode Rejection Ratio (2) Let’s say we have an electrode offset at the input stage before the first stage of the amplifier, now if you do the CMRR math, you will find that these CMRR total overall path from the Vin

input including the mismatch all the way to the output, is 1 over CMRR of the electrode impedance offset, and if there’s any register in the path, also the register mismatch, plus the CMRR of the amp itself. Now what does this mean? This means, let’s say you have a CMRR of the amplifier, say 120dB, and you have the impedance mismatch caused by the electrode offset, which gives you around CMRR of 80dB, then even if you have a very high CMRR of this amplifier, because of these passives of the matching of the impedance of the electrode, you’re losing the overall CMRR of the system. So this means that the use of off-chip devices is not attractive in terms of bio potential amplifiers because typically the off-chip devices have worse matching than the on-chip devices. This is an important thing to remember before moving forward.

26. Dynamic Offset Cancellation (DOC) Okay, and what about the offset? Can we cancel it by applying some constant offset voltage? Let’s say you have sampled the offset of 4mV, can we just apply that at the input and forget about it? Well I hope that life was as easy as that, but the problem is, that’s not the only offset component you have. You also have the dynamic offset which is 1/f noise which cannot be cancelled out with any offset given in the DC side, DC offset at the input. So this is a must in a wearable sensor interface circuit, the dynamic offset cancellation. To mitigate the in-band or physiological signal noise, and when I say in-band, it’s starting from ground DC, I mean slightly above DC, up to let’s say 1 kHz, or even if it’s EEG or ECG, around 200Hz, and to minimize the static and dynamic offset. This is dynamic offset cancellation. And the first thing is the auto-zeroing that you can think of which gives you the sampling of the offset and then subtract it. So this is naturally in discrete time domain, and issues with that will be kT/C noise and the noise elevation. Well we’re going to see briefly about what that is. And the second choice you have is the chopping and this is to modulate the offset and filter it out, we have to. It is very similar to FM modulation. And it’s inherently continuous time domain and issues are there like for your offset, as you heard this morning, the chopping-induced DC offset and as well as harmonics are there. So we’ll cover that briefly from the coming slides.

27. Auto-Zeroing Okay, let’s look at the auto-zeroing and I’ll show three slides. If you see the ideal amplifier here, in the sampling phase, you disconnect the input into your amplifier from the signal source, and you just connect the feedback which shorts the output to the sampling capacitor which is denoded at Caz and S1 and S2 are closed, and then now, Vout is equal to the V offset value, and then it is stored at auto-zeroing, and the amplifying phase, now you disconnect the S1 and also the S2. Now the amplifier really works as an amplifier. Then as the S3 is closed, now the Vin is amplified and you are expecting because you have sampled the offset in a previous phase and you’re subtracting it from the negative input here, you’re expecting that all these sampled offsets

in the previous stage, will be subtracted from the input and consequently, you’re removing offset. But there are some practical problems involved here. The first thing is the input-referred residual offset because of the finite gain of the ideal lamp here. If you see the previous slide, the gain over here is actually not in unity but it’s A divided by A+1. So that 1 over A+1 component is left as a residual and that causes the gain error, and also the charge injection is a problem with these switches over here, which I’ll briefly discuss.

28. Auto-Zeroing in a Nutshell So that was the basic concept of auto-zeroing, but let’s look at the auto-zeroing in a more acrysense; as I said, it’s about discrete time domain operation, and the concept is to sample the offset and subtract it from the source. So if you see this as a sample and hold operation, it’s a gate function in time domain, meaning that when you sample it in an offset, this path over here, sample that whole path, is enabled and disabled automatically, so it’s a gate function, which means if you see in the frequency domain, that’s a sinc function. Obviously you have some harmonics in the higher frequency range, but sinc function can be seen as a low-pass filter in characteristics and also as you see that sin function component is subtracted from its source. So that’s 1-H(f) all of the sinc function, which is eventually a high-pass filter. So noting that 1/f noise lies in the low frequency range and you’re subtracting it and you’re passing through it, the high-pass filter; that means you’re effectively suppressing the low frequency component. And that’s why the offset and the 1/f are reduced. However, if you see this in a more electrical sense or conceptually, you’re assuming that the sampled offset value remains the same by the time you amplify. But let’s say that if the noise is not bandwidth limited, it goes to infinite, so the high frequency noise component will be different by the time you subtract it from the input in the amplification phase. So this is why I’ve written here that the limited bandwidth, due to the limited bandwidth, the thermal noise will be left and fold back into the baseband by the time you subtract it. Also, the problem is the KT/C noise which I’ll not cover here. But one good news is that this is applicable to single-ended system inherently because this is very good for sampling and then subtracting from the first phase such as image sensors.

29. Chopping (6): Time Domain Well because of this noise fold over, auto-zeroing is when compared to chopping, is not as attractive. So let’s look at the basic of chopping and how it works. I believe that most of you already know how this works, but let’s go through it again, just as a brain refresher. So we have the input component, the signal component is the blue line over here, and the aggressor is denoted as a red dotted line. So if you modulate it, so this is ground as one single-ended but actually this is a differential signal, so if you swap the signal, plus and minus with the chopping clock, then what you’ll see after the modulator is alternating inputs like this as the blue.

Now on top of it, the amplifier’s 1/f noise, and all sort of dynamic offset will be amplified so after your amplification, your blue lines shows the amplified signal component and the red dotted line shows again, the amplified version of the noise and the offsets. Now if you pass that through the demodulator just as I said in the fm case, frequency modulation case, now the signal component is back into baseband, and one other component is twice the chopping frequency, yet the offset value, I mean the offset component will be modulated, now it’s residing the chopping clock frequency. So if you filter it out with a proper low-pass filter, now you have the continuous signal back to the amplified version of the signal component with suppressed version of the noise and offset.

30. Chopping (6): Frequency Domain Well in the time domain, it’s not easy to understand, so let’s look at the frequency domain. You have the input here, the signal component is denoted as a grey line over here, I mean grey shaded area, and after you modulate it, you will see that the signal component shows up, is modulated into the chopping clock, just as in fm, of course you have some harmonics there, and this red dotted line, as in the previous slide, is DC offset and noise which will be after demodulation, will go to the chopping clock, but good news is now you have the signal component back to the baseband. I didn’t draw it here but of course in high frequency, there’s the harmonics of the signal component. But if you filter out with the proper low-pass filter, then you’re left with a nice signal amplifier version, and successfully suppressed in noise in residual offsets. So that’s the key concept of the chopper modulation.

31. Non-Idealities Well in practical sense, you have some non-idealities including the residual offset. It’s something similar resulting noise power source is similar what you’re doing, but it’s the key source of this is different, so we’ll also cover noise source to see where non idealities are coming from.

32. Practical Issues The practical issue of chopping is due to the bandwidth and gain limitation of the chopper amplifier here, where this chopper switch is. So if you do the modulation like this, this is the voltage of the modulated signal, because of the limited bandwidth of the chopper switches, you will always have some tail as you can see in this slide. Ideally you want a perfect one line over here, but because of the limited bandwidth, you have some tails, components, and then if you modulate and demodulate it, as you can see on every clock edge, positive and negative edge, you will have this signal residual showing up at the same switch, twice the amount that you see in the clock frequency spikes in the demodulated signal.

So this is after low-pass filtering, you see as a residual error term in the DC so it will be added to your demodulated baseband signal. And the higher the chopping block frequency, consequently you’ll have more chopping spikes, that’s why it will elevate more as a residual offset after you demodulate it.

33. Chopping (6): Time Domain So ideally speaking, if you go to the previous slide over here, In order to lose the specification for the low-pass filter, you want to have as much difference from the chopping clock to the baseband signal bandwidth as possible. Otherwise you’ll have to have a very sharp low-pass filter.

34. Practical Issues But as I said because of the non idealities, primarily due to the chopping spikes, there is a clear tradeoff in between the chopping clock frequency that you can choose.

35. Residual Offset So if you go a little bit deeper into residual offset, there is also charge injection clock feed through just as in the auto-zeroing case, where the residual offset of the chopping spike in the residual offset after the low-pass filter, may go up to 10s of microvolts. So this is a problem. As I said, the higher the chopping clock frequency that you use, the more residual offset you’ll get. So this is what is denoted as two times the chopper clock, multiplied by the Vspike, multiplied by the τ, the time constant of the residual that you’re getting.

36. Reducing the Residual Offset (1) Now, so how do you reduce that? Well there’re some techniques, one way of doing it is to delay sampling or time controlled demodulation. The key is that if you see the preceding spike patterns over here, if you can demodulate with a slightly delayed clock, then the resulting demodulated in the spikes will have positive and negative components, which will cancel out hopefully. Well it sounds great, but the problem is in order to do this timing control, you need a very tricky logic to detect these spikes delay in how much amount do we have to delay, is very difficult to choose. Of course, also the input spikes, you’re assuming it will be the same all the time but due to the varying capacitance in this path, may not be the same all the time, so that’s another issue here.

37. Reducing the Residual Offset (2) The second way of doing it is nested chopping. So the key concept here, is if you have the modulating spikes like this, if you can add one other chopper that surrounds the red main

chopper in a way that you cancel out, meaning in a time domain, in a long term sense, if you can cancel out the positive spikes and negative spikes, that will cancel out the spikes average out each other, then you’ll get theoretically almost zero offset and that’s the concept of the nested chopping. And with the proper choice of the lower chopper and the main chopper, then you can get around 200nV of residual offset, of course with the reduced bandwidth because of the nested chopper at the output, I mean the lower chopper. So you’re losing the bandwidth, but you’re getting performance in residual offset.

38. Summary: Offset Cancellation Okay, so let’s summarize the dynamic offset cancellation for the readout circuits, especially for the wearable environment, So auto-zeroing concept is to sample the offset, and then subtract it from the input, the next phase, issues are kT/C noise and also noise elevation due to the limited bandwidth, strength is that it is good for sampled system. This is an adherently sampled system so you can match better for samples than a single-ended system, whereas chopper modulation is more for continuous time and its concept is to modulate the offset to the higher frequency and then filter it out. Issues with it will be chopping-induced DC offset as I mentioned, but the strength is better when compared to the auto-zeroing you have better noise performance than the auto-zeroing counterpart.

39. Outline Okay so we have seen some basics about readout circuits, now let’s move on to the circuit topologies for wearable environment. We have seen similar slides in the previous speaker’s but let’s go over it to get some more ideas out of it.

40. Gain Element Comparison And before going to it, let’s compare the gain element which you can largely say capacitive versus resistive. I’m sorry in the handout, you don’t have these red characters, please put it in. So if you compare the capacitive versus resistive element, gain element, typically the epsilon has less mismatch than the resistive role, and also the resistive as you know, typically use the serpentine structure, where in capacitive, you use the area, both limit between W and L large, so the better the matching in terms W is better in capacitance, and also the oxide versus xj, you have better matching for the capacitive. So in terms of purely matching purposes, you prefer using on-chip capacitors rather than the resistors. But you have to also keep in mind, that both are very area consuming.

41. Resistive Gain Element(9)

The first topology which is very similar to the 3-amp, opm structure that we have seen, is something we already saw from Farit’s slide with the resistive gain element, using the current mirror to copy the current from the first stage to the second stage. Now as you can observe here, you have the opm at the input stage as a unity gain buffer, the advantage obviously is you have a large input impedance so it’s a very large Zin, which is good news for the bio potential amplifiers. But the down side is that you have the delimited DC headroom, and the CMRR is limited because of the passive matching, and there’s no, Farit used a term, compensated, so there’s no compensation for that, so you are prone to 1/f noise as well as the thermal noise.

42. Capacitive Gain Element The second amplifier is the capacitor-coupled instrumentation amplifier, which we’ve already seen, and this is a very popular structure by the way, you’ll see many, many amplifiers, the core amplifiers are based on this structure. You have the capacitive, as I said, it has better matching than the resistive, and you have a gain defined by Cin divided by the feedback capacitor over here which gives you a very precise gain, and inherently because you have the large capacitance at the input, you block the DC, so you can have rail-to-rail input without any problems. And also, there’s no high current path or chopper before this input capacitance, which means you’ll have a large Zin. But the problem with this is structure will be the CMRR which is limited, again because of the passive matching and if you recall the slide when I mentioned the passive matching versus the CMRR, that may kill all of your CMRR, in the overall path. So the CMRR of this overall path will be bound by the feedback capacitance mismatch, in capacitive mismatch, and the parasitic capacitor which I didn’t draw here, but it’s over here. The three mismatches are all combined and if you see the noise as Farit has already presented, you’ll have this parasitic capacitance as well as the feedback capacitor component which will elevate the noise of the OTA.

43. Limitation on Passive Matching Okay, so we have seen some passives and limited CMRR due to the passive matching. So there’s a fundamental limit due to the process variation, so is there any way to work around with it? That’s why we saw the chopper modulation in the previous slides. To mitigate the mismatch-induced offset and dynamic offset at the same time, you can apply the chopper modulation. Well it’s applicable for both capacitive and resistive gain elements, and that is what you’re going to see from the coming slides.

44. Chopper-Stabilized CCIA (CS-CCIA) This structure proposed by Tim Denison in 2006, in ISSCC, uses the classical Harrison amplifier that we saw using capacitive gain elements so if we move the chopper, each capacitive gain element instrumentation amplifier, but before, prior to this input capacitance which I said that

passive matching is a problem, you have the chopper modulation, so now the mismatch of this input capacitors or any mismatches in passive will be modulated, then filtered away by the time you demodulate. So this gives you a very good CMRR, consequently you are getting around 100dB CMRR which is very good and the noise performance is much better because you are removing the 1/f noise, I’ll say not removing but mitigating, the 1/f noise. And since you are using the capacitor matching, you have a well-defined gain and high pass corner also defined. And here, your resistance over here is implemented by the pseudo register and also the capacitor gain amplifier that you saw on the previous slide, is using. But there also some down sides here, so this amplifier was primarily for implantable neural environment, where you don’t have to care about high input impedance of the amplifier because in the wearable environment as I said, the skin electrode impedance, really goes high, as high as 1 MΩ. Then the limited impedance of this amplifier may not be appropriate. So this is primarily due to the chopper residing right before the input AC coupling capacitance. So there’s a high current path, you can use a differential path which limits the input impedance which is bounded by that. And also the electrode DC offset headroom is limited by the capacitive ratio between the DC input and the Chp in this path over here which has a DC servo loop, so this only has the headroom of 15mV. I wouldn’t say that this is a problem for an implantable case, but in terms of wearables, whereas I said, the electrode DC offset may go up to 200, 300mV, this is a problem.

45. Chopper-Stabilized If you see the measurement result, as I said, using the capacitive gain is defined by capacitive ratio where it’s very well defined, very clean. CMRR you can achieve with chopper stabilization, it’s gets around 100dB, very good. And also the noise, over 100Hz integrated is preferable input, is below 1µV RMS, which is very good. And you want a rough corner due to the mitigation of chopper stabilization is pushed down to 1 Hz.

46. CS-Res. IA Now the second type is combining the registered gain element with a chopper and as you can see, it uses the chopper stabilization again, but this time the gain element is resistive, so the gain is defined by R2 divided by R1, and you also have the offset reduction. The chopper has the offset as I said, the chopper induced offset that would be reduced by the offset reduction loop, as well as the DC offset reduction with the DC servo loop. In this case, it’s in the current domain which we’re going to discuss in the coming slides as well. Here with this help with chopper stabilization, again you’re getting very good CMRR, 120dB and since you’re getting a well matched resistance, you’ll get a well-defined gain, and input impedance is as high as 100 MΩ, very good, and also the low noise performance is very good 60nV/Hz.

I’ll say if you’re thinking about using this wearable, the only problem that I can see is the limited DC headroom by current-based DC servo-loop which gives you around +-50mV. As I said again, in the wearable environment, the DC offset may get up to range of 200 or 300mV.

47. CS-Res. IA(14) If you see the measurement for this, again the gain is defined, very clean, the noise floor is around 60nV/Hz as I said, and the 1/f noise in the lower case range would be around 1Hz which is very good as well. So as we compare to the uncompensated case, you can clearly see that chopper modulation really, raises the noise level down.

48. Improving Zin in CS-CCIA So the capacitive chopper modulation that you saw in the first case, the problem as I mentioned was the low input impedance of the amplifier. So in order to improve input impedance of such capacitive gain element chopper stabilized amplifier, this structure was firstly introduced in 2009 where you have the chopper modulation at the virtual ground low impedance node, this seems like a very simple idea, but it’s very powerful. So now you have, you don’t have any low impedance node high chopping path, between these two inputs, the first thing you see from the input is the capacitor where you have a large impedance. High impedance is possible, it goes up to around 700MΩ by chopping, simple chopping at the virtual ground, and this is possible. And of course the 1/f is also mitigated, the noise performance is very good, around 130nV/Hz, and IA offset is also compensated. If you notice this as well, this also based on the capacitive instrumentation amplifier.

49. Improving Zin in CS-CCIA(15) Now the problem with this structure below, is now as you can see, the chopper is after the input capacitance, well the reason was to improve the input impedance, but because of this, now the mismatch of these two capacitors which are offset, I mean off-chip, will be limiting, dominating this CMRR performance of the overall path that I mentioned before. And because of that now, the CMRR is limited to 60dB. So there’s a clear tradeoff between the CMRR and the input impedance.

50. Improving Zin in CS-CCIA(2) In order to mitigate, is there any way to mitigate or solve this problem? The answer is yes; this impedance boosting loop was proposed, afterwards. So the basic concept is to provide current from the output, sample it and then provide partially, that gives you positive feedback to the input, meaning that if you’re getting some same signal at the capacitor input over here, near 1 plate of capacitance, if you’re getting some current, it’s assisted from the output, then the effective current flowing through this input node will be smaller.

Consequently, this impedance is reflected as a larger impedance, input impedance. Now this concept is widely used in many of the instrumentation amplifiers to aid the chopper induced lower impedance of the amplifier.

51. Dealing with Chopper-Induced Ripples More so, I mentioned that the chopper modulation, you need to have demodulation chopper and then filter away with the low-pass filter. Sometimes these low-pass filters in many, many of the cases, this low-pass filters are limited by the area. You can’t have, you don’t have the luxury of embedding a very high-order low-pass filter. So one way of doing it with a limited area is to have the continuous time reduction loop. The idea is to sample the ripple that, this over here, is denoted the ripple, and then converting into current domain, chop it, so now that you have the IDC component of the ripples, after you chop it, and then with the integrator, you make the voltage version of that ripple component. So now you have the ripple component which is converted into DC value which will cancel out if you give a negative feedback to the input. So by doing so, you can effectively remove or mitigate the low-pass filter requirement at the output of the demodulated chopper demodulator. So you can reduce the area of high-order filters, you can just use a small-order filter, or we can even sometimes remove it as well.

52. Ripple Reduction Measurement If you see the ripple reduction measurement, you can clearly see that the demodulator with this ripple reduction loop, this ripple component is suppressed fairly well in this measurement.

53. AC-Coupling by DC-Servo Loop (DSL) Well one thing that I will have to also mention here is that there are two types of DC servo-loops. The first thing is the DC servo-loop which as I mentioned is a DSL current domain, which removes the electrode DC offset, and you’re relying on the Gm of DSL loop to cancel out the offset, and this tradeoff with the power of DC offset, the current. So if you follow this topology, you have a less area consumption, but the offset ability is limited by the current consumed by the DC offset loop and you have the elevation of noise, because the DC servo loop, and this is the amount you’re getting additionally. Whereas if you do the DC servo loop in voltage domain, meaning that the difference is that you’re feeding it over here, now you’re trading off with the area of the DC servo loop capacitor here, which is missing, and we don’t have it in the current domain. So by adding this DC servo loop capacitor, you can cancel out the electrode DC offset with the amount of capacitor you are embedding here, yet you’re elevating noise significantly with the DC servo loop capacitor. We’ll see in the coming slides too.

54. CS-CCIA(18)

One other structure that was proposed, is to have the DC servo loop, ripple reduction loop, and the impedance loop, all at once to achieve a good CMRR, this is for wearable environment by the way, and with the well-defined gain, and even the high input impedance at the same time. Now what is missing here at the DC servo loop, this one, doesn’t have the one that I’m mentioning here, this does not have the chopper here, is if you see carefully,

55. Low Noise DC Servo Loop The EC DC servo loop is completely out of chopper, meaning, after you get the output over here, you sample it and a modulated version is added at the input. So now you cannot remove any noise induced by this integrator and that really induces noise elevation because of the chopper itself, and this is highly dependent on how much capacitor you have in DSL loop.

56. Low Noise DC Servo Loop(19) So in order to mitigate this issue, you can also add a chopper explicitly over this OTA in the DSL loop. Here if you recall, the DC servo loop is added primarily to remove the DC component, so the bandwidth is not as large as the signal component itself. So the chopper modulation clock frequency doesn’t have to be that high and the main chopper here is 4 kHz, now you can add only about 500 Hz chopper because as I said, the higher the chopper frequency you use, the more chopper induced residual offset you will get and they will really kill the advantage you’re getting from the DSL here.

57. Noise RTI of CS-CCIA(19) If you see the noise measurement, with the aid of the DC servo loop chopper, you can get the less than 1µV rms, over 100Hz range.

58. Noise Efficiency Factor Comparison And also compared to noise efficiency factor which is a similar slide that you have seen earlier today, gives you the noise RTI versus the supply current, and the NEF which is noise efficiency factor, plotted overlaid on this graph, you can see these similar performances of these amplifiers in the reference list.

59. Summary of IA Topologies Let me summarize the IA topologies; you have either capacitive gain elements, or resistive gain elements, if you use the resistive gain elements, you typically have high input impedance with the limited DC headroom, and you also have some noise problems. And capacitive gain elements, you have rail-to-rail DC headroom with high input impedance, but again with the limited CMRR and noise problem, these two gain elements I’m talking about, with the uncompensated version without chopper modulation.

So in order to overcome these issues, we can have the dynamic offset cancellation, which you can use the chopper stabilized techniques to improve the noise performance. You cannot completely remove the noise problem because the chopper itself, as I said, induces some secondary effects, but it can effectively mitigate the issue. And the limited input impedance can be mitigated by having the positive feedback loop that moves to the input impedance. And also or by the chopping at virtual ground, you can effectively increase the input impedance of the chopper stabilized amplifiers too. And also the combination of continuous time ripple reduction loop, DC servo loop, and impedance boosting loop, is also possible.

60. System Level Consideration Now let’s move on to the wearable sensor system design with the example of the seizure detection system. Now I would also like to address one issue here. As a system level consideration when you’re designing the readout circuit, one important factor that we should not forget is that the end users do not care if the interface circuit has the state-of-the-art performance or not, what they care, what really matters is a good user experience. Once you have this integrated into the patch sensor or the device or monitor or whatever you have, what the end user cares about is, do I have no need to care about the batteries during operation for example. I don’t have to care about the source of power, and the pervasiveness, less irritation, minimal cumbersome wires, is what they care about. So our ultimate goal here is to satisfy the end user needs but not to just compete for the lowest power consumption or energy consumption. Or lowest noise level, or highest CMRR, etc. So if these specs are required to satisfy the user needs, then obviously you have to really fight for it, but you have to first think about what your ultimate needs are. So this is what I’m saying, interface circuit should also consider this system level target.

61. Seizure and Epilepsy Let’s look at an example of seizure and epilepsy, how to deal with it with a patch sensor. Pravalence of seizure, sorry not epilepsy, seizure is around two million in the U.S. which is quite a lot, at least two million people in the U.S. are experiencing a seizure at least once in their lifetime. And it is higher in developing countries and children, because they’re not controlled properly. The problem with the current seizure detection, seizure tracking method, is amazing mainly by interviewing the patients, the clinicist sits together with the patient and asks, how many seizures have you had during the last two or three weeks? And based on the answer, you physician describes a medication and slowly increases the dose of medication because the overdose would have the bad side effects.

Or you also have the in-hospital EEG monitoring that you saw from Tim’s slide, or obviously this is not the ultimate solution because even if you have the in-hospital EEG monitoring you can’t guarantee that the seizure will happen during that period. So continuous monitoring of abnormal activity of EEG is very, very important.

62. Difficulty in Detecting Seizure via EEG Now can’t we just do it? The problem is person-to-person and age-to-age variation in seizure is really serious. So what I’m saying is a seizure pattern for patient A, has almost nothing to do with patient B. What is perfectly normal pattern for patient A, can be seizure pattern for patient B. So you need to have machine learning to detect the proper person-to-person variations. And also the natural limit of surface EEG there including the eye fluttering, muscle contractions, and motion artifacts, and also the high dynamic range and low power operation is consequently required. And non-physiologic noise, swaying electrodes, AC coupling, you have to deal as well as the high skin electrode impedance, in case of dry electrode for long term monitoring, and electrode mismatch that we had discussed in the previous slide, is something that we have to deal with. It can be mitigated by the high CMRR, and low noise analog front-end.

63. Motivation: Seizure Detection System So what’s the problem here? Well one of the problems with the existing solution is that you can have seizure classification with high detection rate but with high latency at the same time or you have the low latency in detecting seizure, but with a lot of false positives, most are problematic. So here we have to distinguish two factors, when you’re seeing seizure detecting, it’s either onset detection or event detection. So when you say event detection that means you are focusing more on the detection rate and you don’t care too much about the detection latency, so this something that you have already in EEG data in your hand and then you want to run quickly to detect highest possible detection rate, that’s the event detection. And onset detection on the contrary, is used to detect seizure not necessarily with the highest possible detection rate, but with the minimal detection latency. Why is onset detection important? Because many of the seizure patients actually have electrical onset of seizures prior to clinical onset in case of epilepsy, for example. So if you can detect with the minimal latency less than two seconds for example, you can combine with the stimulation circuit that Tim has presented. And then hopefully you can suppress seizure beforehand. This is why onset detection is also very meaningful. And what we’re trying to implement here is to have on seizure onset detection circuitry that detects the onset of seizure and then records that chunk of ECG data is case of onset detected. So here the goal is to have high detection rate of over 95%. If you concentrate on detection rate only, you can get 98% detection rate for example. But in that case, you’ll have lower longer

latency. But here I’m saying, 95% or plus is goal for detection rate, yet having small latency of less than two seconds and low false positive is also very important.

64. EEG SoC Architecture So the architecture shown here achieved that. You have the full integrated EEG SoC, and when I say full integrated, you have the analog front-end detector classification processor, and a recording engine that records in case of seizure onset. And it has the machine learning for patient specifics for your detection, so let’s see how design premiers were drawn from this spec.

65. SoC Architecture So if you see the architecture of this SoC, you have the analog front-end 8-channel, which is then fed to the feature extraction engine, and then classification engine which is nonlinear which sparks in linear real time. Now the biggest noticeable thing is that in detection mode you only operate, expand 30 Hz bandwidth and then when the seizure is detected, then you transfer the recording engine which records the full 100 Hz bandwidth for the clinical review. This lessens the manner at front-end filter specification.

66. Seizure Detection Algorithm Linear SVM Okay, so what is the detection algorithm? This is with the help with Dr. Ali Shaw, then Mass General Hospital, before moving on, I have to mention this. If you are detecting seizure, a lot of people think if you to do the FFT, and I have this signal power, you can maybe have this stereotypical seizure pattern which is not true unfortunately, if you see the CHBMIT database which has the real seizure patient data of the EEG, some patients, many, many, patients like common belief, will have a seizure with a high amplitude and significant portion of energy in the seizure cases, whereas some patients are the exact opposite. The normal pattern they have for strong energy in the signal bandwidth but when the seizure happens, all of a sudden this high-energy component goes away. So if you just detect seizure based on FFT, chances are very low that you will detect in general, seizures in all cases. So this is the difficulty of detecting seizures using fixed algorithms. The way we do it is you split the 30 Hz into seven bands, so bands off 4 Hz each, and then you not only accumulate the FFT value, I mean the signal component in the frequency domain, but you also analyze and accumulate two seconds of data and then you calculate the signal power. And then you also detect the spacial variation along the channels. And these three factors should be considered at the same time; otherwise your detection rate will not be high in a real case. And having the linear SVM means that you have, after these feature vectors are recuperated using these three different factors, that 1, 2 second sample of data, is corresponding to one spot or one small point over here. So if you can have the feature space divided by one boundary over here, then from that point anything that goes over this side will be seizure, or in the other side will be determined as

nonseizure, this the core of the SVM. The beauty is that you can control the boundary depending on the patient you have, you can control it. But with the linear SVM, meaning that linear classification that you can see, the problem is that you have high false positive rates around 14.5% on average. Detection rate was moderate, around 87%, but the real problem is with the false positive rate.

67. Seizure Detection Algorithm Non Linear SVM Now if you apply a nonlinear SVM on the other hand, you can have a nonlinear boundary over here, to have the seizure detection rate as high as 98% on average it’s 95.1%, and a false positive, best and worst of 1.81% on average,, this is based on the CHBMIT data base which contains 21 patients worth of EEG including nonseizure and seizure datas. One thing that I have to emphasize here, is when you are using this database, you have to careful because some people tend to use the training sets, many, many, training sets, and using the same training set to detect seizure. That’s pattern recognition, that’s not machine learning. And the target of our application, as I said, is that you have a very limited number of training sets and with such limited training sets; can you detect a future oncoming seizure? That is the case. So maximum in case of nonlinear SVM for example, with a two seconds mapping into one feature vector, the maximum SVM you can get is around 50, if not 20, 40, 30, which corresponds to ten seconds, or 20 seconds of seizure onset. If you’re seeing people training with one thousand feature vectors or like two thousand, that means that in a real case, you will barely have such feature vectors or vectors in practice.

68. Analog Front-End Requirement Analog front-end has some requirements because we have seen the similar structures in the previous slides so I’ll skim through it quickly.

We have designed each channel to consume less than 3µW and low noise operation of less than 1µW, I mean microvolt RMS, and offset cancellation loop cancels the IA offset as we’ve seen before. And also incorporated the DC servo loop to have an AC coupling to get rid of DC offset up to 200mV, and impedance boosting loop is also assisted. And ASPU, meaning analog signal processing unit is also incorporated to give a programmable gain, at the same time, change the bandwidth from detection mode of 30 Hz to recording model of 100 Hz.

69. OTA Core of CS-CCIA(18) So this is the core of the operation transconductance amplifier. You have the main amplification path with this folded cascode and a current buffer over here, and this integrator over here, capacitance gives you the feedback as a trans impedance amplifier conversion to the voltage and also the compensation.

70. OTA Core of CS-CCIA Now ripple reduction loop is added with the offset cancellation, the loop over here is similar to what we saw in the previous slides. What it does is it samples the ripple from the output conversion to the current version and then you chop it and then integrate into voltage, corresponding voltage, DC voltage, then you add it and feed it back to the input stage over here. Now, by doing so, you will elevate the thermal noise unfortunately.

71. Continuous-Time CS-CCIA The amount of that will be without this offset cancellation loop, this is the amount of noise you’re getting, I’m talking about the thermal noise here, and by adding this loop, you’re getting some more elevated noise caused by the offset cancellation loop.

72. OTA Core of CS-CCIA And in order to minimize it, by sizing the GM1, much, much higher than the offset calculation loop to GM, then you can minimize that noise level of elevation.

73. Continuous-Time CS-CCIA And with the help of offset cancellation loop, as I mentioned, you can lose the specification for the low-pass filter and then no chopping spike filter or low-pass filter is required, so this safes you a lot of area. And DC servo loop will also remove the electrode offset and the previous slide you have seen, that the amount of DC servo loop capacitor will determine how much offset you can remove, and in our design, it’s about 200mV. And adding the pseudo MOS, I mean pseudo PMOS register, pseudo register will have sufficiently large time constant which will give you high capacitor filter characteristic of around 0.1 less than 0.5 Hz corner. And by having this DSL as I said, because this is completely out of chopper loop, will give you more additional noise elevation, and that as we have seen, by adding a chopper around this DSL integrator, you can get rid of it. Impedance boosting loop is also included.

74. Gain-Bandwidth of CS-CCIA And this is the measurement of the DC servo loop when it’s activated; you can see that around 15dB suppression is happening at the DC level. So it suppresses the DC, and if you see the corner frequency with the help of pseudo resistance, the cutoff frequency is around 70 mHz which is way lower than 0.5 Hz of target. And once the offset cancellation loop is activated, the 4 kHz chopper at the frequency, you can see the suppression of the ripples. I mean 4 kHz gives you some aggression of 6 dB, right, the spike here is the measurement error, the actual amount of suppression is around 6 dB.

75. Noise RTI of CS-CCIA I was talking about the noise level elevation due to the DSL, DC servo loop and this is what you’re seeing. So by activating the DC servo loop, you can actually see the noise level elevation of around 11%.

76. Analog Signal Processing Unit Okay, so let’s move on to the almost end of slides. The analog signal processing unit is also added as I said to control the gain, as well as the bandwidth for the recording mode, you’re activating 30Hz for efficiency, I mean for the detecting mode, and for the recording mode, you’re activating 100 Hz. In order to that you have to correlate double sampling based, this is indiscrete time mode, and this will enhance to elevate some noise but as we have seen, most of the noise performance is determined in the first stage where we have this low noise amplifier’s design, it’s not a big problem. But one thing that is noticeable is that you are sampling the output of amplitude of the samples and if you start saturating, it gives feedback to the gain controller which will decrease the gain. And each sample at the output of this SAR ADC, does have that information gain, both the gain and bandwidth information so you can reconstruct this signal afterwards. What is stored into the SRAM, on-chip SRAM, and has the gain and bandwidth information for each sample.

77. Analog Signal Processing Unit That’s what you’re seeing in systematic gain and bandwidth adaptation. It’s divided into five bands, the output of the ADC, and then depending on the sample where it lies, it changes the gain in real time and then gives feedback to the analog signal processing unit.

78. Configurable ASPU Measurement* So this is the measurement for the ASPU or the signal processing unit with a variable gain. This is the bandwidth in the detection mode of 30 Hz that I mentioned, it’s well defined, and also the bandwidth is changed between 30 Hz and 100 Hz.

79. SoC Verification and Measurement (18,19) Now this SoC, we have implemented, should be also verified in a systematic way. The processor itself can be verified with the MIT-CHB EEG database that we have seen in the previous slides, which has 24 patients, 906 hours of EEG containing seizure patterns primarily from children’s groups. Detection accuracy with the processor only, we unloaded the data with the interface in the processor, using nonlinear SVM; detection rate was around 95.1%.

And SoC is also trained to detect rapid eye blinks, so when I say rapid eye blinks, some epileptic seizure patients accompany the rapid eye blink patterns, not all, some of them and to replicate such cases, we have trained the SoC with very specific eye blinking patterns and then try to detect that afterwards and combine and mix up with their normal pattern. For example, for very specific blink patterns within five seconds over ten times, versus, can we differentiate that with nine blinks instead of ten? And this is such scenarios that we can use for SoC detection. And electrodes are placed in Fp1, F3, Fp2, and two channels were activated, and latency as intended, is less than two seconds and detection accuracy on average in this case was 96.0%. And what’s more noticeable compared to the linear SVM is that the false positive is now less than 1% or equivalent to 0.52 events per day.

80. Performance Comparison (AFE) These are AFE performance comparisons for the analog front-end of the implemented circuit. There are some metrics here that you can refer to when you’re designing the readout circuit, such as CMRR, noise RTI, electrode DC offset removal performance, noise efficiency factor, and also in this case, the area is something noticeable. What I would ask you to take from this slide is not that this is the best circuit, that’s not going to happen, that’s not the case, but for very specific wearable environment, I’ve shown you how to design this specification for the front-end, also for the processor, and then you can use proper techniques or proper topology to achieve that goal. Obviously if your goal is to implement the implantable readout circuit, this is not required, you’re using too much power and this is taking maybe too much area.

81. Performance Comparison (DBE) For the processor, supply voltage is different, you’re using 1V, and the back-end area is 5.4mm in 0.18 micron, and DC accuracy is around average, 95%, and the false alarm is less than 0.52 per day, and energy efficiency and on-chip SRAM is also noted here.

82. Summary Okay let me summarize today’s talk here. Wearable sensor for proactive healthcare is required for the everyday life and for chronic disease management. And in order to do so, we have energy efficiency convenience, safety and reliability all considered at once. And you can use dry electrodes for such purposes of monitoring over two weeks or extended period of time for continuous health monitoring purposes. And when you’re designing the interface circuits, you should also consider the system level specifications and needs. And do not forget what your ultimate goal is. And tradeoff between the specs is obviously required, depending on your application, that’s the same message that Tim and Farit were giving.

And challenges to tackle in wearable sensor interface circuit, I summarized the high electrode impedance which requires the high input impedance, as well as the electrode induced DC offset and noise which can be mitigated by high CMRR of the amplifier and offset cancellation loop. But do not forget that even if you have designed a high CMRR amplifier, the moment you’re using the off-chip device, you’re killing the overall CMRR of the system. The limited power and area is also something that for specific applications, you need to consider, in this case, the dynamic offset cancellation and continuous time ripple reduction will mitigate these issues. Thank you very much.