Field-Programmable Logic and its Applications

Chania, September 5 – September 7, 2011

Zhe Feng1, Naifeng Jing2, GengSheng Chen3, Yu Hu4, and Lei He1

1. Electrical Engineering Department, University of California, Los Angeles 2. School of Microelectronics, Shanghai Jiao Tong University3. State Key Lab of Application Specific Circuits and Systems, Fudan University, Shanghai, China 4. Electrical and Computer Engineering Department, University of Alberta

Email: feng07@ucla.edu; lhe@ee.ucla.edu

IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-based FPGAs

SRAM-based Field Programmable Gate Arrays (FPGAs) are vulnerable to Single Event Upsets (SEUs). We show that a large portion (40%-60% for the circuits in our experiments) of the total used LUT configuration bits are don’t care bits, and propose to decide the logic values of don’t care bits such that Soft Error Rate (SER) is reduced. Our approaches are efficient and do not change LUT level placement and routing. Therefore, they are suitable for design closure. For the ten largest combinational MCNC benchmark circuits mapped for 6-LUTs, our approaches obtain 20% chip level Mean Time To Failure (MTTF) improvements, compared to the baseline mapped by Berkeley ABC mapper, which is 3× more improvements compared to the existing best in-place IPD algorithm.

IntroductionSingle Event Upset (SEU)

Source− neutrons coming from cosmic rays

− alpha particles emitting from trace impurities in packaging materials, solder bumps, etc.

Impact– Change the states of SRAM cells.

– Change the logic function and routing.

p+

p-

n-

p+ n+ n+

+-+

-+-+

-Sensitive Area

VDD VSS0 1alpha+

I

V

R

V=IR

Figure thanks to Joseph Fabula et al. Xilinx

1 1

Not effected by the SEU!

Observability Don’t-cares

with a=1&b=1

Logic Masking

SEUs are created equally but not propagated equally.

Assigning Satisfiability Don’t Care (SDC) bit to a different value does not change logic function, placement and routing, but it may reduce SER.

2-LUTB

00 001 010 111 0

2-LUTC

00 001 010 011 1

2-LUTA

00 001 010 011 1

a

b

c

d

f

2-LUTB

00 001 010 111 0

2-LUTC

00 001 010 011 1

2-LUTD

00 001 110 111 1

2-LUTA

00 001 010 011 1

a

b

c

d

f

f = ab + ac + bcd + acd

2-LUTD

00 001 110 111 0

Failure rate = 0.2031 Failure rate = 0.1875

=

SDC

On average, 50.8% LUT bits are don’t cares when MCNC benchmark circuits are mapped to 6-input LUTs

LUT-Level Chip-levelABC IPF ABC IPF

alu4 0.34 0.24 0.36 0.28apex2 0.27 0.24 0.25 0.23apex4 1.55 0.96 1.64 1.39

des 1.79 1.69 4.16 3.63ex1010 1.21 1.13 1.62 1.43exp5p 0.7 0.67 0.93 0.88misex3 0.54 0.38 0.58 0.38

pdc 1.05 0.9 1.75 1.38seq 0.66 0.52 0.73 0.59spla 1.28 1.09 2.02 1.66

Failure Rate Ratio 1.00 0.83 1.00 0.83MTTF Improvement 1.00 1.20 1.00 1.20

Our approach decides states of SDC bits in all LUTs to increase the likelihood of masking soft errors in the their fanin cones thereby to improve the reliability of the circuit.

High-level circuit description

Logic synthesis

Logic optimization

IPF

Bitstream

Physical synthesis

In-Place Re-synthesis Flow

Motivation X-Filling Algorithm

Satisfiability Don’t Care Ratio Experiment Results

Obtain 20% chip level MTTF improvements, compared to the baseline mapped by Berkeley ABC mapper, which is 3x more improvements when compared to the existing best in-place IPD algorithm.