I/O Interfacing

• A lot of handshaking is required between the CPU and most I/O devices.

• All I/O devices operate asynchronously with respect to the CPU. The events that determine when an input device has data available or when an output device needs data are independent of the CPU.

Three I/O strategies

• Must be capable of data rates fast enough to keep up with the demands of the device, but must not be allowed to transfer data faster than the device can process it.

» Polled waiting loops» Interrupt-driven I/O» Direct memory Access (DMA)

Synchronization

• The CPU must have some way of checking the status of the device and waiting until it is ready to transfer

Transfer Rate

• A measure of the number of bytes per second transferred between the CPU and an external device.

• Maximum transfer rate – a measure of the bandwidth capability of a particular method of doing I/O.

Comparison of transfer rates

• Polled waiting loops provide data rates that are a bit slower, but still quite reasonable.

• Interrupt-driven I/O requires overhead of saving and restoring the machine state (significantly degrades data rates unless more than one byte can be transferred per interrupt.

• DMA has fastest transfer rates (additional hardward complexity needed.

Latency

• Measure of the delay from the instant that the device is ready until the time the first data byte is transferred. Latency is equivalent to the “response time”

Comparison of Latency

• Polled Waiting Loops – latency can be very high (the computer may not even be checking the device for new data when it arrives).

• Interrupt-driven I/O – dramatically lower than polled, but still imposes a software overhead.

• DMA – very low (lower than the others)

Polled Waiting I/O

• Use software to test the status of a device,before transferring each data byte.

• Continuously checking the peripheral’s BUSY/READY flag

• Ties up the CPU – no other tasks can be performed.

Interrupt-Driven I/O• There are different types of interrupts

– Hardware• Generated by the 8259 PIC – signals the CPU to suspend execution of

the current program and process the interrupt (keyboard, serial port)• Occasionally, programs must disable hardware interrupts when

performing sensitive operations on segment registers and the stack. Use CLI (Clear Interrupt flag) to disable interrupts and STI (Set interrupt flag) to enable interrupts.

– Software • Not really an interrupt (INT)

– Internal Interrupts• Divide by zero• Traps

Responding to Interrupts

Normal Processing

Interrupt Occurs

Finish Current Instruction

Normal Processing Resumes

Push flags, CS, and IP (EIP) onto stack

Pop flags, CS, and IP(EIP) from stack

Branch to ISR

Execute ISR

Hardware Interrupt Pins

• NMI – non-maskable interrupt – it cannot be blocked (the CPU must respond) – reserved for critical system functions.

• INTR – maskable via the IF flag.