investigation of the electrical...

FINAL REPORT OF THE WORK DONE ON

UGC MAJOR RESEARCH PROJECT

ENTITLED

INVESTIGATION OF THE ELECTRICAL

PROPERTIES OF DOPED/UNDOPED ZnO

BASED THIN FILM TRANSISTORS WITH

DIFFERENT GATE DIELECTRICS

UGC Reference No. F. No. 42-794/2013 (SR): Dated 22/03/2013

Period of Report: From 01-04-2013 to 31-03-2017

Submitted by

Dr. Paragjyoti Gogoi

Assistant Professor

Department of Physics

Sibsagar College, Joysagar-785665, Assam

CONTENTS

Page No.

Executive Summary of the Project Report i

CHAPTER-1

INTRODUCTION

1.1 What is thin film transistors (TFT) 1

1.2 Applications of TFTs 2

1.3 Method of Preparation of TFTs 2

1.3.1 Vacuum evaporation method 2

1.3.1.1 SPD procedure 3

1.3.1.2 MPD procedure 3

1.3.2 Sputtering method 4

1.3.3 Chemical method 4

1.4 Evaporation Sources 5

1.5 Fabrication of Thin film transistors (TFTs) 5

1.5.1 TFT structure 5

1.5.1.1 Staggered electrode structure 6

1.5.1.2 Coplanar electrode structure 7

1.6 Material analysis for TFTs 7

1.7 Physical process in the TFT 8

1.7.1 Surface states, surface charges and space

charges 12

1.7.2 Polycrystalline semiconductor 13

1.7.3 Effect of source-drain contacts 14

1.7.4 Borkan and Weimer’s theory 14

1.8 Brief review of the works on TFTs 18

CHAPTER-2

OBJECTIVE OF THE WORK AND

MATERIALS AND METHOD

2.1 Significance of the study 24

2.2 Objectives of the project 25

2.3 Materials and method 26

2.3.1 Preparation of evaporation mask 26

2.3.2 Fabrication of Thin Film Transistors 28

2.3.2.1 The vacuum unit (brief description) 28

2.3.2.2 Cleaning of vacuum unit 29

2.3.2.3 Preparation of substrates 30

2.3.2.4 Heating of substrates 31

2.3.2.5 Evaporation of metal, insulator and

semiconductor 31

2.3.2.6 Method of fabrication of TFTs 32

2.3.2.7 Characterization of fabricated films 35

2.3.2.8 Annealing of TFTs 35

2.3.2.9 Film thickness measurement 36

2.3.2.10 Tolansky method (Multiple beam interference

method 36

2.3.2.10.1 Experimental arrangement of

Tolansky method 36

2.3.2.10.2 Film thickness (d) 38

2.4 Experimental arrangement for electrical measurement 38

2.4.1 Circuits for measurement of TFT characteristics 38

2.4.2 Gate capacitance measurement 39

2.5 Stability investigation 39

2.6 Apparatus/machines used 40

CHAPTER-3

ELECTRICAL PROPERTIES OF THERMALLY

DEPOSITED ZnO TFTs AT HIGH VACUUM

3.1 Introduction to the semiconductor ‘ZnO 41

3.2 Introduction to Neodymium oxide (Nd2O3) 42

3.3 Introduction to Lanthanum oxide (La2O3) 43

3.4 Introduction to Aluminium oxide (Al2O3) 43

3.5 Experimental details 44

3.5.1 Fabrication of ZnO-Nd2O3, ZnO - La2O3

and ZnO - Al2O3TFTs 44

3.5.2 Study of the I-V characteristics of the

fabricated TFTs. 45

3.6 Results and discussions 45

3.6.1 I-V characteristics 45

3.6.2 Electrical parameters 46

3.7 Stability of the devices 50

CHAPTER-4

FABRICATION OF ZnO-Al2O3 and THIN FILM TRANSISTORS

USING CHEMICAL BATH DEPOSITION (CBD) TECHNIQUE

4.1 Introduction 51


4.2.1 Preparation of ZnO thin film using CBD method 53

4.2.2 Fabrication of TFTs. 54


CHAPTER-5

FABRICATION OF ZnO TFTs BY CBD TECHNIQUE

WITH HIGH-K La2O3 GATE DIELECTRIC

5.1 Introduction 61



CHAPTER-6

SOL-GEL DERIVED DIP COATED

ZnO – La2O3 THIN FILM TRANSISTORS

6.1 Introduction 71



CHAPTER-7

SUMMARY AND CONCLUSION 80

REFERENCES 83

Paper published

Paper presented in Seminar/Conference

***************

EXICUIVE SUMMERY

OF THE PROJECT REPORT

Title: Investigation of the electrical properties of doped/undoped ZnO based thin film transistors with different gate dielectrics

The project work has been done according to the original plan of work and

following the objectives of the project and applying the methodology that mention

in the project proposal. The detail report of the work done is presented in seven

chapters. A brief discussion of the chapters are presented below-

Chapter 1 presents the general introduction of thin film transistors. This

chapter describes briefly about the various applications of TFT’s, various TFT

structures and their deposition techniques, material analysis for TFTs and the

physical processes involved in the TFTs. Also one important theoretical models that

describe the physical process involved in the TFTs and on the basis of which, some

the finding of the present investigations would be interpreted is introduced briefly in

this chapter. Furthermore, a brief review of the works on TFTs is presented in this

chapter.

Chapter 2 describes the materials and methodology of the investigations

made in this work. This chapter explains the preparation of different evaporation

masks, fabrication of TFTs, annealing of the TFTs and the film thickness and gate

capacitance measurement. This chapter also describes the cleaning of vacuum unit,

preparation of substrates, heating of substrates and evaporation process of metal,

insulator and semiconductor. Moreover, the measurement of current-voltage

characteristics, experimental arrangement and the various apparatus used in this

investigation are introduced in this chapter.

Chapter-3 contains the fabrication and characterization of TFTs by thermal

evaporation technique with ZnO as active material and Nd2O3, La2O3 and Al2O3 as

gate insulators. All the TFTs are fabricated in coplanar electrode structure under

high vacuum of the order of 10-6 tor. The current-voltage characteristics of the TFTs

are evaluated and some important transistor parameters such as field effect mobility

(µFE), threshold voltage (VT) and sub-threshold swing are estimated using suitable

models. The field effect mobility (µFE), threshold voltage (VT), drain current on-off

ratio and sub-threshold swing of the fabricated devices for ZnO-Nd2O3 TFT are

found as 0.36 cm2/VS, 7 V, 1.1x105 and 1V/decade respectively. For ZnO -La2O3

TFTs, the field effect mobility (µFE), threshold voltage (VT), on-off ratio and sub-

threshold swing are found as 0.31 cm2/VS, 3.7 V, 105 and 1.1V/decade respectively.

For ZnO- Al2O3 TFTs, the field effect mobility (µFE), threshold voltage (VT), on-off

ratio and sub-threshold swing are found as 0.4 m2/VS, 4V, 105 and 1.2 V/decade

respectively.

Chapter-4 contains the preparation of ZnO thin film using chemical bath

deposition technique and their potential application as active material in thin film

transistors. High dielectric constant insulator Al2O3 is used as dielectric layer and

the electrical properties of the devices are evaluated. ZnO thin films are

characterized by XRD and SEM analysis. Measured values of mobility (µFE),

threshold voltage (VT), on-off ratio and sub threshold swing of the fabricated

devices are found as 0.45 cm2V-1s-1, 1.8 V, 106 and 0.6 V/decade respectively.

Chapter-5 contains the fabrication of ZnO thin films by another simple and

low cost CBD technique with high - k rare earth oxide La2O3 as gate dielectric. The

characterization of the fabricated thin films and the measurement of electrical

characteristics of the TFTs with air annealed and without air annealed ZnO samples

have been done. ZnO thin films are characterized by XRD and SEM analysis. The

measured values of electrical parameters of TFTs with air annealed sample of the

TFT are mobility (µFE) is 0.58 cm2/Vs, threshold voltage (VT) is 4V, drain current

on-off ratio is 106, sub-threshold Swing is 1V/decade and gain band-width product

is 0.04 (kHz). The electrical parameters of TFTs without annealed sample of the

TFT are mobility (µFE) is 0.024 cm2/Vs, threshold voltage (VT) is 6.6V, drain

current on-off ratio is 104, Sub-threshold Swing is 1.1V/decade and gain band-

width product is 0. 039x10-3 (kHz).

Chapter-6 contains the fabrication of ZnO- TFTs using sol-gel technique on

perfectly cleaned glass substrates with La2O3 as gate dielectric layer. ZnO thin films

are characterized by XRD and SEM analysis. Evaluations of various electrical

parameters of the TFTs are also done. Measured values of mobility (µFE), threshold

voltage (VT), on/off ratio and sub- threshold swing of the fabricated devices are 1.5

cm2V-1s-1, 2.5 V, 107 and 0.8 V/decade respectively.

Chapter-7 describe the summery and conclusion of the findings of the

project work.

The references used in the study of the project are presented after chapter -7.

***********************

CHAPTER - 1

INTRODUCTION

1.1 What is Thin Film Transistor (TFT)?

In general a thin film transistor (TFT) may be stated as a four layered solid

state device in which current conduction through a channel layer made of

semiconducting material between two electrodes source and drain (conducting

layer) is modulated by applying an external electric field across a third electrode

called gate electrode which is kept separated from the semiconductor layer by an

insulating layer. Thus a TFT is a MOSFET like device consisting of metal, insulator

(oxide) and semiconductor. All the materials are deposited over an insulating

substrate in the form of thin films.

The first TFT was fabricated by P. K. Weimer in 1962 in RCA laboratory in

Princeton, New Jersey, where he had used CdS as active material, gold as source,

drain electrodes and shallow mask for patterning [1]. Peter Brody employed TFT in

electroluminescence display in 1968 [2] and by the late 1970, Peter Brody

demonstrated the application of TFT in active matrix liquid display (AMLCD)

technology. The TFT based display technology became commercial product in

1980.

1

1.2 Applications of TFTs

The primary application of thin film transistors is as switching device in flat

panel displays (FPD) technologies. Flat panel displays are becoming increasingly

commonplaces in today’s electronic devices. Active –matrix liquid crystal displays

(AMLCD) are the leading flat panel displays technology in which thin film

transistors are used as pixel- addressing elements [3]. These displays are implanted

in portable computers, imaging and communication electronics and also in desktop

displays. Two dimensional sensor arrays are another field of TFT application [4].

Poly-Si TFTs also have been applied into some memory devices as load transistors

such as in dynamic random access memories (DRAM), static random access

memories (SRAM) [5] electrical programming read only memories (EPROM) and

more recently, deep submission logic and signal repeater application [6].

1.3 Method of preparation of TFTs

In general, an ideal thin film is stated to be a solid material bounded by two

parallel plans wherein the material is distributed uniformly and continuously. A thin

film is usually formed by condensation of material on a substrate, which is different

in chemical nature from the material whose thin film is desired. Basically two

methods are used in preparing thin films and these are (1) physical methods and (2)

chemical methods. Vacuum evaporation and sputtering etc. belongs to physical

methods. Chemical methods include chemical vapor deposition, chemical bath

deposition, sol-gel method etc.

1.3.1 Vacuum evaporation

In this process, the material to be deposited is heated in a vacuum chamber

to its gaseous state and then vapour produced is allowed to condense on a substrate.

Because of reduced pressure, the melting point of the material is sufficiently

lowered and the tendency to form oxide is reduced. The evaporated materials from

the source reach the substrate through a straight-line path, which ultimately aid in

produced good quality films. The material to be deposited may be heated either by

2

resistance heating process or electron bombardment heating process. In resistance

heating process, the material is heated to its evaporation temperature by slowly

increasing the source temperature. Flash evaporation is another resistive heating

process in which, the evaporant is grinded into its powdered formed and is allowed

to fall on a source maintained at its evaporation temperature. This technique is used

for those evaporants whose different constituents have different vapour pressure. In

electron bombardment heating process, a highly energetic beam of electron is

focused on to the evaporant surface. When oxidized films are needed, then reactive

evaporation process is used in which material is evaporated in relatively high

oxygen pressure varying from 10-3 torr to 10-2 torr where by the film get oxidized.

In vacuum evaporation techniques, the following two procedures are used to

obtain more than one deposition. These are (1) single pump down procedure (SPD)

and (2) multiple pump down procedure (MPD).

1.3.1.1 SPD procedure

In SPD procedure step-by-step deposition of different material can be done

without breaking the vacuum i.e. in one pump down of the vacuum system. In SPD

procedure, the substrate can be transferred from one mask to another by means of

levers operated from outside of the vacuum chamber. The positioning and

uncovering of different evaporation sources containing different materials to be

deposited are also operated from the outside. Films deposited by SPD procedure are

therefore free from ambient atmospheric contaminants and device fabricated by this

procedure show high quality and good performance.

1.3.1.2 MPD procedure

In MPD procedure, vacuum is broken after each deposition step or in

between some deposition steps. Though more time is required to fabricate a device

by MPD procedure, the main advantage of this procedure is that, devices could be

produce in bulk. Since one deposition is done at a time, a large mask or one array of

identical mask covering the entire dimension of the chamber could be used. Thus a

3

number of devices can be fabricated at a time. The disadvantage of this procedure is

that each layer is exposed to the ambient atmosphere prior to deposition of the next

layer, and due to which devices are not free from harmful contaminations that may

be responsible for built-in mechanism.

1.3.2 Sputtering method

In this method of deposition of thin films, the material to be deposited is

bombarded by highly accelerated ion and the ejected atoms of the material are

allowed to condense on the substrate. The highly energetic particles used to

bombard the material are generated in a cathode of DC glow discharge at 3-5 kV

and in the presence of 20-100 mili torr of Argon. Non-porous and high quality film

can be deposited by sputtering process. This technique is more frequently employed

for the deposition of refractory metal films like tantalum and niobium. A wide

variety of material including oxides, nitrides and carbides can also be deposited by

sputtering.

1.3.3 Chemical method

Chemical method is also a widely used method of thin film deposition.

Basically chemical method can be classified into two classes. Chemical Vapour

Deposition (CVD) technique and Chemical Bath Deposition technique (CBD), Sol

Gel Method etc. In CVD technique, film deposition takes place on a surface

composed of the same or different material, by means of a chemical reaction from

the gas phase at the surface, the substrate temperature is kept higher than the

surroundings such that a heterogeneous reaction takes place. In CBD technique, thin

films are grown on substrates by immerging them in a chemical solution of suitable

molar concentration prepared to get the required material. In sol gel method a gel

type solution is prepared and thin films are prepared by dipping the substrate into it

or by spin coating method.

4

1.4 Evaporation sources

In vacuum evaporation process, a source is required for evaporation of the

material where it is kept. The evaporation sources supply thermal energy to the

evaporants. The sources should have high melting point and low vapour pressure.

Depending upon the requirement of heat of vaporization for the evaporants,

different sources such as helical filament, basket and boat are used. These are

usually made up of refractory metals or certain non-metallic materials like nitrides,

oxides etc.

The metallic evaporant sources consist of either metal foil or metal wire.

Tungsten, tantalum and molybdenum are commonly used metal foils, which are

usually designed into open boats of various shapes. Dispenser is an arrangement

used to flash evaporation in which powdered evaporants is allowed to fall slowly on

a very hot tungsten strip from a vibrating dispenser and thus it gets evaporated

immediately. Non-metallic crucibles having high thermal conductivity are also used

as evaporation sources. These crucibles are heated by radiation from a refractory

metal filaments wound around them. Drumheller is another kind of evaporation

sources used for the evaporants that scatter during degassing. These evaporation

sources can achieve temperature ranges from 1000oC to 3000oC. Temperature up to

3000oC can be achieved in electron-beam heating technique. In this process a

stream of electrons, accelerated up to 10 kV is focused on the surface of the

evaporants and causes the evaporation of the material.

1.5 Fabrication of thin film transistors (TFTs)

1.5.1 TFT structure

TFTs are fabricated by consecutive deposition of the gate, drain and source,

the gate insulator and the semiconductor channel material. Basically TFT’s

structures are classified as staggered electrode structure and coplanar electrode

structure as follows.

5

1.5.1.1 Staggered electrode structure

In staggered electrode structure, the drain and the source are situated on one

side of the semiconductor and the gate electrode is placed on the opposite side. Two

types of structures are obtained in this class, which are shown in figures 1.1 (a) and

1.1 (b). In the structure of figure 1.1 (a), the metal source-drain (s-d) electrodes are

deposited on an insulating substrate such as glass. A very narrow gap is kept

between the s-d electrodes for the channel length. Then the semiconductor film is

deposited over this gap to make a conducting channel. Over the semiconductor

layer, an insulator film is grown for passivation of the semiconductor surface.

Finally over this insulator layer, a metal gate is deposited. The structure shown in

figure 1.1 (b) is the inverted staggered electrode structure in which the above steps

of deposition are exactly inverted.

a b

Figure 1.1(a): Staggered electrode structure of the TFT

(b): Inverted Staggered electrode structure of the TFT

Legend

Insulator

Semiconductor

Substrate

Contact metal

6

1.5.1.2 Coplanar electrode structure

In coplanar electrode structure, the three electrodes are on the same side of

the semiconductor. Figure 1.2 shows the structure of coplanar electrode structure of

TFT. In figure 1.2, starting at the substrate, the sequence of depositions are

semiconductor layer, the source-drain electrodes, the insulator film and finally the

gate electrode.

Figure 1.2: Coplanar electrode structure of the TFT

Figure 1.2: Coplanar electrode structure of the TFT

1.6 Material analysis for TFTs

For fabricating TFTs metal, semiconductor and insulator materials are

respectively fabricated as the electrodes, the active material and dielectric material.

Commonly used metals, as electrodes are aluminium, indium, chromium, silver,

copper and gold. These metals are so selected that, metal-insulator and metal-

semiconductor contacts become ohmic which is an important requirement for good

performance of the TFTs. The semiconductor used as active material in TFTs,

should have high carrier mobility and low carrier concentration. The semiconductor

film deposited in normal vacuum contain several defects. In some semiconductors,

these defects can be eliminated by post evaporation heat treatment or by deposition

on a heated substrate. Till date, several semiconductors such as InAs, GaAs, CdS,

7

CdSe, InSb, PbSe, Te, Si, In2O3, PbS, ZnO etc. have been tested as active material

and a few organic semiconductors such as pentacene have been tested. Among

these, PbTe, CdS, CdSe, Si, ZnO shows better performance as active material. Up

till now, several insulators have been used as dielectric materials in TFTs. Usually

the insulators used in TFTs should have high dielectric constant, low loss, high

resistivity and low optical absorption. The insulator film should have large number

of traps or the film should be stoichiometric and the metal insulator contact desired

to be ohmic for which the surface states are low. The suitable insulator materials are

inorganic compounds such as SiO, SiO2, Al2O3, Nd2O3, Dy2O3, Eu2O3, La2O3,

Yd2O3, Pb2O3, Ag2O3, MgO, LiF, CaF2 etc.

1.7 Physical processes in TFTs

The physical process involved in a TFT can be understood by studying

metal- insulator-semiconductor (MIS) structure [7]. Space charge region can be

created at the semiconductor surface by the presence of localized charges at the

surface or by an external electric field. The energy band diagram for n-type and p-

type semiconductor materials are shown in figure 1.3 (a), (b), (c), (d), (e) and (f).

When energy bands at the surface of an n-type semiconductor are bent down, an

accumulation layer is formed at the surface having a higher conduction than the

bulk of the semiconductor, which is shown in figure 1.3(a). If the bands are bent up

at the surface as shown in figure 1.3 (b), a depletion layer is formed having lower

conductance than the bulk. If the bands are bent up still more [figure 1.3 (c)] to such

an extent that conduction by carriers of opposite polarity starts, an inversion layer is

said to exist. Similar behavior could be obtained in case of p-type material [figure

1.3 (d), (e), (f)]. In TFTs, both of the accumulation and depletion layers are formed,

but inversion layer of n-type and p-type devices have not been reported.

8

S – Semiconductor I – Insulator M – Metal

E C

E F

E I

E V + + + +

- - - - -

S I M

E F

V > 0

n - ty p e

(a)

E C

E F

E I

E V

- - - - -

+ + + + +

E F

V < 0

p - ty p e

S I M

(d)

E C

E F

E I

+ + + +

E V

E F

V < 0

S I M

- - - - -

(b)

E C

E F

E I

E V

E F

V > 0

- - - - -

+ + + +

S I M

(e)

Figure 1.3. Energy band diagram for MIS structure for n-type and p-type semiconductor (a) accumulation, (b) depletion & (c) inversion layer for n-type and (d, e, f) for p-type semiconductor

S I M

E C

E F

E I

E V

E F

V > 0

- - - - -

+ + + +

(f) (c)

E F

E I

E V

E F

V < 0

S I M

- - - - -

+ + + +

9

S – Semiconductor I – Insulator M – Metal

EC

EF

EV

EF

S I M

(a) VG = 0

EC

EF

EV

EF

S I M

(b) VG = 0

EC

EF

EV EF

S I M

(c) VG = +Ve

EC

EF

EV

EF

S I M

(d) VG = -Ve

Figure 1.4.Effect of surface states on the energy bands at the semiconductor – insulator interface (a, c) acceptor – like surface states, enhancement type TFT (b, d) donor – like surface states, depletion type TFT

10

The nature of the surface states present in the semiconductor-insulator

interface affects the shape of the bands. Contact potential difference due to the work

function of the metal gate may also play a part. Existence of a high density of

acceptor like states or deep traps bends the band up and a depletion layer is formed

on the surface. A positive gate voltage is required to convert the depletion layer into

an accumulation layer and gives rise to a strong enhancement unit. On the other

hand a high density of donor like states at the interface provides an accumulation

layer at zero gate bias. Hence to pinch off this current, a negative gate bias is

required and the unit is called depletion type unit [1]. The band diagram for both

types of TFTs at zero gate bias and pinch off gate voltage (V0) are shown in figure

1.4.

Weimer had discussed the conduction mechanism in the TFTs. [8]. Figure

1.5 shows the rise of potential along the channel from source to drain in a depletion

type TFT. In region I near the source, the channel potential is less than the gate

potential, and here the enhancement of the channel conductance occurs. In region II,

enhancement is no longer possible and the built-in channel is progressively pinched

off. In region III, near the drain, where the channel potential exceeds (Vg – Vo), i.e.

Vd>> (Vg – Vo), the channel is completely pinched off, but current flow is

maintained by the high field and the injection of majority carriers into this space

from region II. Current flow in the region I and II is ohmic while that in region III,

it is emission limited i.e. space charge limited. Conduction mechanism in

enhancement type unit may be discussed in a similar manner.

In practical TFTs, existence of trapping centers in the semiconductor and the

insulator films due to the built-in defects, the surface states at the interface, in

diffusion of air contaminants and the source-drain electrode contacts play

significant role in determining the electrical properties. In polycrystalline

semiconductor film, the grain boundaries also provide potential barrier to the charge

carriers. It would be useful to have a discussion on the various influencing factors

11

that affects the device performance. The various factors that influences the device

performance are discussed below-

1.7.1 Surface states, surface charges and space charges

Shockley had predicted theoretically that the existences of large density of

energy levels are introduced by the presence of many states and charges at the S-I

interface [9]. Thus surface states and charges in the structure usually affect the MIS

characteristics [7]. These states are classified as surface states, interface states, fixed

surface states, mobile ions and ionized traps. Allen and Gobeli have estimated the

density of surface states in the case of atomically cleaned Si samples and reported

the density of surface atoms of the order of 1014 cm-2 [10].

The surface states are further divided into the types (i) fast states and

(ii) slow states. The first type exchange charges with the C.B. or V.B. in a short

time and assumed to lie close to the S-I interface, whereas the latter type requires

longer time for exchange of charges and are believe to lie at the interface of air and

insulator. Very large density of surface states can make it impossible to control the

Semiconductor Gate Insulator Accumulation layer

Source Drain I II III

Channel potential O V (x) = Vg V (x) = Vg - Vo Vd ≥ Vg - Vo

Insulating substrate

Figure 1.5.Cross-sectional drawing of a TFT showing the semiconductor in the gap region separated into subdivisions by the field-effect action of the

insulated gate

12

current in a TFT by applying gate voltage. The density of surface states depends on

film formation, annealing condition and on semiconductor orientation. The surface

charges, which include the fixed surface charges, the mobile ions and ionized traps,

are located at or near the S-I interface. The space charges in the insulators include

the mobile ions and the ionized traps inside the insulator. The effect of surface

charges on the TFT is that, it lowers the effective bias on the TFT. Alkali ions, such

as sodium in the oxide films are mainly responsible for the instability of the oxide-

passivated devices, because they can move through the oxide film under the

influence of the gate field [11]. Therefore proper control of ion drift instability will

give useful characteristics of TFTs.

1.7.2 Polycrystalline semiconductor

A semiconductor film consists of series of conducting crystallites or grains

separated by grain boundaries [figures 1.6 (a), (b)] are said to be polycrystalline

semiconductor. Several authors [12, 13, and 14] have studied the influence of grain

boundaries on the transport properties of polycrystalline semiconducting films.

Figure 1.6. (a) Grains and grain boundaries in polycrystalline film

(b) Potential barrier in polycrystalline semiconductor

(a)

Grains Grain boundary

E B E C

E F

E V

(b)

13

At the grain boundaries, due to the trapping of charge carriers, potential barriers to

the charge carries are developed. These potential barriers impede the motion of the

charge carriers from one grain to another and thus limit the conductivity of films.

1.7.3 Effect of source-drain contacts

The source-drain contacts with the semiconductor film affect the

performance of a thin film transistor. Normal operation of a TFT requires a source

contact having low impedance for injection of majority carriers. The failure to

achieve a good ohmic contact at the source electrode decreases the

transconductance and hence in some cases, it produces crowded characteristics. A

blocking contact at the drain yields S-shaped (I-V) characteristics in the

neighborhood of the origin [1]. Ohmic contact is a not critical requirement at the

gate electrode, because the gate induces carriers to the channel by capacitor action

only.

Several theoretical models have been proposed by several investigators to

explain the physical process in TFTs. One of the important model is discussed

below.

1.7.4 Borkan and Weimer’s theory

Borkan and Weimer [1] are the first to develop a model of TFT. This

model has been developed on the basis of two simplifying assumptions.

(1) The mobility of the carriers throughout the conducting channel is a

constant independent of gate voltage over the useful operating range of the device.

(2) The gate capacitance is a constant independent of gate voltage.

Figure 1.7 shows the electrode structure of field effect analysis for a TFT.

Here h is the thickness of the semiconductor film, L is the channel length and w is

the channel width. The gate electrode is a narrow metal strip having a width equal

to the channel length L, separated from the semiconductor by an insulator of

thickness t, the potentials applied to the gate and drain electrodes relative to the

14

source electrode are Vg and Vd respectively. The potential of the semiconductor at

any point at a distance x from the source electrode is given by V(x).

The charge per unit area induced in the channel region by the application of

gate potential Vg is given by

(1.1)

where,

∆N (x) = number of electrons per square centimeter in the induced charge

q = the electronic charge.

Cg = gate capacitance across the insulator.

w=channel width and L= channel length

The total drain current Id can be expressed as

(1.2)

xdd E

h

xN

hwL

NqhwI

∆+=

)(0µ

[ ])()( xVVwL

CxNq g

g −=∆

Semiconductor

Insulator

Gate Electrode

Drain Electrode

Source Electrode

L

W

t

h

x = L x x = 0

Vd

Vg

Figure 1.7: Electrode structure used for field effect analysis of TFT

15

where, µd = effective drift mobility in cm2V-1s-1,

Ex = electric field between source and drain in Vcm-1

N0 = total number of charge initially present in the gap region of the

semiconductor. N0 is positive for a depletion-type unit and negative

for an enhancement type unit. The value of N0 is a function of the

volume density of donors and acceptors, as well as the thickness of

the semiconductor.

Combining equations (1.1) and (1.2), we have

(1.3)

which gives

(1.4)

the term qNo /Cg in equation (1.4) can be replaced by a voltage –Vo , where Vo

represent the gate voltage required for the onset of drain current. For an n-type

semiconductor, Vo is positive for an enhancement type unit and negative for a

depletion- type unit. The equation (1.4) becomes

(1.5)

Equation (1.5) is valid for 0 <Vd ≤ (Vg – V0) up to the knee of the Id versus Vd

characteristics. It has been observed that theoretically obtained curves have good

similarity with the experimental curves up to the knee portion. The expressions for

different transistor parameters such as transconductance (gm), output resistance (rd),

amplification factor (µ), gain-bandwidth product (G.Bw) and effective mobility (µb)

etc. are given below-

( ) ( )xdVxVVC

qN

L

CdxI

dV

g

g

gdL

d ∫∫

−+=⇒

0

0

0

µ

−

+=

2

20

2d

dg

g

gd

d

VVV

C

qN

L

CI

µ

−−=

2)(

2

02d

dg

gd

d

VVVV

L

CI

µ

dx

xdVxVV

C

qN

L

CI g

g

gd

d

)()(0

−+=

µ

16

The output conductivity below the knee is given by

(1.6)

The transcondutance below the knee is given by

(1.7)

or

(1.8)

In equation (1.8), the left hand side is proportional to the gain-bandwidth

product for the device, while the right hand side is equal to the reciprocal of the

carrier transit time between source and drain.

The value of the amplification factor µ can be obtained directly from the

characteristics, or from the transconductance and the output resistance as given by

the relation

(1.9)

where (1.10)

and (1.11)

The maximum drain current (at the knee) determine from equation (1.6)

(1.12)

The transconductance at or above the knee is given by

2L

VC

V

Ig

dgd

g

dm

µ=

∂∂

=

2

L

V

C

g dd

g

m µ=

dm rg=µ

constVg

dm

d

V

Ig

=∂∂

=

constVd

dd

g

I

Vr

=∂∂

=

)(2

0

ogd

Vd

dd VV

LV

IG

d

−=∂

∂=

→

µ

202(max) )(

2VV

L

CI g

gd

d −=µ

17

(1.13)

The gain-bandwidth (G.Bw) product is an important TFT parameter, which

is a figure of merit that characterizes the high frequency performance of a three

terminal active devices. The gain-bandwidth product is given by the relation

(1.14)

From equation (1.6), G.Bw below the knee is given by

(1.15)

and G.Bw at or above the knee is given by

(1.16)

This model helps in evaluating the various TFT parameters such as output

resistance (rd), transconductance (gm), amplification factor (µ), effective mobility

(µFET), gain bandwidth product (G.Bw) etc.

1.8 Brief review of the works on TFTs

Weimer fabricated the first TFT successfully and since then due to constant

research and investigations on TFTs by many investigators, performance of TFTs

improved greatly and they can be used widely in large area electronics. Some

important works done which develop the performance of TFTs since 1962 to up-till

now are mention below.

2

0 )(

L

VVCg

ggd

m

−=

µ

g

m

C

gBwG

π2. ≈

22.

L

VBwG dd

πµ

≈

2

0

2

)(.

L

VVBwG

gb

π

µ −≈

18

Weimer used Au as source-drain and gate electrodes, SiO as gate insulator

and CdS as the semiconductor. These TFTs could produce an amplification factor

(µ) greater than 100, input resistance (rd) greater than 106 ohm, transconductance

(gm) 10,000 µmho and gain-bandwidth product (G.Bw) greater than 10 MHz. The

switching speed obtained was less than 0.1 µ sec [2].

Borkan and Weimer presented a theoretical analysis of the TFTs based on

the assumption of a homogeneous conducting channel with constant carrier mobility

[1]. This model was valid up to the knee region of saturated TFT characteristics.

TFT with tellurium semiconductor shows an effective drift mobility of 200

cm2V-1s-1 and on/off current ratio up to 200 [15].

Pennebaker fabricated TFTs with PbS films and reported an effective

mobility as high as 200 cm2V-1ss-1 [16].

Brody and Kuing have fabricated a high-gain InAs thin film transistors. The

TFTs exhibits good saturation in both enhancement and depletion modes of

operation. They reported the field effect mobility of such devices as high as 1800

cm2V-1s-1, transconductance of 10,000 µ-mhos and gain-bandwidth product of 8

MHz with a 100 µm source-drain spacing [17].

O’ Henlon and Haering reported CdS TFTs that could withstand several

hundreds volts and switch current of the order of 100 µA with control voltage of the

order of 50 V [18].

InSb TFTs fabricated in coplanar–electrode structure and SiO as gate

insulator shows well defined saturated region and large transconductance (gm) [19].

Refioglu and De Massa reported a theoretical explanation of the TFTs on the

basis of exponential and uniform distribution of traps and the temperature

dependence of TFT characteristics with traps [20].

19

Anderson proposed a theoretical model for polycrystalline TFTs by taking

into account the band bending at S-I interface and the potential barriers at the grain

boundaries. He also reported that the reduction of slow and fast states densities

might be achieved with higher gap semiconductors with high quality insulator films

[21].

Van Calster fabricated a two-gated InSb – SiO TFTs having Sb electrodes

and operating at cryogenic temperature and revealed that the interface states were

located in the SiO layer [22].

Misumi et.al fabricated polycrystalline Si TFTs with Al2O3 as gate oxide.

They evaporated Si films by molecular beam deposition in ultra high frequency and

Al2O3 film by RF magnetron sputtering which yields on/off ratio of 104 [23].

A theoretical model have been proposed by Levinson et.al which explain

the conductivity in thermally grown annealed and ion implanted CdSe TFTs, which

could account for the different donor density. With the help of this theory, trap

density, critical donor density, crystallite size and mobility of TFTs with

polycrystalline semiconductor can be calculated [24].

CdS – Yb2O3 TFTs, which exhibited well, saturated characteristics had been

reported by Deka and Baishya [25, 26].

Polycrystalline Si TFTs fabricated using photochemical doping with

phosphorous from the gas phase by ultraviolet laser have been reported by Coxon

et. al [27].

Vanfleteran and Van Calster presented a photolithographic process to

describe the fabrication of the polycrystalline CdSe TFTs using four vacuum cycles

and four lift of mask. The device made have stability similar to the ones made by

the single pump down process [28].

Singh and Baishya reported the performance of CdS and CdSe TFTs using

Nd2O3 as gate insulator fabricated by thermal evaporation process using MPD

procedure [29].

20

Hatalis and Greve prepared a-Si TFTs by LPCVD method and observed its

performance as a function of deposition temperature and obtained field effect

mobility as high as 32 cm2V-1s-1for the devices built at 3600C [30]. Singh and

Baishya reported a comparative study of some TFTs with rare earth oxides as gate

insulators [31].

High performance polycrystalline Si TFTs with ECR (electron cyclotron

resonance) plasma hydrogen passivation reported by Takeshita et.al, which have n-

channel enhancement mode characteristics with a large transconductance, high

switching ratio, a threshold voltage as low as 0.4 V [32].

Yamaguchi et.al fabricated polycrystalline Si TFTs by laser crystallization

of a amorphous Si film using a liquid encapsulation technique to increase the grain

size and obtained the hole mobility of 43 cm2V-1s-1 [33].

Shimizu et.al reported poly-Si TFTs fabricated by novel excimer laser

crystallization method using dual beam irradiation which enhanced the grain size (2

µm) leading to high field effect mobility of 100 cm2V-1s-1 and 300 cm2V-1s-1 for

holes and electrons and on/off current ratio of 106 [34].

Bonnel et. al reported the fabrication of poly- Si TFTs crystallized by two

steps annealing process on glass substrates, which exhibits a field effect mobility of

35 cm2V-1s-1 and threshold voltage of 5.7 V. The TFTs measured with this two-step

annealing material exhibits better characteristics then those obtained by

conventional furnace annealing [35]. Choi et.al observed that the reduction of heat

removal rate from the molten Si layers during an excimer laser crystallization step

improved the performance of poly-Si TFT leading to a mobility of 600 cm2V-1s-1

[36].

King and Saraswat fabricated n-channel poly-Si1-x-Gex TFT and reported

their electrical characterization [37]. Si-Ge TFTs with Al2O3 as gate insulator has

been fabricated by Jin et.al. Without any hydrogen passivation, these TFTs exhibit

21

field effect mobility of 47 cm2V-1S-1, a threshold voltage of 3 V and on/off ratios

above 3 x 105 at a drain voltage of 0.1V [38].

Demitriadis and Tassis proposed an analytical model for the turn on

characteristics of poly-Si TFTs, which was based on the drift diffusion thermoionic

emission conduction mechanism and continuous distribution of traps localized at

the boundaries [39]. Maegawa et.al reported that fluorine-implanted poly-Si TFTs

shows a positive threshold voltage shift, increase the ON current and decrease the

leakage current significantly [40].

Demitriadis and Tassis developed a model for the grain boundary barrier

height of undoped poly-Si TFTs based on rod like structure of the grains with a

square cross-section and a Gausssian distribution of the trapping states [41].

The performance of TFT with ultra thin Ni –MILC (metal induced lateral

crystallized) polycrystalline silicon channel layers has been reported by Jin et.al.

These TFTs exhibit high mobility of 110 cm2V-1s-1 at drain voltage of 5V and on/off

current ratio of about 3 x 107. No deliberate hydrogenation was performed on these

devices [42].

Pangal have reported an n-channel polycrystalline silicon TFTs fabricated

using hydrogen plasma seeded crystallization process at temperature of 10000C

which exhibits a field effect mobility ~100 cm2V-1s-1 and on/off current ratio of

~107 [43].

Sarvati and Nathan developed a model for reverse characteristics of Si: H -

TFTs, and observed the static and dynamic behaviour of a Si: H TFTs [44].

Hsueh and Lee fabricated poly-silicon TFTs by copper induced lateral

crystallize process. The Cu-induced poly-Si TFT exhibits a field effect mobility of

24 cm2 V-1s-1 and a threshold voltage of 6.6 V [45]. ZnO-based n-channel,

enhancement-mood transparent TFTs with excellent drain current saturation and

drain current on/off ratio of ~107 have been reported by Hoffman et. al. The devices

22

exhibit a threshold voltage rang from ~10 to 20V and field effect mobility of ~2.5

cm2 V-1s-1 [46].

High performance polycrystalline Ge TFTs fabricated by metal induced

crystallized process on flexible plastic substrate at low temperature (1300C) has

been reported by Shahjerdi et.al, which exhibits field effect mobility of 110 cm2V-

1s-1 and on/off current ratio of 104 [47].

Transparent thin film transistors (TTFTs) with an amorphous zinc tin oxide

channel layer formed via RF magnetron sputter deposition have been reported by

Chiang et.al. They reported field effect mobility of 50 cm2V-1s-1 and current on/off

ratio greater than 107 [48].

****************

23

CHAPTER - 2

OBJECTIVE OF THE WORK AND

MATERIALS AND METHOD

This chapter contains the objective of the project and the materials and

experimental procedure used in the investigation of the proposed work. The

preparation of evaporation masks, fabrication of TFTs with thermal evaporation

process, chemical bath deposition method and sol gel method, annealing of TFTs,

the film thickness and gate capacitance measurement, preparation of substrates are

described in this chapter.

2.1 Significance of the study

The wide spread application of active matrix liquid displays technology

(AMLCD) has made thin film transistors (TFTs) one of the most common devices

employed in the large area electronics industries. Though in large area electronics

industries, TFTs are widely used, investigations are going on to enhanced the TFTs

performance in terms of mobility, stability, reliability and reproducibility. Currently

researchers trying to enhanced the TFTs performance by fabricating TFTs with new

semiconductor –insulator combination and using suitable dopant with the active

material to enhance the TFT performance. Research have been going in searching

24

new fabrication techniques which provides a cost-effective, low temperature and

large area compatible technique for the growth of high quality semiconductor

layers. With this proposed project it will try to overcome the deficiencies of TFTs

by introducing new semiconductor –insulator combination such as semiconductor

like ZnO doped with suitable dopant as active material and different dielectric

materials as gate insulator using different fabrication techniques.

2.2 Objectives of the Project

The main objectives of this proposed project are –

1. To prepare ZnO thin films using different fabrication techniques such as

thermal evaporation technique, chemical bath deposition technique and sol-

gel methods.

2. To characterize the fabricated thin films by XRD, SEM, TEM, AFM, UV-

VIS, FTIR etc.

3. To doped suitable dopant with the fabricated ZnO thin films in order to

improve the carrier mobility and other electrical parameters.

4. To study the electrical properties of the prepared doped and undoped ZnO

thin films.

5. To fabricate thin film transistors with doped and undoped ZnO films as

active material with different dielectric materials as gate insulator.

6. To measure current-voltage (I-V) characteristics and the transfer

characteristics of the TFTs.

7. To evaluate the threshold voltage, field effect mobility and other electrical

parameters of the TFTs using suitable theoretical models.

8. To perform detailed electrical characterization of the TFTs using suitable

theoretical model.

9. To investigate electrical properties of TFTs with nanocrystalline ZnO thin

films.

10. To study the stability of the TFTs.

25

2.3 MATERIALS AND METHOD

2.3.1 Preparation of evaporation mask

Various geometrical patterns of the thin films of a TFT can be evaporated on

the substrates by using suitable evaporation masks. These evaporation masks are

designed depending upon the shape of the desired films. For each deposition, the

substrates are placed on the mask in close proximity to allow deposition of the film

to the exposed substrates areas only. The material such as glass, graphite,

aluminium etc. that do not loss their planarity and dimensions on heat treatment are

generally used for masks. In the present investigation, aluminium foils of 0.03 cm

thickness are used to prepare the mechanical mask for the deposition of films. The

aluminium foils are cut to circular shape of diameter 23.5 cm so that it can be

placed properly inside the vacuum unit. The desired shape of source-drain

electrode, semiconductor, insulator and gate electrode are first drown by a fine

Figure 2.1: Evaporation mask for s-d electrodes deposition (a) aluminium foil (b) opening for film thickness measurement (c) source-drain electrodes (d) contact pads

a

b

c

d

26

Figure 2.2: Evaporation mask for semiconductor deposition (a) aluminium foil (b) opening for film thickness measurement (c) geometrical pattern for semiconductor deposition

Figure 2.3: Evaporation mask for insulator deposition (a) aluminium foil (b) opening for film thickness measurement (c) geometrical pattern for insulator deposition

a

b

c

a

b

c

27

metal tip and then various geometrical patterns are made using suitable cutting and

filing tools. Separate evaporation masks are prepared for the deposition of source-

drain electrodes, semiconductor, insulator and gate electrode. The evaporation

masks prepared for deposition of various films such as source-drain electrodes,

semiconductor, insulator and gate electrode are shown in figures 2.1, 2.2, 2.3 and

2.4 respectively.

Before placing in the vacuum chamber, the evaporation masks are cleaned

thoroughly to avoid possible contaminations. For cleaning, the masks are first

treated with Teepol and washed in water and dried by blowing hot air. Finally the

masks are cleaned by acetone and dried by blowing hot air. The masks have to be

cleaned prior to each deposition during the course of investigation.

2.3.2 Fabrication of Thin Film Transistors

2.3.2.1 The vacuum unit (brief description)

A model VC 12 Vicco High vacuum coating unit is used for fabrication of

TFTs, which is shown in figure 2.5. The whole unit consists of three main parts;

Figure 2.4: Evaporation mask for gate electrode deposition (a) aluminium foil (b) opening for film thickness measurement (c) geometrical pattern for gate electrode deposition

a

b

c

28

viz. the vacuum chamber, the pumping system and metal bell jar of 12-inch

diameter resting on a rubber gasket placed on a metal base plate. The chamber is

evacuated by using an oil diffusion pump having a suction capacity of 200

liter/minute. The rotary pump can produce a rough vacuum of 2 x 10-3 torr. The

ultimate vacuum that can be achieved by the vacuum unit is 10-6 torr, which is

measured by penning ionization gauge attached in the unit. The rough vacuum of

the chamber and the diffusion baking line is measured with the help of pirani gauge.

The base plate is fitted with seven well insulated and three earthed

electrodes. Each electrode is coupled to earthed electrodes connected to the base.

Out of these, two electrodes are used for heating the evaporation source, two for

either radiant heater or substrate heater and one for HT (High tension) discharge

cleaning; one electrode is a multipin electrode having four electrically insulated

terminals. Of these, two are used to connect the thermocouple for measurement of

substrate temperature. Besides, the base plate has provisions for fitting a movable

shutter and a multifilament tunnel. The masks can be positioned with the help of

three stands fitted on the base plate. The transformers and the corresponding

electrical circuits for sending currents at required voltages through the various

electrodes and gauges are also fitted in the compact unit. Various meters and control

knobs for performing different operations are fitted on the front panel of the

instruments.

2.3.2.2 Cleaning of the vacuum unit

Before going to deposit a film, the vacuum unit must be cleaned thoroughly

to avoid possible contaminations. In MPD method of device fabrication, the

vacuum is broken after each deposition. So, prior to the deposition of each film for

the ultimate realization of the TFTs, the vacuum unit is cleaned thoroughly. The

glass bell jar is cleaned carefully by carbon tetrachloride (CCl4) or petroleum ether.

Rubber accessories like rubber gaskets, o-rings etc. are cleaned using petroleum

ether. The steel and metal parts like electrode, base plate, substrate holder are

cleaned first by fine emery paper and then washed with acetone. Then the whole

29

unit is dried by blowing hot air. The vacuum unit is also cleaned during vacuum

annealing of the fabricated devices.

2.3.2.3 Preparation of substrates

In this investigation, optically plane glass slides (blue star PIC-2) of size 7.5

x 2.5 x 0.14 cm are used as substrate for fabrication of thin film transistors. These

glass slides are cut into suitable sizes and first treated with ‘Teepol’ and then

washed in water and kept immersed in very dilute nitric acid for about 30 minutes.

Then the slides are again washed in water and then rinsed in distilled water. The

glass slides are then taken out from distilled water and observed for a continuous

thin layer of water [49]. If the thin layer of water is not observed, the procedure is

repeated until the layer of water is continuous. The continuous layer on the glass

indicates the proper cleaning. The substrates are then dried by blowing hot air and

Figure 2.5: Picture of the (Vicco High Vacuum) vacuum coating units

30

then cleaned in an acetone bath and finally baked at 250oC in a clean electric oven

for 4-5 hours. After these, the substrates are ready for deposition. The substrate

once used is not used again.

2.3.2.4 Heating of substrates

Sometimes, the films are deposited on heated substrates to obtain better

result. For this purpose radiant heater is used. This is a flat circular heater,

approximately 19 –20 cm in diameter, made by winding nichrome wire on a mica

sheet. The two surfaces of the heater are covered with mica sheet to prevent short

circuit. The heater is placed in close proximity with the substrates and temperature

is controlled by regulating the current using a dimmerstate. The substrate

temperature is measured with the help of chromel – alumel thermocouple, the tip of

which is just touching the glass substrates. The two mica sheets covering the heater

coil are replaced from time to time with fresh sheet, because during deposition,

evaporants are found to condense over them. The heater is cleaned regularly to

make it free from dust particles and other types of contaminants.

2.3.2.5 Evaporation of metal, insulator and semiconductor

To fabricate the complete TFT, different films (metal, insulator and

semiconductor) of the TFT have to be deposited in steps by thermal evaporation of

various materials in high vacuum. In this investigation, for fabrication of the TFTs,

aluminium (Al), ZnO and oxides (Nd2O3, La2O3, Al2O3) are used as ‘source-drain

and gate’ electrodes, semiconductor material and gate insulator respectively.

To obtain the film for source-drain and gate electrode, Al is evaporated from

tungsten – helix filaments. The required quantity of Al is kept inside the helix and

covered by the shutter plate. When complete melting of Al occurs, the shutter is

removed and Al is allowed to deposit on the substrate through the mask.

For the deposition of semiconductor, both molybdenum and tungsten

baskets are used for evaporation of ZnO. Required quantity of ZnO is kept in

31

molybdenum boat and covered by the shutter. The semiconductor material is

evaporated at constant temperature by passing a constant current through the

evaporation source utilized. The semiconductor is sufficiently degassed and during

that period, a shutter covers the evaporation source and the temperature is kept

lower than the evaporation temperature. After some time, the shutter is removed and

the ZnO is kept to its evaporation temperature and allowed to deposit on the

substrates through evaporation mask. During evaporation, a substrate temperature

of required amount is maintained with the help of substrate heater.

For deposition of oxide films, the oxides are kept in the evaporation source.

For deposition of different oxides, different evaporation sources are used. In this

case tungsten baskets are used as evaporation sources. Like semiconductor, the

oxides films are also sufficiently degassed prior to the deposition and during this

period, the movable shutter covers the evaporation sources. The oxides are also

evaporated at constant source temperature and during degassing, the temperature is

kept lower than the evaporation temperature. After some time, the shutter is

removed and the oxide is kept to its evaporation temperature and it is allowed to

deposit on the substrates.

2.3.2.6 Method of fabrication of TFTs

The TFT are fabricated using mainly three processes viz. vacuum

evaporation technique, chemical bath deposition method and sol-gel technique. The

active material ZnO thin films are deposited as active material on ultrasonically

cleaned glass substrates by vacuum evaporation technique, chemical bath deposition

method and sol-gel technique but other thin films of the TFT such as source, drain

and gate electrode and dielectric layers are deposited by vacuum evaporation

technique using multiple pumps down (MPD) method.

Aluminium is deposited as source, drain and gate electrodes. Rare earth

oxides Nd2O3, La2O3, Al2O3 etc. are deposited as dielectric layer.

32

The TFTs are fabricated in coplanar electrode structure on cleaned glass

substrates. Different masks prepared from aluminium sheet are used to deposit the

various films of the TFT. A 50 micrometer channel length is produced using a wire

grill fixed on the mask.

Different steps of the fabrication of the TFTs is shown in the block diagram

(Figure 2.6). The TFTs will be fabricated in coplanar electrode structure (Figure

2.7) on ultrasonically cleaned substrates.

Figure 2.6: Block diagram of the main steps for the fabrication of the TFTs.

Firstly, ZnO is deposited using vacuum evaporation, chemical bath

deposition method and sol-gel methods on glass substrates.

Al is deposited as source-drain electrode over the ZnO layer. A wire grill

fixed on the source-drain mask defines the channel. After the deposition of source-

drain electrode layer, oxides (Nd2O3, La2O3, Al2O3 etc.) layers are deposited over

the source-drain layer to the get the dielectric layer. Finally, Al is deposited over the

oxide layer as gate electrode. All the films are kept in vacuum desiccators prior to

the deposition of subsequent layer, which reduce the possibility of air

contamination. It is necessary to keep the substrates in dry air to prevent the

deposited films from absorbing moisture and thereby prevent the formation of

oxides. Formation of oxides on the source-drain electrode may produce crowded

33

characteristics of the devices [1]. Figure 2.8 shows the plane view of the fabricated

TFT respectively. The fabricated TFTs are kept in clean desiccators contained silica

gel. Photograph of fabricated TFT is shown in figure 2.9.

Figure 2.7: Coplanar electrode structure of the TFTs

Contact pads

Insulator

Semiconductor Channel

s-d electrode

Gate electrode

Substrate

Figure 2.8: Plane view of the fabricated TFT

34

2.3.2.7 Characterization of the fabricated films

The as deposited ZnO thin films are characterized by XRD and SEM

analysis. The XRD and SEM of the samples are done in STIC of Cochin University

and Science and Technology, Kerala.

2.3.2.8 Annealing of TFTs

Polycrystalline semiconductor is composed of small crystallites

joined together by grain boundaries [21]. Due to the trapping of charge carriers at

the grain boundaries, a potential barrier exist at the grain boundaries called grain

boundary potential barrier which decreases the mobility of the charge carriers [24].

Annealing of the TFTs increases the size of the grains and hence decreases the

potential barrier. Therefore annealing of TFTs is crucial important for obtain better

performance. For this purpose, the prepared TFTs required a post deposition heat

treatment at elevated temperature.

For baking in vacuum, the TFTs are kept in a thoroughly cleaned petridishes

and placed over suitably designed metal plate fixed on the three stands of the

vacuum coating unit. A flat substrate heater, maintained at constant temperature by

Figure 2.9: Photograph of a TFT fabricated in this investigation

35

adjusting the current flow with the help of dimmerstate is placed in close proximity

with the TFTs. The temperature is measured with the help of a chromel- alumel

thermocouple.

Some TFTs are baked in a clean electric oven at elevated temperature

keeping the TFTs in thoroughly cleaned pertidishes. For air baking, the electric

oven is preset at the desired baking temperature.

2.3.2.9 Film thickness measurement

The thicknesses of the films deposited are determined with the help of

Tolansky method [50] and electrical method. These are explained bellow-

2.3.2.10 Tolansky method (Multiple beam interference method)

This method was developed by Tolansky considered as the most elegant

method for film thickness determination [50]. The thickness of the TFTs cannot be

measured directly as it is a multi-layered device. Therefore separate film is grown

on glass substrates along with the films for the TFTs. This separate film is used for

thickness measurement.

The film sample whose thickness has to be determined is coated with a

highly reflecting layer of Al. Thus a step height equal to the film thickness is

produced.

2.3.2.10.1 Experimental arrangement

Figure 2.10 shows the experimental arrangement used for thickness

measurement of the fabricated films. Divergent rays from a mercury lamp (80W)

are allowed to pass through a circular aperture, a collimating lens, and an optical

filter that transmits the strong green line (λ = 5461 Å) of mercury. A

semitransparent glass plate at an angle of 450 to the collimated beam reflects the

rays, which fall normally on the interferometer plates.

36

With a low power microscope the resulting interference patterns are

observed. Sharp well-defined fringes of equal thickness are observed by this

arrangement, which are shown in figure 2.11. Fringe width and step height are

measured with the linear and circular scales attached to the microscope base.

Mercury Lamp Collimating Lens

Optical Filter

Microscope

Interferometer Glass

Semitransparent Glass

Figure 2.10. Experimental arrangement used for thickness measurement of the fabricated films

∆L

L

Figure 2.11: Fractional discontinuity due to step formation in the fringe pattern

37

2.3.2.10.2 Film thickness (d)

In the observed fringe system, the distance of separation between the

successive bright or dark fringes is λ/2, where λ is the wavelength of the

monochromatic light used. In the present study, the monochromatic light is obtained

from a mercury lamp (λ = 5461Å). Due to the presence of steps, the fringes are

displaced by ∆L, where L is the fringe spacing. Then the ratio ∆L/L is the fractional

discontinuity of the fringe system and the film thickness ‘d’ is given by the relation

d = (∆L/L) (λ/2) (2.1)

The accuracy that obtained by this method in the experimental sample is in

the range of ±30 Å.

2.4 Experimental arrangement for electrical measurement

For electrical measurement, the TFTs are mounted carefully in a vacuum

desiccator. The electrical connections to the different electrodes are made using

connecting wires and the electrical contacts with the contact pads are made using

pressure contacts with aluminium foils on the contact pads. The electrical

connections are taken out through rubber cork. This arrangement provides easy

connections of the TFTs to the measuring circuits and protected the TFTs from air

contaminants.

2.4.1 Circuit for measurement of TFT characteristics

Figure 2.12 shows the circuit diagram for obtaining the current voltage

(I-V) characteristics of the TFTs. The potential at the gate and drain were measured

by the D.C. micro voltmeter. Drain current is measured by a digital nanoammeter.

38

Drain

Source

Gate

V

nA/µA

V

A semiconductor parameter analyser (SPA-121) also used to observe the I-V

characteristics of the devices.

2.4.2 Gate capacitance measurement

The gate capacitance of the TFTs is measured by the ‘APLAB’ Auto

computer LCR – metre (4912). For this purpose, a common terminal is taken out

from the source and drain electrode and gate electrode is taken as other terminal.

Then the total gate capacitance is taken as the capacitance across the insulator layer

[1].

2.5 Stability investigation

In order to test the stability of the fabricated TFTs, they are kept in a

vacuum desiccators charged with fused CaCl2 during the stability test. The

performance of the TFT’s are examined periodically after every one month. This is

continued for five months. This test gives the stability of the devices to restore their

characteristics properties.

Figure 2.12: Circuit diagram for TFT characteristics measurement

39

2.6 Apparatus/machines used

The various measuring apparatus that are used throughout the investigation

are mentioned below along with their technical specifications.

i) Vicco High Vacuum Coating Unit (V-12)

ii) Digital Nanoammeter

Model : DNM-121 (Scientific Equipment Roorkee)

Range : 100 nA to 100 µA

ii) Digital D.C. Micro voltmeter

Model : 412 (Systronics)

Range : 1mV to 1000 V

i) Nanoammeter

Model : NM-122 (Scientific Equipment Roorkee)

Ranges : 10 nA to 100 µA

vi) Traveling Microscope (National Instrument Corporation, Ambala Cantt.

India) Resolution: 0.001cm

vii) Digital Balance (Citizen); four digits.

viii) Semiconductor parameter analyser (SPA-121)

ix) Digital pH metre

x) Magnetic Stirrer

xi) Digital Power supply

xii) Digital furnace

xiii) Digital Oven

xiv) Digital LCR meter, etc.

**************************

40

CHAPTER - 3

ELECTRICAL PROPERTIES OF THERMALLY

DEPOSITED ZnO TFTs AT HIGH VACUUM

This chapter contains a brief introduction of ZnO (active material), Nd2O3,

La2O3, Al2O3 (gate insulators). Then the fabrication of ZnO- Nd2O3 and ZnO-

La2O3 and ZnO - Al2O3 TFTs by thermal evaporation method and measurement of

their electrical parameters and their characterization, results and discussion are

presented.

3.1 Introduction to the semiconductor ZnO

ZnO is a promising material (metal-oxide) for device electronics such as

photovoltaic devices and TFTs. ZnO has a relatively large direct band gap of

~3.3 eV at room temperature. Advantages associated with a large band gap include

higher breakdown voltages, ability to sustain large electric fields, lower electronic

noise, and high-temperature and high-power operation [51]. Most of ZnO has n-

type character, even in the absence of intentional doping . Controllable n - type

doping is easily achieved by substituting Zn with group-III elements such as Al, Ga,

In or by substituting oxygen with group-VII elements chlorine or iodine. Due to

41

these merits, in the proposed investigation, ZnO will be used as active material in

the proposed TFTs. The proposed investigation will also be carrying out using

nanocrystalline ZnO which touches the fabrication chemistry of nanoscale materials

and device electronics of recent nanotechnology.

3.2 Introduction to Neodymium Oxide (Nd2O3)

Neodymium oxide, also called Neodymia is a rare earth oxide of rare earth

element Neodymium (Nd) whose atomic number is 60. Its molecular weight is

336.48 and appearance is purple. The melting point of Neodymium oxide is

1900oC. The oxide is insoluble in water, but moderately soluble in strong mineral

acid.

The dielectric constant of Nd2O3 as 14.27 [52]. Dharmadhikari and

Goswami investigated that, the capacitance of Nd2O3 depends on both frequency

and temperature except at low temperature where it becomes constant for all

frequencies. The breakdown field strength of Nd2O3 was estimated to be more than

1.5 x 10-6 Vcm-1, while the dissipation factor was quite low (0.0045). A high

resistivity (1012-1013 ohm cm) in constant electric field at room temperature was

observed [53]. Vacuum evaporated thin film of Nd2O3 on glass substrate is

colourless and transparent.

Many investigators have successfully used Nd2O3 as dielectric material in

TFTs and capacitors since Nd2O3 shows good dielectric behaviors, for its

mechanical and chemical stabilities. Singh and Baishya and Puzari and Baishya

successfully used Nd2O3 as gate insulator in TFTs [29, 54]. A comparative study of

rare earth oxides as gate insulator revealed that TFTs with Nd2O3 as gate insulator

are superior in terms of transconductance and stability [31]

42

3.3 Introduction to Lanthanum Oxide (La2O3)

Lanthanum oxide (La2O3) also called lanthana is a rare earth oxide of rare

earth element lanthanum. Molecular weight of La2O3 is 325.82. It is white in

appearance. Melting point of La2O3 is 2315°C and boiling point is 4200°C.

Lanthanum oxide is an amorphous, odorless, white solid that is insoluble in water,

but soluble in dilute acid [55]. The average room temperature resistivity is 103 Ω

cm. Wilk et. al reported that, La2O3 has hexagonal crystal structure at low

temperature and cubic structure at high temperature and its band gap energy is 4.3

eV [56].

The dielectric constant of La2O3 is 14.77 as reported by Xue et.al [52].

Mahalingam et.al studied the dielectric properties of La2O3 thin films at various

temperatures over the frequency range of 5 kHz – 30 kHz. The capacitance of a

capacitor prepared from La2O3 film is observed to decrease with frequency and this

decrease is less pronounced towards lower temperature. The D.C. breakdown field

strength for electron beam deposited and thermally evaporated La2O3 films are 2

x106 Vcm-1 and 8.7 x 106 Vcm-1 respectively [57].

Capacitor prepared using La2O3 shows a high capacitance density

(0.5 µ cm-2), high dielectric constant, low loss, low temperature coefficient of

capacitance and high breakdown field strength for which it may be considered

for application of capacitor element in micro-electronics circuits.

3.4 Introduction to Aluminium oxide (Al2O3)

Aluminium oxide is a chemical compound of aluminium and oxygen with

the chemical formula Al2O3. It is the most commonly occurring of

several aluminium oxides, and specifically identified as aluminium (III) oxide.

It occurs naturally in its crystalline polymorphic phase α-Al2O3 as

the mineral corundum, varieties of which form the

precious gemstones ruby and sapphire. Al2O3 is significant in its use to produce

aluminium metal, as an abrasive owing to its hardness, and as a refractory material

43

owing to its high melting point. The melting point of Al2O3 is 2,072 °C. Al2O3 is

an electrical insulator but has a relatively high thermal conductivity (30 Wm−1K−1)

for a ceramic material. The dielectric constant of Al2O3 is 9.1 [51].

3.4 Experimental details

3.4.1 Fabrication of ZnO-Nd2O3 and ZnO-La2O3 and

ZnO - Al2O3TFTs

For the fabrication of the TFTs, suitably cleaned glass slides are used as

substrates in coplanar electrode structure. Firstly ZnO is deposited as active material

on these glass substrates using the method of thermal evaporation process which is

described in chapter 2. The source-drain electrodes, gate dielectric layer and the

gate electrode are deposited over the ZnO layer by multiple pumps down method

using thermal evaporation process in high vacuum. In every depositions, thoroughly

cleaned mask from aluminium foil are used to achieve the different geometrical

patterns of the films. Initial substrate cleaning and the cleaning of the unit and mask

after each deposition are achieved by the procedure described in chapter 2.

The fabricated TFTs are annealed at 5000 C for 4-5 hours in high vacuum of

the order of 10-6 torr. These are then stored in a clean desiccators charged with

fused CaCl2 to protect them from air contaminants. The thicknesses of the

fabricated films are measured by Tolansky’s method described in chapter 2. The

thicknesses of some oxides are measured by capacitive method. The dimensions of

the channel are measured by using a traveling microscope. The measured values of

thickness, channel length and channel width are presented in table 3.1.

44

3.5.2 Study of the electrical characteristics of the fabricated

TFTs

The electrical circuit for the measurement of the electrical characteristics of

the TFTs is described in chapter 2.

3.6 Results and discussions

3.6.1 I-V characteristics

The characteristics curves depicting the variation of drain current (Id) with

drain voltage (Vd) at constant gate voltage for ZnO-Nd2O3 and ZnO-La2O3 and ZnO-

Al2O3 TFTs are shown in figures 3.1, 3.2 and 3.3. The field effect characteristics of

the devices at constant drain voltage VD = 10V are shown in figure 3.4. In figure 3.4

Curve a, b and c represents ZnO-Nd2O3, ZnO-La2O3 and ZnO-Al2O3TFTs

respectively. The threshold voltages of the TFTs are evaluated from the plot of √Id

vs. Vg at constant drain voltage, which are shown in figure 3.4. The threshold

Device type ZnO-Nd2O3 ZnO-La2O3 ZnO-Al2O3

s-d length (cm)

0.005 0.005 0.005

s-d width (cm)

0.16 0.16 0.16

Thickness of the s-d electrode (Å)

850 800 800

Thickness of ZnO Film (Å)

540 500 560

Thickness of Nd2O3 Film (Å)

800 ---- -----

Thickness of La2O3 Film (Å)

---- 840 ------

Thickness of Al2O3 Film (Å)

----- ------ 900

Thickness of the gate Electrode (Å)

950 920 1000

Gate capacitance of x 10-9

(farad) 4 4.9 5

Table 3.1: Device dimension, thickness of the films and gate capacitance

45

voltages (VT) of the devices are obtained as 7 V and 3.7 V and 4V for ZnO-Nd2O3 ,

ZnO-La2O3 and ZnO-Al2O3 TFTs respectively.

The electrical parameters of the devices are calculated on the basis of

equation (3.1) [58].

2TGiFEDsat )VV(C

L2

WI −= µ (3.1)

Where W is the channel width, L is channel length, Ci is the gate capacitance per

unit area, VT is the threshold voltage and µFE is the field-effect mobility. The field-

effect mobility µFE of the devices are calculated from the slope of this plot and

found as 0.36 cm2/VS, 0.31 cm2/VS and 0.4 cm2/VS for the ZnO-Nd2O3, ZnO-

La2O3 and ZnO-Al2O3TFTs respectively.

The plots of log (ID) versus VG at a constant drain voltage (VD=10V) for the

TFTs are shown in figure 3.5. The on-off ratio of the devices are measured from

figure 3.5 and found 1.1x105, 105 and 105 respectively for ZnO-Nd2O3 and ZnO-

La2O3, ZnO-Al2O3 TFTs. The sub-threshold swing is calculated from the slope of

the graphs using the relation (3.2) [59]. For the respective TFTs ZnO-Nd2O3 , ZnO-

La2O3 and ZnO-Al2O3, the sub-threshold swings are found as 1V/decade,

1.1V/decade and 1.2V/decade respectively.

( ) 1log

−

δ

δ=

GV

DIs

(3.2)

3.5.2 Electrical parameters

The electrical parameters of the ZnO-Nd2O3, ZnO-La2O3 and ZnO-Al2O3TFTs,

such as field effect mobility (µFE), threshold voltage (VTH) and sub-threshold swing

are evaluated using equation 3.1 and 3.2 and mentioned in the table 3.2.

46

Figure 3.2: Variation of ID vs. VD at constant VG of thermally deposited ZnO-La2O3 TFT

0 2 4 6 8 10 12 14 16 18 200.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

V G

= 10V

V G

= 7V

V G

= 5V

V G

= 3V

V G

= 1V

I D (

µ A

mpere

)

V D

(Volt)

0 2 4 6 8 10 12 14 16 18 200.0

0.2

0.4

0.6

0.8

1.0

VG= 10V

VG= 7V

VG= 5V

VG= 3V

VG= 2V

I D (

µ A

mpere

)

VD (Volt)

Figure 3.1: Variation of ID vs. VD at constant VG of thermally deposited ZnO-Nd2O3 TFT

47

Figure 3.4: (ID)

1/2 vs. VG curves at constant drain voltage VD =10V the TFT

Curve a, b and c for ZnO-Nd2O3, ZnO-La2O3 and ZnO-Al2O3TFTs respectively.

Figure 3.3: Variation of ID vs. VD at constant VG of thermally deposited ZnO-Al2O3 TFT

0 2 4 6 8 10 12 14 16 180.0

0.5

1.0

1.5

2.0

2.5

VG =10V

VG =7V

VG =5V

VG =3V

VG =2V

I D (

µ A

mpere

)

VD (Volt)

-2 0 2 4 6 8 10 12 14 16 18 20

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

VD =10V

(ID)1

/2 A

mpere

VG (Volt)

c

b

a

48

The factor that is responsible for the low value of current (ID) of the devices

is the trapping of charge carriers in the grain boundaries. In polycrystalline ZnO, the

crystallite sizes of the grains are very small and the trap density is very large. Most

Device type Mobility (µb)

cm2V-1S-1

Threshold

Voltage (VT)

Drain current on-off ratio

Sub-threshold swing

ZnO-Nd2O3

0.36 cm2/VS

7 V 1.1x105

1V/decade

ZnO -La2O3 0.31 cm2/VS 3.7 V 105 1.1V/decade

ZnO-Al2O3 0.4 cm2/VS 4V 105 1.2V/decade

Figure 3.5: log ID vs. VG curves at constant drain voltage VD=10V of ZnO TFTs

Curve a, b and c for ZnO-Nd2O3, ZnO-La2O3 and ZnO-Al2O3TFTs respectively.

Table 3.2: Field effect mobility (µFE), threshold voltage (VT) and sub-threshold

swing of the fabricated devices

-2 0 2 4 6 8 10 12 14 16 18 201E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

0.01

c

b

a

VD= 10V

log

ID A

mpere

VG (Volt)

49

of the carriers available for current conduction are trapped in the trapping centers.

So the resultant carriers (after trapping) decrease which result in the low value of

the current. As the trap density increases, the grain boundary potential barriers

increase and hence the mobility decreases.

3.6 Stability of the devices

To test the stability of the TFTs, they are kept in vacuum desiccators for one

year. After each one month the I-V characteristics of the devices are observed. Form

these observations it is found that initial four months there is no variation of the I-V

characteristics occur. But after fifth month, a gradual decay of the I-V

characteristics observed. Thus we can say that the TFTs are not stable with respect

to the time. Suitable encapsulation of the devices is needed for better stability.

**************************

50

CHAPTER - 4

FABRICATION OF ZnO-Al2O3 and THIN FILM

TRANSISTORS USING CHEMICAL BATH

DEPOSITION (CBD) TECHNIQUE

This chapter discuss the preparation of ZnO thin film using chemical bath

deposition technique and potentially applied as active material in thin film

transistors. High dielectric constant insulator Al2O3 is used as dielectric layer and

the electrical properties of the devices are presented.

4.1 Introduction

Recently ZnO is recognized as a promising semiconductor material in

modern electronics devices like solar cell, LED, piezoelectric transducer, laser

diode, gas sensor , thin film transistors etc. due to the wide band gap (3.37 eV) and

high excitation binding energy (60 meV) [60]. Many investigators have used ZnO

as active material in TFT due to their high field effect mobility, high thermal and

chemical stability [61-63].The performance of TFTs is directly dependent on the

field-effect mobility. High field–effect mobility of the carrier in the channel region

increase the switching speed of the transistors and low threshold voltage reduce the

power consumptions of the TFTs. Enhanced drain current of the TFTs is required to

achieve high frame rate in high resolution displays. Increased drain current is the

51

result of high field-effect mobility and low threshold voltage. Hence the threshold

voltage needs to be lowered and the field-effect mobility of the carrier in the

channel needs to be increased. Also the semiconductor –insulator combination

plays the key role in TFT performance. Proper selection of gate dielectric and metal

electrodes (good ohmic contact) can improve the performance of TFTs [58]. Search

for suitable semiconductor –insulator combination is still going on that could

provide high mobility in the channel region.

In the recent years metal oxide semiconductors, like indium (In), gallium

(Ga), zinc (Zn) oxides etc., received much attention as strong materials for next

generation display technology due to their unique properties, such as transparency,

high electron mobility. Polycrystalline oxide semiconductor like ZnO has received

much attention as promising material for transparent thin film transistors (TTFT) in

active matrix liquid crystal displays [64-66].

Though SiO2 is a successful gate dielectric in TFTs, the operating voltage of

thermally deposited SiO2 gate insulators is high (above 20V). For portable

application the operating voltage needs to be lowered for low power consumption.

The key factor for the reduction of low operating voltage is the lowering of

threshold voltage. One of the main technical reasons to lower the threshold voltage

is to use of high dielectric constant gate dielectric [67, 68]. In this investigation we

have used Al2O3 as gate dielectric since Al2O3 is successfully used as gate dielectric

in TFTs due to its excellent dielectric constant (9-10.1), chemical, mechanical and

thermal stability [69, 70]. Also Min Suk Oh et. al. reported that the gate stability of

the TFT could be increased with the application of Al2O3 as gate insulator [71].

Various techniques are employed to synthesized and fabricate ZnO thin

film viz. CBD method, vacuum evaporation method, pulse-laser deposition

technique, spray pyrolysis, sol-gel technique etc. Among these techniques, CBD is

one of the simplest and cost effective techniques that provide a thin film of uniform

surface [72, 73]. Recently, interests have been grown to fabricate chemically

deposited ZnO thin films to use as TFT’s channel material that provide a low

temperature and large-area compatible processing technique.

52

Here we have reported the Chemical Bath Deposition of ZnO films from a

simple solution mixture of ZnCl2 and NH4 bath and their performance as active

material in TFTs. The prepared thin films are characterised by XRD and SEM

analysis. Some important electrical parameters are evaluated and presented.


4.2.1 Preparation of ZnO thin film using CBD method

ZnO thin films are deposited by CBD method on glass substrates. Glass

slides of size 7.0x2.5x0.14 cm are cleaned perfectly using distilled water, acetone

bath, nitric acid washed and ultrasonication. For the synthesize of ZnO films, ZnCl2

and NH3 of analytical grade purity without further purification are used. Aqueous

solution of ZnCl2 is used as precursor for the preparation of ZnO films as Zn2+ ion

source.

Firstly 100 ml of 0.1 M ZnCl2 solution is prepared in a beaker with

deionised water and stirred for 1 hour at room temperature. Then 40 ml of 30% NH3

aqueous solution is added to the ZnCl2 and prepare the bath. The reaction takes

place in the following ways.

Initially a little amount of ammonia solution is added to the beaker

containing ZnCl2 solution, a white precipitate of zinc hydroxide is form. The

equations for reaction are as follows-

ZnCl2 + 2NH4OH =Zn(OH)2 + 2NH4Cl (4.1)

Then after addition of more ammonia (50 ml of 30% NH3), the zinc

hydroxide precipitate dissolved to a clear colourless solution of soluble zinc amine.

The equations for the reaction are -

Zn(OH)2 + 4NH3 = [Zn(NH3)4]2+ + 2OH- (4.2)

2OH- + Zn+ = ZnO + H2O (4.3)

The clear solution is then filtered and cleaned glass slides are immerged into the

filtered solution vertically for 24 hours for deposition of the ZnO films. After 24

hours the films are kept out from the bath and washed with distilled water and dried

53

in oven. Then transparent thin films of uniform surface are obtained. The films are

then annealed in air at 5000C for one hour.

The thicknesses of the films are measured using Tolanky’s multiple mean

interference method [50].

4.2.2 Fabrication of the TFTs

The TFTs are fabricated in top gate electrode structure on perfectly cleaned

glass substrates. The source-drain and gate electrodes and the dielectric layer are

deposited by thermal deposition technique. The TFTs are fabrication using the

following deposition steps-

i) The ZnO thin films of 600 Å are deposited on the glass substrates by CBD

technique.

ii) Al source-drain electrodes are deposited over the ZnO film maintaining a

channel of length 50 µm.

iii) Al2O3 of 800 Å is deposited over the source-drain electrodes as gate

insulator.

iv) Over the insulator Al is deposited as gate electrode.

A schematic diagram of the deposition steps of the TFT is shown in figure 4.1.

Figure 4.1: Schematic structure of the top gate coplanar

electrodes structure of the TFTs

54


The thin films deposited by chemical bath deposited method are characterised by

XRD and SEM analysis. The XRD spectrum of the films (figure 4.2) shows three

distinct picks (100), (002) and (101). This confirms the preparation of ZnO film by

the CBD method and polycrystalline nature of the ZnO thin films. The SEM

micrograph is shown in figure 4.3 which shows the uniform granular structure of

the deposited films.

Figure 4.2 XRD spectrum of the ZnO thin film

The ID-VD characteristics of the fabricated devices at various gate voltages

(VG) are shown in figure 4. 4 which shows good gate modulated characteristics. The

drain current significantly increased and showed saturation behaviour from 3 volt

drain voltage. From the figure 4.4 it is seen that considerable drain current at gate

voltage Vg= 1V and complete pinched off occur at 1volt gate voltage. The devices

are operating in enhancement mode.

20 30 40 50 60 70

400

600

800

1000

1200

1400

1600

(101)

(002)

(100)

Intensity

2 θθθθ degree

55

Figure 4. 3 SEM image of the ZnO thin film annealed at 5000 C.

Figure 4.4: IV –VD characteristics of ZnO TFTs at constant VG

0 1 2 3 4 5 6 7 8 9 10 11 12 13

7x10-6

6x10-6

5x10-6

4x10-6

3x10-6

2x10-6

1x10-6

6V

5V

4V

3V

2V

VG= 1V

I D (Ampere)

VD (Volt)

56

The square root of the drain current plots for the TFTs at constant drain

voltage VD = 8V are shown in figure 4.5. The threshold voltage (VT) of the devices

is calculated from the extrapolation of the linear portion of graph to the VG axis of

plot and found to be VT = 1.8 Volt. In saturation regime VD=VG–VT, and the drain

current is given by equation (4.4) on the basis of which the electrical parameters are

extracted [58].

Figure 4. 5: √Id - VG plots for ZnO TFTs at constant drain voltage VD =8V

2

TGiFETDsat VVCL2

WI )( −= µ (4.4)



effect mobility µFE is calculated from the slope of this plot.

-2 -1 0 1 2 3 4 5 6 7

0.3

0.4

0.5

0.6

0.7

0.8

VD= 8V

(ID s

at1

/2) Ampere

VG Volt

57

Figure 4.6: Plot of log (ID) - VG at constant drain voltage VD= 8V

The transfer characteristics at a constant drain voltage (10V) are shown in

the Figure 4.6. The sub-threshold swing is calculated from the slope of this graph

using the relation (4.5) [59].

( ) 1log

−

δδ

=G

D

V

Is (4.5)

The drain current on-off ratio of the device is calculated from the relation

(4.6) [58].

( )D

TGFETi

OFF

ON

dV

VVC

I

I

σµ 2−

= (4.6)

Where σ and d are conductivity and thickness of the semiconductor of the TFTs

respectively.

-2 -1 0 1 2 3 4 5 6 7

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

0.01

s= 0.6 V/decade

log I

D Ampere

VG Volt

58

Table 4.1: Measured values of mobility (µFET), threshold voltage (VT), on-off ratio

and sub threshold swing of the fabricated devices

The extracted values of field effect mobility, threshold voltage, drain current

on-off ratio and sub-threshold swing, of the devices are found to be 0.45 cm2/Vs,

1.8 V, 106 and 0.6 V/decade respectively and presented in table 1. The threshold

voltage and sub-threshold swing of the TFT are significantly low and the mobility

and drain current on-off ratio is found to be high. As the chemically prepared ZnO

thin films are annealed at 5000 C for 1 hour, the oxygen content in the films

increases which provides good quality of ZnO films. Passivation of oxygen atoms

into the interstitial positions of the ZnO crystals at high annealing temperature

reduces the trapping of charges in the grain boundaries and thus reduces the

potential barrier at the grain boundaries. The resulting effect is that the

polycrystalline ZnO electrically progresses towards single crystal ZnO

characteristics, yielding higher mobility and on/off ratio. The high field effect

mobility and on/off ratio may also due to the low gate leakage of the Al2O3 gate

dielectric [74]. The mobility of the devices may further be increased by doping

suitable dopant as well as annealing the devices at oxygen atmosphere at high

temperature which can passivate the oxygen vacancies that create deep level in the

band gap structure [75, 76].

Parameters

(ZnO-Al2O3)

Mobility (µFET) 0.45 (cm2V-1s-1)

Threshold voltage (VT) 1.8 V

on/off ratio 106

Sub-threshold Swing 0.6 V/decade

59

TFTs with ZnO as active material with Al2O3 dielectric are successfully

fabricated by CBD and thermal evaporation technique. The TFTs exhibits high field

effect mobility, low threshold voltage, low sub threshold swing and high drain

current on/off ratio. The low threshold voltage indicates that the devices are suitable

for portable applications. From this investigation it can be also concluded that

ZnO-Al2O3 semiconductor –insulator combination for TFTs is feasible. Further,

doping effect on ZnO with different dopant is also under investigation for the

improvement of mobility and other electrical properties of the ZnO TFTs.

***********************

60

CHAPTER-5

FABRICATION OF ZnO TFTs BY CBD TECHNIQUE

WITH HIGH-K La2O3 GATE DIELECTRIC

In this chapter the fabrication of ZnO thin films by another CBD technique

has been presented with high - k rare earth oxide La2O3 as gate dielectric. The


characteristics of the TFTs are presented.

5.1 Introduction

Among the various techniques for fabrication of ZnO thin films, viz. thermal

deposition, chemical bath deposition, metal organic chemical vapour deposition

spray pyrolysis, sol gel etc. chemical bath deposition is one of the simplest and cost

effective techniques for the deposition of semiconductors and ceramic film

deposition which provides a thin film having uniform surface [72, 73]. More

generally in CBD technique, an aqueous solution made up of some mixture of

precursor solution and complexing agents and the substrates for the deposition of

the films are required.

Rare earth oxide La2O3 exhibits very high dielectric constant (14.77) [52] and

low leakage current and hence reliable as dielectric in microelectronics and recently

61

La2O3 is under intense investigation for replacing conventional SiO2 [78, 79]. Due

to the property of insensitive to the impurities and more stable owing to the absence

of grain boundaries, amorphous dielectrics are suitable for gate dielectrics. Up till

now many investigators have successfully used La2O3 as gate insulator in TFTs [62,

80, 81].

In this paper we have reported the chemical bath deposition of ZnO thin

films, their characterization and performance of ZnO thin film as active material in

TFTs. The electrical characteristics and the various parameters are evaluated using

theoretical model and presented. The CBD method used to prepare ZnO thin film is

a modification of the method used by A. P. Chatterjee et al [82].


For the preparation of ZnO thin films, firstly glass slides are cleaned

ultrasonically to use as substrates. For the deposition of ZnO on glass substrates,

sodium zincate (Na2ZnO2) bath is prepared. For the preparation of Na2ZnO2 bath,

firstly 100 ml of 0.1 M ZnCl2 aqueous solution is prepared using deionized water.

Then NaOH is added into the ZnCl2 solution to prepare (Na2ZnO2) bath. The mixer

is then stirrered by magnetic stirrer for 30 minutes. Initially a white precipitate of

zinc hydroxide (Zn(OH)2) is formed. A clear solution is obtained after addition of

60 ml of 4 M NaOH solution into the bath. The mixer is again stirrered for 30

minutes. In the entire process the bath temperature is maintained at 400C. The pH of

the solution is 11. The chemical reactions are as follows-

ZnCl2 + 2NaOH = Zn(OH)2 + 2NaCl (5.1)

Zn(OH)2+2NaOH=Na2ZnO2+2H2O (5.2)

The ZnO thin films are deposited on the substrates by alternate dipping into the

(Na2ZnO2) bath and then into hot water bath. This leads to the reaction-

Na2ZnO2 + H2O = ZnO + NaOH (5.3)

62

The zinc hydroxide is formed due to hydrolysis of deposited ZnO during

subsequent immersions in hot water [82]. The film thickness can be increased by

increasing the immersion time into the bath. In this investigation the number of

immersion is 20-25 and the immersion time is 5 seconds into the two baths for

deposition of each ZnO films. The as deposited films are then annealed at 5000C for

1 hour in air. The thicknesses of the films are measured using Tolanky’s multiple

bean interference method [50].

The TFTs are fabricated in top gated coplanar electrode structure. The

source-drain and gate electrodes and the dielectric layer are deposited by thermal

evaporation method under high vacuum of the order of 10-6 tor. The different

fabrication steps of the TFTs are as follows-

v) The ZnO thin films of 500 Å are deposited on the glass substrates by CBD

technique as mentioned above.

vi) Al source-drain electrodes are deposited over the ZnO film maintaining a

channel of length 50 µm. and channel width 0.1 cm.

vii) Grad purity rare-earth oxide La2O3 without further purification is deposited

over the source-drain electrodes as gate dielectric layer of 800 Å.

viii) Over the dielectric layer Al is deposited as gate electrode.

A schematic diagram of the fabricated TFT is shown in figure 5.1.

Figure 5.1 Schematic diagram of the coplanar electrode structure of the TFTs.

63


Figure 5.2: XRD spectrum of the ZnO thin film.

Curve a, without annealing; Curve b, annealed at 5000C in air

The polycrystalline structure and the surface morphology of the ZnO films

are investigated through XRD spectrum (figure 5.2) and SEM analysis (figure 5.3).

In figure 5.2, Curve a and b shows the XRD spectrum without annealed and

annealed at 5000C respectively. No distinct peaks are observed in case of ZnO

films without annealed (curve a). But four distinct picks (100), (002), (101) and

(110) of ZnO is observed in the XRD spectrum in case of the annealed films at

5000C in air, which confirms the preparation of ZnO thin film by CBD method

(curve b). The SEM micrograph shows a uniform granular structure of the ZnO

films. The average size of the ZnO crystallites are calculated from XRD pattern

using the Debye-Scherer’s formula (equation 5.4) as follows and found as 117 nm.

θβλ

cos

kd = (5.4)

30 40 50 60 70

b

a

(110)

(101)

(002)(100)

Intensity (a. u.)

2 theta (degrees)

64

Where λ is the wavelength of X-ray radiation used, β is the angular line width at

half of the maximum intensity, θ is Bragg diffraction angle and k is a constant.

Figure 5.3 SEM image of the ZnO thin film

Well-modulated ID-VD characteristics at various gate voltages (VG) of the

fabricated TFTs with air annealed sample are observed which are shown in figure

5.4. The drain current is significantly increase and show well saturated

characteristics from 12 volt gate voltage onwards and complete pinched off occurs

at 2 volt gate voltage. The TFTs are operated in enhancement mode. Figure 5.5

shows the ID-VD characteristics of TFTs without annealed sample which shows low

drain current with respect to drain voltage then that of the TFTs with air annealed

ZnO sample.

The (ID)1/2–VG plots for the TFTs at constant drain voltage VD = 10 V are shown

in figure 5.6. In figure 5.6, curve a and b are for the TFTs with air annealed and

without annealed ZnO sample respectively. From the extrapolation of the linear

portion of the graph to the VG axis of plots, the threshold voltages (VT) of the

devices are calculated. In saturation region VD=VG–VT, the drain current is given by

equation (5.5) [58] on the basis of which the electrical parameters are evaluated.

65

2TGiFEDsat )VV(C

L2

WI −= µ (5.5)



effect mobility µFE is calculated from the slope of this plot. The gain-bandwidth

product is the measure of high frequency performance of the devices. The gain-

bandwidth (G.Bw) product of the device is evaluated from equation (5.6) [1]

iC

mgBwG

π=

2. (5.6)

The Plots of log (ID) versus VG at a constant drain voltage (VD=10V) is shown in the

figure 5.7 in which curves a and b represents the TFTs with air annealed and

without annealed sample respectively. The sub-threshold swing is calculated from

the slope of these graphs using the relation (5.7) [59].

( ) 1log

−

δ

δ=

GV

DIs (5.7)

The drain current ON-OFF ratio of the device is calculated from the relation (5.8)

[58].

( )DdV

2TVGV

FEiC

OFFI

ONI

σ

µ −=

(5.8)

Where σ and d are conductivity and thickness of the semiconductor of the TFTs.

64

Figure 5.4 ID –VD characteristics of air annealed ZnO TFTs at constant VG

Figure 5.5 ID –VD characteristics of without annealed ZnO TFTs at constant VG

0 2 4 6 8 10 12 14 16 18 20

0.0

0.1

0.2

0.3

0.4

0.5

0.6VG=20V

VG=15V

VG=10V

VG= 5V

VG=2V

I D µ Ampere

VD Volt

0 2 4 6 8 10 12 14 16 18 20

0

1

2

3

4

5

6

7

8

VG=20V

VG=15V

VG=10V

VG=5V

VG=2V

I D µ Ampere

VD Volt

67

Figure 5.6 √ID - VG plots for ZnO TFTs at constant drain voltage VD =10V. Curve

a and b are for TFT with air annealed and without annealed sample respectively.

Figure 5.7 The plots of log (ID) - VG at constant drain voltage. Curve a and b are for

TFT with air annealed and without annealed sample respectively

-2 0 2 4 6 8 10 12 14 16 18 20

0.0

0.5

1.0

1.5

2.0

2.5

3.0

(ID)1/2 Ampere

VG Volt

b

a

VD = 10V

-2 0 2 4 6 8 10 12 14 16 18 20

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

0.01

b

a

log ID Ampere

VG Volt

68

The J-V characteristic of the dielectric film in Al/La3O3/Al configuration is

shown in figure 5.8. From figure 5.8 it is seen that the dielectric film show very

low leakage current and thereby approving the suitability for use as dielectric layer

in thin film transistors.

Figure 5.8 J-V characteristics of Al/La2O3/Al structure

The calculated values of mobility, threshold voltage, sub-threshold

swing, gain band-width product and drain current on-off ratio of the devices are

presented in table 5.1. and the results are compared with the TFT with without

annealed ZnO thin film. High value of field effect mobility and ON-OFF ratio are

exhibited by the TFTs. The threshold voltage and sub-threshold swing are found to

be relatively low. The gain band-width product of the TFTs is also high which is

due to the high field effect mobility. The high value of the mobility of the TFT is

due to fact that as the TFT is annealed in air at high temperature 5000 C, the oxygen

content in the films may increase which provides good quality ZnO films. At high

annealing temperature the passivation of the oxygen atoms into the interstitial

positions of the ZnO crystals and reduce the trapping of charges in the grain

-8 -6 -4 -2 0 2 4 6 8

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

Current Density J (A/cm

2)

Voltage (in Volt)

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

69

boundaries. This leads to the reduction of potential barrier at the grain boundaries

and consequently the mobility of the carrier increases. The mobility of the devices

may further be increased by annealing the devices at oxygen atmosphere which can

passivate the oxygen vacancies that create deep levels in the band gap structure [60,

63]. No significant results are observed in case of the TFTs using ZnO films

without annealing because trapping of charge carriers in the grain-boundaries of the

ZnO polycrystals occurs which acts as potential barrier and decrease the mobility as

well as other electrical parameters.

Table 5.1 Comparison of the measured values of electrical parameters of TFTs with air annealed and

without annealed sample.

Parameters

TFT with

air annealed sample

TFT with without

annealed sample

Mobility (µFE) 0.58 (cm2/Vs) 0.024 (cm /Vs)

Threshold voltage (VT)

4 V 6.6 V

on-off ratio

106 104

Sub-threshold Swing

Gain-bandwidth

Product (G.Bw)

1 V/decade 0.04 (kHz)

1.1 V/decade 0.039x10-3 (kHz)

The ZnO-based TFTs with La2O3 gate dielectric were successfully

fabricated by CBD and thermal evaporation technique. The TFTs exhibited high

field effect mobility, high on-off ratio and low threshold voltage. From this

investigation it can be also concluded that high-k rare-earth oxide La2O3 act as a

good dielectric material in TFTs and the ZnO-La2O3 is a good semiconductor –

insulator combination for TFTs. Further, effect of other dielectric materials and

doping effect of ZnO is also under investigation for the improvement of

performance of the ZnO TFTs.

***************************

70

CHAPTER - 6

SOL-GEL DERIVED DIP COATED ZnO – La2O3 THIN

FILM TRANSISTORS

This Chapter contains the fabrication of ZnO- TFTs using sol-gel technique

on perfectly cleaned glass substrates with La2O3 as gate dielectric layer. Evaluation

of various electrical parameters of the TFTs is also presented in the chapter.

6.1 Introduction

Recently ZnO has recognized as a promising semiconducting material in

optoelectronics devices and thin film transistors etc. due to its significant optical

transparency, excellent electrical conductivity and non-toxic property [83-85]. It has

been reported that for TFT applications in display technologies, ZnO does not

interact with visible light due to its wide band gap, whereas TFTs based on silicon

have some limitations of optical applications such as light sensitivity, light

degradation and opaqueness [83, 86]. Also silicon based TFTs have limited

applications due to their low field effect mobility and low drain current. Similarly

organic TFTs have the limitations of environmental degradation. On the other hand

ZnO TFTs exhibits high transparency, relatively high field effect mobility, less light

sensitivity and excellent mechanical, chemical and thermal stability [87, 88].

71

Also wide band gap semiconductor like ZnO permit to operate at much higher

voltage, frequency and temperature and hence, ZnO TFTs have received significant

attention in recent years as an alternative to silicon-based and organic TFTs [84,

74].

Variety of processes viz. vacuum deposition, metal organic chemical vapour

deposition, spray pyrolysis, sol-gel, sputtering, pulse laser deposition etc. are

usually used to fabricated and synthesize ZnO thin films. Though the different

vacuum deposition techniques provide thin films of uniform and less surface

damage, but these techniques are expensive and high energy consumption [83]. But

sol-gel techniques is one of the simplest low cost solution proceed method that

provides direct patterning of the thin film on the substrates which could replace the

conventional photolithographic printing through ink-jet printing [89]. Moreover sol-

gel technique has the advantage of low temperature processing and possibility of

fabricating on large area substrates.

Recently rare earth oxides La2O3 is under intense investigation as gate

dielectric due to their high dielectric constant, high thermal and chemical stabilities.

In this study we have used thermally deposited high –k rare earth oxide La2O3 as

gate dielectric because of its high dielectric constant (14.77) [52], and low leakage

current [79, 90] which is suitable for replacing conventional SiO2. Many

investigators [62, 78, 80, 81] have successfully used La2O3 as gate dielectric in

TFTs and microelectronics.

Here we have reported the electrical characteristics of ZnO thin film

transistors fabricated by sol-gel derived dip coated ZnO thin films as active

material. The as deposited ZnO thin films are characterized by XRD and SEM of

the samples.


The precursor solution of 0.3 M zinc acetate dehydrate

[Zn(CH3COO)2.2H2O] is dissolved into 2 Methoxyethanol. The solutions are then

72

stirred at 60oC for 2 hours and add Methanolemaine (MEA) to get a clear,

transparent and homogeneous solution. The pH of the solution is maintained as 10.

After getting a clear, transparent and homogeneous solution, the solution is now

ready for dip coating. Ultrasonically cleaned glass substrate is now dip into the

solution one by one smoothly and dried for 10-15 minutes at 1000C and allowed to

cool up. The cooled films are appeared to be light brown colour. The dried films are

then annealed at oxygen atmosphere at 5000C for one hour and then transparent

ZnO thin films of uniform surface are obtained. The flow chart showing the step by

different steps of the preparation of ZnO thin films by sol-gel dip coating method is

shown in figure 6.1.

Figure 6.1. The flow chart showing the procedure for preparing ZnO

thin films by sol-gel dip coating method.

73

Figure 6.2: Schematic diagram of the top gate coplanar electrode structure of the TFTs.

The ZnO films are used as active channel material in the TFTs. The TFTs

are fabricated in top gate coplanar electrode structure. The source-drain and gate

electrodes and the dielectric layer are deposited by thermal deposition technique in

high vacuum of the order of 10-6 torr. Al source-drain electrodes are deposited over

the oxygen annealed ZnO film with a channel of length 50 µm. High dielectric

constant rare earth oxide La2O3 of 4 nm is deposited over the source-drain

electrodes as gate insulator. Over the insulator, Al is again deposited as gate

electrode. A schematic diagram of the TFT structure is shown in figure 6.2.


The polycrystalline structure of the ZnO film is investigated through XRD

spectrum. Figure 6.3 shows the XRD spectrum of ZnO thin film annealed at 5000C

in oxygen atmosphere. Eight distinct and sharp picks (100), (002), (101), (110),

(110), (103), (112) and (201) of ZnO are observed in the XRD spectrum which

confirms the hexagonal structure and good polycrystalline growth of ZnO thin film

fabricated by sol-gel technique. Figure 6.4 shows the SEM image of the ZnO thin

film.

Current-voltage characteristics with good electrical modulation at various

gate voltages (VG) of the TFTs are observed which are shown in figure 6.5. The

drain current increases significantly and showed well saturated characteristics from

9 volt drain voltage onwards and complete pinched off occurs at 1 volt gate voltage.

74

From the I-V characteristics it is revealed that the TFTs are operated in

enhancement mode.

Figure 6.3. XRD spectrum of sol-gel derived ZnO thin film annealed at 5000C

Figure 6.4. SEM image of sol-gel derived ZnO thin film annealed at 5000C

20 30 40 50 60 70 80

(201)

(112)

(103)

(110)

(102)

(101)

(002)

(100)

Inte

nsity (

a.u

.)

2 theta (degrees)

75

Figure 6.5 ID-VD characteristics of ZnO TFTs at constant VG

The (ID)1/2–VG plots for the TFTs at constant drain voltage VD = 10 V are

shown in figure 6.6. In figure 6.6, from the extrapolation of the linear portion of the

graph to the VG axis of plots, the threshold voltages (VT) of the devices are

calculated and found as 2.5 V. The threshold voltage decreases towards negative

values which indicate that, it requires greater negative gate voltage to deplete the

larger amount of induced charges at the interface.

Figure 6.6 (ID)1/2 - VG plot for ZnO TFTs at constant drain voltage VD =10V.

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 150

10

20

30

40

50

60

70

80

90

VG=20V

VG=15V

VG=10V

VG=5V

VG=3V

VG=1.5V

VG=1V

I D (

µ A

mpere

)

VD (Volt)

-2 0 2 4 6 8 10 12 14 16 18 200.0

0.1

0.2

0.3

0.4

0.5

0.6

VD=10V

(ID)1

/2 (

Am

pe

re)1

/2

VG Volt

76

The expression for drain current in saturation region (VD=VG–VT), is given

by equation (6.1) [58]. The electrical parameters of the devices are calculated on the

basis of equation (6.1).

2TGiFEDsat )VV(C

L2

WI −= µ (6.1)



effect mobility µFE is calculated from the slope of this plot and found as 1.5

cm2/VS.

The plots of log (ID) versus VG at a constant drain voltage (VD=10V) for the

TFTs are shown in figure 6.7. The on-off ratio of the devices is measured from

figure 6.7 and the sub-threshold swing is calculated from the slope of the graph

using the relation (6.2) [59] and found 107 and 0.8V/decade respectively. The sub-

threshold swing is related to the defects of the film and semiconductor –gate

interface properties [60]. The high on-off ratio of the devices is due to the enhanced

oxygen content in the ZnO films annealed at 5000 C in oxygen atmosphere, as the

induced interface carrier concentration depends on the oxygen content in ZnO films.

( ) 1log

−

δ

δ=

GV

DIs

(6.2)

The current density vs. voltage characteristic of the dielectric film in

Al/La3O3/Al structure is shown in figure 6.8. From figure 8 it is seen that the La3O3

film show very low leakage current and hence La2O3 is suitable for use as dielectric

layer in thin film transistors.

The calculated values of mobility, threshold voltage, sub-threshold swing

and drain current on/off ratio of the devices are presented in table 6.1.

77

Figure 6.7 The plots of log (ID) - VG at constant drain voltage.

Figure 6.8 J-V characteristics of Al/La2O3/Al

-2 0 2 4 6 8 10 12 14 16 18 201E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

0.01

s=1V/deacde

VD=10V

log I

D A

mpere

VG Volt

-6 -4 -2 0 2 4 61E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

Cu

rrent

De

nsity J

(A

/cm

2)

Voltage (Volt)

1E-14

1E-13

1E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

78

Table 6.1: Measured values of mobility (µFE), threshold voltage (VT), on/off ratio

and sub- threshold swing of the fabricated devices.

From the results mentioned in the table 6.1 it can be concluded that good electrical

properties are exhibited by the fabricated TFT. High value of field effect mobility

and drain current on/off ratio are exhibited by the TFTs. The threshold voltage and

sub- threshold swing are found to be relatively low. The high value of the mobility

and on/off ratio of the TFT is due to fact that as the ZnO thin films are annealed in

oxygen atmosphere at 5000 C for 1 hour, the oxygen content in the films increases

which provides good quality ZnO films. At the annealing temperature the

passivation of the oxygen atoms into the interstitial positions of the ZnO crystals

and reduce the trapping of charges in the grain boundaries. This leads to the

reduction of potential barrier at the grain boundaries and consequently the mobility

of the carrier increases.

Sol-gel and thermal evaporation technique have been successfully employed

to fabricate ZnO TFTs which exhibits good electrical properties on annealed in

oxygen atmosphere. High field effect mobility, drain current on/off ratio, low

threshold voltage and sub-threshold swing have been observed in the case of TFTs.

It may also conclude that the ZnO-La2O3 is a suitable semiconductor –insulator

combination for the TFTs fabrication.

****************************

Electrical

Parameters

(Present results) (La2O3) (Sol-gel method)

Mobility (µFE) 1.5 (cm2V-1s-1)

Threshold voltage (VT) 2.5 V

on/off ratio 107

Sub-threshold Swing 0.8 V/decade

79

CHAPTER -7

SUMMERY AND CONCLUSIONS

ZnO is a very important semiconductor material for large area electronic

devices. Due to the possibility of depositing homogeneous films over glass and

flexible plastic substrates by chemical bath deposition technique, sol-gel technique,

thermal evaporation technique etc. at low substrate temperatures; it can be used in

various electronic applications.

The detail of the work done is divided into four sections. A brief discussion

of the sections are presented below-

Section – I : Electrical properties of thermally deposited ZnO TFTs at high

vacuum

Section –II : Fabrication of ZnO-Al2O3 thin film transistors using chemical bath

deposition (CBD) technique

Section – III : Fabrication of ZnO TFTs by CBD technique with high-k La2O3

gate dielectric

Section – IV : Sol-gel derived dip coated ZnO – La2O3 thin film transistors

In section-I, fabrication and characterization of TFTs by thermal evaporation

technique with ZnO as active material and Nd2O3, La2O3 and Al2O3 as gate

insulators has been done. All the TFTs are fabricated in coplanar electrode

80

structure under high vacuum of the order of 10-6 tor. The ZnO films are

characterised by the XRD and SEM analysis. The current-voltage characteristics of

the TFTs are evaluated and some important transistor parameters such as field effect

mobility (µFE), threshold voltage (VT) and sub-threshold swing are estimated using

suitable models. The field effect mobility (µFE), threshold voltage (VT), drain

current on-off ratio and sub-threshold swing of the fabricated devices for ZnO-

Nd2O3 TFT are found as 0.36 cm2/VS, 7 V, 1.1x105 and 1V/decade respectively.

For ZnO -La2O3 TFTs, the field effect mobility (µFE), threshold voltage (VT), on-off

ratio and sub-threshold swing are found as 0.31 cm2/VS, 3.7 V, 105 and

1.1V/decade respectively. For ZnO- Al2O3 TFTs, the field effect mobility (µFE),

threshold voltage (VT), on-off ratio and sub-threshold swing are found as

0.4 cm2/VS, 4V, 105 and 1.2 V/decade respectively.

In section-II, ZnO thin film using chemical bath deposition technique and

their potential application as active material in thin film transistors has been

fabricated. High dielectric constant insulator Al2O3 is used as dielectric layer and

the electrical properties of the devices are evaluated. Measured values of mobility

(µFE), threshold voltage (VT), on-off ratio and sub threshold swing of the fabricated

devices are 0.45 cm2V-1s-1, 1.8 V, 106 and 0.6 V/decade respectively.

In section III, the fabrication of ZnO thin films by another CBD technique

has been done with high - k rare earth oxide La2O3 as gate dielectric. The


characteristics of the TFTs with air annealed and without air annealed ZnO samples

have been done. The measured values of electrical parameters of TFTs with air

annealed sample of the TFT are found as mobility (µFE) is 0.58 cm2/Vs, threshold

voltage (VT) is 4V, drain current on-off ratio is 106, sub-threshold Swing is

1V/decade and gain band-width product is 0.04 (kHz). The electrical parameters of

TFTs without annealed sample of the TFT are Mobility (µFE) is 0.024 cm2/Vs,

Threshold voltage (VT) is 6.6V, drain current on-off ratio is 104, Sub-threshold

Swing is 1.1V/decade and gain band-width product is 0. 039x10-3 (kHz).

81

In section-IV, the fabrication of ZnO- TFTs using sol-gel technique on

perfectly cleaned glass substrates with La2O3 as gate dielectric layer have been

done. Evaluations of various electrical parameters of the TFTs are also done.

Measured values of mobility (µFE), threshold voltage (VT), on/off ratio and sub-

threshold swing of the fabricated devices are 1.5 cm2V-1s-1, 2.5 V, 107 and sub

threshold swing is 0.8 V/decade.

In conclusion of the entire findings of this investigation, the following points

are worth mentionable-

• This investigation tests the feasibility of the ZnO - TFTs with different

oxides Nd2O3, La2O3 and Al2O as gate insulator fabricated by thermal

evaporation process, chemical bath deposition (CBD) technique and sol-gel

method.

• TFTs with ZnO as active material with Al2O3 dielectric are successfully

fabricated by CBD and thermal evaporation technique. The TFTs exhibits

good field effect mobility, low threshold voltage, low sub threshold swing

and high drain current on/off ratio.

• The ZnO-based TFTs with La2O3 gate dielectric were successfully

fabricated by CBD and thermal evaporation technique. The TFTs exhibited

high field effect mobility, high on-off ratio and low threshold voltage. From

this investigation it can be also concluded that high-k rare-earth oxide La2O3

act as a good dielectric material in TFTs and the ZnO-La2O3 is a good

semiconductor –insulator combination for TFTs.

• Sol-gel and thermal evaporation technique have been successfully employed

to fabricate ZnO TFTs which exhibits good electrical properties on annealed

in oxygen atmosphere. High field effect mobility, high drain current on/off

ratio, low threshold voltage and sub-threshold swing have been observed in

the case of TFTs.

**************************

82

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91

Publications

The following papers have been published in the pear reviewed Journals which are

the outcome of the UGC Major Research Project.

1. “ZnO TFTs prepared by chemical bath deposition technique with high-

k La2O3 gate dielectric annealed in ambient atmosphere”, P. Gogoi, S.

Changmai, R. Saikia, D. Saikia and R. P. Dutta, Phys. Status Solidi A, vol.

212, No. 4, page 826–830 (2015) / DOI 10.1002/pssa.201431605.

2. “Top gate ZnO–Al2O3 thin film transistors fabricated using a chemical

bath deposition technique”, P. Gogoi, R. Saikia, and S. Changmai, Journal

of Semiconductors, vol.36, No. 4, page 044002-1-4, (2015), DOI:

10.1088/1674-4926/36/4/044002.

Seminar/Conference attended

1. Presented a paper “ZnO based thin film transistors with high-k rare

earth oxide La2O3 as gate dielectric” in National Conference on Physical

Science, organised by DHSK College, Dibrugarh, Aassm on 13th -14th of

September, 2013

2. Presented a paper “Sol-gel derived ZnO – Al2O3 thin film transistors

annealed at oxygen atmosphere” National Seminar cum Workshop on

Advances in Science and Technology and Pertinent need of Instrumentation,

organised by Department of Physics and IQAC Cell, Sibsagar College,

Joysagar in association with CSIR-NEIST, Jorhat, Assam on 9th -11th

September, 2016.

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investigation of the electrical...

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