Inverter

Motivation

The inverter is the basic gain stage for CMOS circuits. Typically, the inverter uses the common-source configuration with either an active resistor for a load or current sink/source as a load resistor. There are a number of ways in which the active load can be configured as shown in Figure 1. These inverters include the active PMOS load inverter, current-source load inverter and the push-pull inverter. The small-signal gains increase from left to right in each of these circuits with everything else equal. The active load PMOS inverter, current-source inverter and push-pull inverter will be considered in this chapter.

Prerequisites

Mosphysics , large signal models, small signal models and intro to VLSI.

Learning Outcome

Knowledge of various types of inverters.

Characterics of these inverters

Ability to decide what inverter should be used for an application.

ABility to design an inverter for given specifications.

Ability to draw and understand the characteristics

Suggested Time

7 hours

Active Load Inverter

Many times a low-gain inverting stage is desired that has highly predictable small-and large signal characteristics. One configuration that meets this need is shown in Figure 1 and is the active PMOS load inverter (we will simply use the term "active load inverter"). The large signal characteristics can be illustrated as shown in Figure 2. This figure shows the versus characteristics of M1 plotted on the same graph with the "load line" ( versus ) characteristic of the p-channel, diode-connected, transistor, M2. The "load line" of the active resistor, M2, is simply the transconductance characteristic reversed and subtracted from . It is apparent that the output-signal swing will experience a limitation for negative swings. versus can be obtained by plotting the points marked A, B, C and so on rom the output characteristics to the output-input curve. The resulting curve is called a large-signal voltage-transfer function curve. It is obvious that this type of inverting amplifier has limited output voltage range and low gain. It is of interest to consider the large-signal swing limitations of the active-resistor load inverter. From figure 2 we see that the maximum output voltage, is equal to . Therefore,

This limit ignores the subthreshold current that flows in every MOSFET. This very small current will eventually allow the output voltage to approach .

Figure 1. Various types of inverting CMOS amplifiers

Figure 2.Graphical illustration of the voltage-transfer function for the

active load inverter

In order to find v_{OUT}(min) we first assume that M1 will be in the nonsaturated (Active) region and that . We have determined the region where M1 is active by plotting the equation

which corresponds to the saturation voltage of M1. The current through M1 is

and the current through M2 as

Equating Equation 3 to Equation 4 and solving for gives

We have assumed in developing this expression that the maximum value of is equal to . It is important to understand how the lower limit of Equation (5) comes about. The reason that the output voltage cannot got to the lower limit (ground) is that the voltage across M2 produces current that must flow through M1, Any MOSFET can only have zero voltage across its drain-source if the drain current is zero. Consequently, the minimum value of is equal to whatever drain-source drop across M1 is required to support the current defined by M2. The small-signal voltage gain of the inverter with an active-resistor load can be found from Figure 3. This gain can be expressed by summing the currents at the output to get

Solving for the voltage gain , , gives

The small-signal output resistance can also be found from Figure 3 as

Figure 3.Development of the small-signal model for the active load

inverter

The output resistance of the active-resistor load invgerter will be low because of the low resistance of the diode-connected transistor M2. The resulting low-output resistance can be very useful in the situations where a large bandwidth is required from an inverting gain stage.

The small-signal frequency response of the active-resistor load inverter will be examined next. Figure 4(a) shows a general inverter configuration and the important capacitors. The gate of M2 (point x) is

connected to for the case of Figure 3. and represent the

overlap capacitances, and are the bulk capacitances, is the overlap plus gate capacitance, and is the load capacitance seen by the inverter, which can consist of the next gate(s) and any parasitics associated with the connections. Figure 4(b) illustrates the resulting small-signal model assuming that is a voltage source.. The frequency response of this circuit is

where

and

Figure 4(a) General Configuration of an inverter illustrating parasitic

capacitances (b) Small-signal model of (a)

It is seen that the inverting amplifier has a right half-plane zero and a left half-plane pole. Generally, the magnitude of the zero is larger than the pole so that the -3dB frequency of the amplifier is equal

to . Equation (11) shows that in this case, the -3dB frequency of the active-resistor load inverter is approximately proportional to the square root of the drain current. As the drain current increases, the bandwidth will also increase because R will decrease.

Current-Source Inverter

Often an inverting amplifier is required that has a gain higher than that achievable by the active load inverting amplifier. A second inverting amplifier configuration, which has higher gain is the current-source inverter shown in Figure (1). Instead of a PMOS device as the load, a current-source load is used. The current source is a common-gate configuration using a p-channel transistor with the gate connected to a dc bias voltage, . The large-signal characteristics of this amplifier can be illustrated graphically. Figure 5 shows a plot of versus . On this current-voltage characteristics the output characteristics of M1 are plotted. Since is the same as , the curves have been labeled accordingly. Superimposed on these characteristics are the output characteristics of M2 with . The large-signal voltage-transfer function curve can be obtained in a manner similar to Figure 2 for the active-resistor load inverter. Transferring the points A,B,C and so on from the output characteristic of Figure 5 for a given value of , to the voltage-transfer curve of Figure 5, results in the large-signal voltage-transfer function curve shown.

Figure 5. Graphical illustration of the voltage-transfer function for the

current-source load inverter

The regions of operation for the transistors of Figure 5 are found by expressing the saturation relationship for each transistor. For M1, this relationship is

which is plotted on the voltage-transfer curve in Figure 5. The equivalent relationship for M2 requires careful attention to signs. This relationship is

In other words, when is less than 3.2 V, M2 is saturated. This is also plotted on Figure 5. One must know in which region the transistors are operating in to be able to perform the following analyses.

The limits of the large-signal output-voltage swing of the current-source load inverter can be found using an approach similar to that used for the active-resistor inverter, is equal to since when M1 is off, the voltage across M2 can go to zero, allowing the output voltage to equal providing no output dc current is required, Thus, the maximum positive output voltage is

The lower limit can be found by assuming that M1 will be in the non-saturation region. can be given as

This result assumes that is taken to .

The small-signal performance can be found using the model fo Figure 3, with (this is to account for the fact that the gate of M2 is on ac ground). The small-signal voltage gain is given as

This is a significant result in that the gain increases as the dc current decreases. it is a result of the output conductance being proportional to the bias current, whereas the transconductance is proportional to the square root of the bias current. The increase of gain as decreases holds true until this current reaches the subthreshold region of operation, where weak inversion occurs. At this point the transconductance becomes proportional to the bias current and the small-signal voltage gain becomes a constant as a function of bias current.

Figure 6 shows the typical dependence of the inverter using a current-source load as a function of the dc bias current, assuming that the subthreshold effects occur at approximately

Animation

Fig6_inv.swf (For your convenience you can get them inside Self Learning Quadrant)

Figure 6. Illustration of the influence of the dc drain current on the small-signal voltage gain of the current-source inverting amplifier

The small-signal output resistance of the CMOS inverter with a current-source load can be found from Figure 3( with ) as

The -3 dB frequency of the current-source CMOS inverter can be found from Figure 4 assuming that the gate of M2{point x) is connected to a voltage source, V_{GG2}. In this case, is given by equations (14) and and of equations (13) and (15) become

The zero for the current-source inverter is give by Equation (12). The pole is found to be

The -3 dB frequency response can be expressed as the magnitude of , which is

assuming that the zero magnitude is greater than the magnitude of the pole.

Push-Pull Inverter

If the gate of M2 in Figure 5 is taken to the gate of M1, the push-pull CMOS inverter of Figure 7 results. The large-signal voltage-transfer function plot for the push-pull inverter can be found in a similar manner as the plot for the current-source inverter. In this case the points A, B, C and so on describe the load line of the push-pull inverter. The large-signal voltage-transfer function characteristic is found by projecting these points down to the horizontal axis and plotting the results on the lower right hand plot of Figure 7. In comparing the large-signal voltage-transfer function characteristics between the current-source and push-pull inverters, it is seen that the pus-pull inverter has a higher gain assuming identical transistors. This is due to the fact that both transistors are being driven by . Another advantage of the push-pull inverter is taht the output swing is capable of operation from rail-to-rail ( to ground in this case).

Figure 7. Graphical illustration of the voltage-transfer function for the

push-pull inverter

The regions of operation for the push-pull inverter are shown on the voltage-transfer curve of Figure 7. These regions are easily found using the definition of given for the MOSFET. M1 is in the saturation region when

M2 is in the saturation region when

If we plot Equations 27 and 28 using the equality sign, then the two lines on the voltage-transfer curve of Figure 7 result with the regions approximately labeled. An important principle emerges from this and

the previous voltage-transfer functions. This principle is that the largest gain (steepest slope) always occurs when all transistors are saturated. The small-signal performance of the push-pull inverter depends on its operating region. If we assume that both transistors, M1 and M2, are in the saturation region, then we will achieve the largest voltage hainbs. The small-signal behavior can be analyzed with the aid of Figure 8.

Figure 8. Small-signal model for CMOS inverter of Figure 7

Conclusion

The inverter is one of the basic amplifiers in analog circuit design. Three different configurations of the CMOS inverter have been presented in this section. If the inverter is driven from a voltage source, then the frequency response consists of a single dominant pole at the output of the inverter. The small-signal gain of the inverters with current source/sink loads was found to be inversely proportional to the square root of the current, which led to high gains. However, the high gain of the current-source/sink and push-pull inverters can present a problem when one is trying to establish dc biasing points. High-gain stages such as these will require the assistance of a dc_negative feedback path in order to stabilize the biasing point. In other words, one should not expect to find the dc output voltage well defined if the input dc voltage is defined.