inverter dynamics

86
EE415 VLSI Design THE INVERTER DYNAMICS apted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

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Inverter Dynamics

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The InverterDYNAMICS
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tpLH defines delay for output going from low to high
tpHL defines delay for output going from high to low
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Defines slope of the signal
Defined between the 10% and 90% of the signal swing
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A standard method is needed to measure the gate delay
It is based on the ring oscillator
2Ntp >> tf + tr for proper operation
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CMOS Inverter Load Lines
0.25um, W/Ln = 1.5, W/Lp = 4.5, VDD = 2.5V, VTn = 0.4V, VTp = -0.4V
IDn (A)
Vout (V)
X 10-4
Vin = 1.0V
Vin = 1.5V
Vin = 2.0V
Vin = 2.5V
Vin = 0V
Vin = 0.5V
Vin = 1.0V
Vin = 1.5V
Vin = 0.5V
Vin = 2.0V
*
dc points located at the intersection of the corresponding load lines
Note all operating points are located either at the high or low output levels
EE415 VLSI Design
CMOS Inverter VTC
For lecture
VTC of the inverter exhibits a very narrow transition zone; high gain during switching transient (when both PMOS and NMOS are simultaneously on and in saturation). In that region, a small change in input voltage results in a large output voltage variation.
Indicate on VTC plot where VTn and VTp lie
EE415 VLSI Design
Regions of operations
nMOS
G S
current through NMOS = current through PMOS
=> dc operating points are the intersection of load lines
All operating points located at high or low output levels
=> VTC has narrow transition zone
high gain of transistors during switching
transistors in saturation
high transconductance (gm)
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Switching Threshold
VM where Vin = Vout (both PMOS and NMOS in saturation since VDS = VGS)
VM rVDD/(1 + r) where r = kpVDSATp/knVDSATn
Switching threshold set by the ratio r, which compares the relative driving strengths of the PMOS and NMOS transistors
Want VM = VDD/2 (to have comparable high and low noise margins), so want r 1
(W/L)p kn’VDSATn(VM-VTn-VDSATn/2)
=
*
Assumes: The supply voltage is high enough so that the devices are velocity-saturated (VDSAT < VM – VT) and ignores channel length modulation.
Reminder:
k = k’W/L and k’ = mu Cox (mu is carrier mobility)
Larger r to move VM upwards means making the PMOS wider
Smaller r to move VM downwards means making the NMOS wider
EE415 VLSI Design
Switch Threshold Example
(W/L)p = 3.5 x 1.5 = 5.25 for a VM of 1.25V
VT0(V)
(V0.5)
VDSAT(V)
=
3.5 x 1.5 so (W/L)p = 5.25
EE415 VLSI Design
Simulated Inverter VM
VM is relatively insensitive to variations in device ratio
setting the ratio to 3, 2.5 and 2 gives VM’s of 1.22V, 1.18V, and 1.13V
Increasing the width of the PMOS moves VM towards VDD
.1
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Plot needs work – but it’s the best I could do with powerpoint graphing
Small variations in ratio don’t make a lot of difference
To move the VM to 1.5V requires a ratio of 11 !!!
Note that the x axis is semilog
EE415 VLSI Design
Vin
Vout
By definition, VIH and VIL are where dVout/dVin = -1 (= gain)
VOL = GND
NMH = VDD - VIH
NML = VIL - GND
*
A high gain in the transition region is VERY desirable. In the extreme case of an infinite gain, the noise margins simplify to VOH – VM and VM – VOL for NMH (ideally, VDD – VM) and NML (ideally, VM – GND), respectively, and span the complete voltage swing.
EE415 VLSI Design
Vin (V)
Vout (V)
*
Note: simulation overestimates the gain – as seen on the next slide, the maximum gain (at VM) is only -17
And piece-wise linear approximation model is optimistic wrt noise margins.
Low output resistance is a good measure of the sensitivity of the gate wrt noise induced at the output and should be as low as possible.
EE415 VLSI Design
Gain Determinates
Gain is a function of the current slope in the saturation region, for Vin = VM
(1+r)
Only designer influence through supply voltage and VM (transistor sizing).
Vin
gain
Pprocess variations (mostly) cause a shift in the switching threshold
Nominal
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A good device has a small oxide thickness (-3nm), a small length (-25nm), a higher width (+30nm) and a smaller threshold (-60mV). The opposite is true for a bad device.
EE415 VLSI Design
Gain=-1
Vin (V)
Vout (V)
*
Not the best curve for 0.5 supply (but the best I could do in ppt).
Observations
The gain of the inverter in the transition region increases with a reduction in Vdd. For a fixed r, VM is proportional to Vdd.
At a voltage of 0.5V (just 100mV above the threshold of the transistors) the width of the transition region measures only 10% of the supply voltage (and a gain of -35), while it widens to 17% for 2.5V
But, reducing the supply
Is absolutely detrimental to the performance of the gate
The dc characteristics become increasingly sensitive to variations in the device parameters (e.g., VT)
Scaling the supply means reduced signal swing making the gate more sensitive to external noise sources that don’t scale
Note, in plot on the right, we still obtain an inverter even though the supply voltage is not large enough to turn the transistors on! The subthreshold current is sufficient to switch the gate between low and high levels, as well as to provide enough gain to produce an acceptable VTC.
The ultimate show stopper is when the gain in the transition region approaches 1 (as in the green curve on the right plot) – giving the true lower bound on supply scaling (without cooling the chip).
EE415 VLSI Design
Switch Model of Dynamic Behavior
Gate response time is determined by the time to charge CL through Rp (discharge CL through Rn)
CL
VDD
Rn
Vout
For class.
response determined mainly by the output capacitance of the gate, CL - drain diffusion capacitance of the NMOS and PMOS transistors; the connecting wires, and the input capacitances of the fan-out gates
A fast gate is built either by keeping the output capacitance small or by decreasing the on-resistance or the transistor (or both)
Decreasing the on-resistance achieved by increasing the W/L ratio of the device
Be award that the on-resistance of the NMOS and PMOS transistors is not constant; rather it is a nonlinear function of the voltage across the transistor
EE415 VLSI Design
V
DD
V
DD
V
in
V
out
M
1
M
2
M
3
M
4
C
db
2
C
db
1
C
gd
12
C
w
C
g
4
C
g
3
V
out
2
Fanout
Interconnect
V
out
V
in
C
L
Simplified
Model
tpHL = f(Ron*CL)
low fan-out
Decrease on-resistance of transistor
*
Define
Determining VIH and VIL
*
?
tf
tr
tpHL
tpLH
The top time is from simulation
the bottom from solving the (simplified) equations
Note overshoots on simulated output signals. Caused by the gate-drain capacitances of the inverter transistors which couple the steep voltage step at the input node directly to the output before the transistors can even start to react to the changes at the inputs.
These overshoots have a negative effect on gate performance and explain why the simulated delays are larger than the estimations.
EE415 VLSI Design
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Sizing factors larger than 10 barely yields any extra gain
(and cost significantly more area).
S
tp(sec)
*
Making S infinitially large yields the maximum obtainable performance gains.
Bulk of the improvement is already obtained for S = 5, sizing factors larger than 10 barely yield any extra gain.
While sizing up an inverter reduces its delay, it also increase its input capacitance – impacting the delay of the driving gate!
EE415 VLSI Design
PMOS/NMOS Ratio Effects
of 1.6 to 1.9 gives optimal performance
= (W/Lp)/(W/Ln)
tp(sec)
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Observe that the rising and falling delays are identical at the predicted point of beta of 2.4 (the crossing point of the three curves) that is the preferred operation point when the worst-case delay is the prime concern.
EE415 VLSI Design
Input Signal Rise/Fall Time
The input signal changes gradually (and both PMOS and NMOS conduct for a brief time).
This affects the current available for charging/discharging CL and impacts propagation delay.
ts(sec)
tp(sec)
x 10-11
x 10-11
for a minimum-size inverter with a fan-out of a single gate
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Have assumed until now that the input signal abruptly changes from 0 to Vdd or vice versa. In reality, the input signal changes gradually and, temporarily, the PMOS and NMOS transistors conduct simultaneously).
ts is the input switching time (delay) slope
If the driving gate were infinitely strong, its output slope would be unaffected (by the load).
EE415 VLSI Design
Assume that for WP = 2WN =2W
same pull-up and pull-down currents
approx. equal resistances RN = RP
approx. equal rise tpLH and fall tpHL delays
Analyze as an RC network
tpHL = (ln 2) RNCL
tpLH = (ln 2) RPCL
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CL
*
= Delay (Internal) + Delay (Load)
f = CL/Cgin effective fanout
R = Runit/W ; Cint =WCunit
How many stages are needed to minimize the delay?
Real goal is to minimize the delay through an inverter chain
the delay of the j-th inverter stage is
tp,j = tp0 (1 + Cg,j+1/(Cg,j)) = tp0(1 + fj/ )
and tp = tp1 + tp2 + . . . + tpN
so tp = tp,j = tp0 (1 + Cg,j+1/(Cg,j))
In
Out
CL
Cg,1
1
2
N
EE415 VLSI Design
Optimum Delay and Number of Stages
When each stage is sized by f and has same fanout f:
Minimum path delay
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CL/C1 has to be evenly distributed across N = 3 stages:
*
EE415 VLSI Design
The optimum N is found by differentiating the minimum delay divided by the number of stages and setting the result to 0,
For = 0 (ignoring self-loading) N = ln (F) and the effective-fan out becomes f = e = 2.71828
Optimal Number of Inverters
What is the optimal value for N given F (=fN) ?
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For a given load, CL and given input capacitance Cin
Find optimal sizing f
*
EE415 VLSI Design
Optimum Effective Fan-Out
Choosing f larger than optimum has little effect on delay and reduces the number of stages (and area).
Common practice to use f = 4 (for = 1)
Too many stages has a negative impact on delay

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note that curve on the left starts to increase at 5 ! reinforcing last bullet
EE415 VLSI Design
CL = 64 Cg,1
Impressive speed-ups with optimized cascaded inverter chain for very large capacitive loads.
F ( = 1)
good for performance
good for power consumption
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EE415 VLSI Design
Power influences design decisions:
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Dynamic power:
(dis)charging capacitors
proportional to switching frequency
leakage
fast charge transfer => fast gate
fast gate => more power consumption
Power-delay product (PDP)
PDP = energy consumed /gate / switching event
measured using ring oscillator
*
No path exists between VDD and VSS in steady state
No static power consumption! (ideally)
Main reason why CMOS replaced NMOS
NMOS technology:
Creates voltage divider when pull-down is ON
Power consumption limits # devices / chip
CMOS Inverter: Steady State Response
*
*
*
*
Short circuit current goes to zero if tout_fall >> tin_rise,
but can’t do this for cascade logic.
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Keep the input and output rise/fall times equal
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JS = 10-100 pA/mm2 at 25 deg C for 0.25mm CMOS
JS doubles for every 9 deg C!
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Principles for Power Reduction
Prime choice: Reduce voltage!
Supply voltage was reduced from 5 V to 1V over the years
25 time reduction of switching power
Reduce switching activity
Reduce physical capacitance
fopt(energy)=3.53, fopt(performance)=4.47
kT/q does not scale
Energy scales slowly
Ed Nowak, IBM
Make things cheaper:
Want to sell more functions (transistors) per chip for the same money
Build same products cheaper, sell the same part for less money
Price of a transistor has to be reduced
But also want to be faster, smaller, lower power
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Reduce gate delay by 30% (increase operating frequency by 43%)
Double transistor density
Reduce energy per transition by 65% (50% power savings @ 43% increase in frequency
Die size used to increase by 14% per generation
Technology generation spans 2-3 years
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Minimum Feature Size (nm)
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CMOS SiGe-BICMOS III-V (InP)
SAT TV/WLAN RADAR
IMT2000 Automotive Military
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(e.g., reduced bit-line swing in memory)
Consider switching a CMOS gate for
N
N
1960
1970
1980
1990
2000
2010
10
-2
10
-1
10
0
10
1
10
2
Year
• Fixed Voltage Scaling
together by the same factor
S
only dimensions scale, voltages remain constant
most realistic for todays situation —
voltages and dimensions scale with different factors