Working Inside and Outside of the ProcessorInside of the Processor

We are familiar with various addressing schemesLet’s quickly review basic methods

To alter the flow of control through programAltering flow of control involves context switch

ContextInformation that characterizes

Current executing environment of programIncludes items such as

Program counterAuto variablesRegister contentsState of globals

Context SwitchChange from current context to new oneMay involve

Saving current oneRetrieving old one

Depending upon tasks to be performedTakes varying amounts of time

Can be critical in real time system

Let’s look at alternatives at high level firstWe have 4 basic ways we can proceed through program

SequentialEach instruction executed in sequence

BranchSelect one of several branches based upon conditionGraphicallyType of construct seen in

if elseswitch or case

LoopRepeatedly execute set of instructions

ForeverUntil some condition met

Can make decision Before

Code may not be executedAfter loop

Code executed at least onceType of construct seen in

do or repeatwhilefor

ProcedureLeave current contextExecute set of instructionsReturn to contextType of construct seen for

Procedure or subroutine callInterrupt handlerCo-routine

Let’s now look at assembly language levelSequential

a = 10;

b = 20;

c = a + b;

clr R0;

addi R0, 10 // puts 10 into R0

clr R1;

addi R1, 20; // puts 20 into R1

add R0, R1; // computes R0 + R1 and puts result into R0

Branchif - else construct

Assume a .. e in registers R1..R5

Loop

Assume a in R2 and i in R3

if (a == b)

c = d + e;

else

c = d - e;

cmp R1, R2 // test if contents of R1 and R2 equal

beq $1 // if equal branch to $1

// $1 is a label created by compiler

sub R4, R5 // compute d - e and put results in d

movea R3, R4 // move results to c

jmp $2 // $2 is label created by compiler

$1: add R1, R2 // compute d + e and put results in d

movea R3, R1 // move results to c$2: ...

while (a < 10)

{

i = i + 2;

a++;

}

br $2 // jump around code

$1: add i, 2 // compute i + 2 put result in i

inc c // auto increment c

cmp c, #0AH // compare c with 10

blt $1 // continue looping

$2: ....

Procedure CallMost complex of flow of control constructsNot more difficult

More involvedWill include

ProceduresSubroutinesCo-routines

ProcessWe’ll consider from high levelProgram loaded at address 3000Code executed until address 3053Procedure encountered

1. Save return addressSeveral important things to note

Address saved is 3054Stack gets

Return addressParameters

2. Address of procedure 5000 put into PC3. Instruction at 5000 begins executing4. Execution continues until 50535. Return encountered

Action similar to callStack gets

Return valuesStack looses

Return address6. Return Address put into PC7. Execution continues at 3057

Had procedure call been encountered in procedure F!Identical process repeated

Can be repeated multiple timesMust be aware that stack can overflowIf too much pushed on

Begin to loose informationParticularly return address

3000 Code

3053 Procedure Call F1

3054 More Code

5000 F1

Procedure Code

5053 Return

CoRoutineSpecial kind of procedure callMutual call exchange between

Co-operating proceduresExclusive procedures

Sharing timeMechanics are the same as procedure call

Major differenceConventional procedure executes until end

Unless leaves under extraordinary circumstancesCo-routines

Exit and returnThroughout body of procedure

Usually under directionThird process or procedure

Graphically process appears as shown

Control procedure starts processContext switch determined by

Control procedure External event

Timing signalInternal event

Data valueProcess continues until procedures completedWith each switch

Appropriate information from current contextMust be saved

Interfacing to the Outside WorldIntroduction

There are variety of ways and reasons to talk to outside worldConsider first kinds of devices we may want to interface to

For embedded systems tasks include Measuring Controlling Interacting with other subsystems Computing

Accelerators

Graphics Communications

Collectively such devices called I/O systemDevices we may interact with include

File systems and storage devicesRead and write data

NetworkSend and receive dataExecute remote procedures

Keyboard and mouseInteract with computer

Scanning devicesBring in information

Display and printing devicesDisplay variety of data

The procedure serves as basis for look at Interacting with outside world signalsControlling such devices

As we’ve noted embedded systemsDesigned to perform some task

Performing such a task means interfacing with world outside processorSuch tasks may include

Making measurementsControlling motorRunning telecommunication system

We are dealing with portions of von Neumann machine Designated

Input and OutputMemory

When consider memory mapped I/O

When studying processor input and outputWe must look at several things

Data source or destinationI/O ports Memory address space

Nature of the exchangeThree types possible

EventShared variableMessage

NoteSuch exchange also occurs between / among

Tasks within same processor How I/O procedure invoked

Associated restrictions Where procedure resides Protocol for the data exchange Timing requirements The physical medium of the exchange

Let’s look at each of these We’ll begin with the physical mediumWe call such a medium a bus

BussesComprised of

AddressControlData

Serial Bit and characterCharacter

ParallelCharacterCharacter and Word

TimingOur exchange with outside world

SynchronousBased upon some timing element

AsynchronousStart of and subsequent transactions temporally independent

AsynchronousTransfer independent of sender / receiver timing

SynchronousTransfer dependent upon sender / receiver timing

Busses a Deeper Look

To understand input and outputWe must have some understanding of

How we communicate with such devicesThree general configurations

Star

RingBus

Each has certain advantages and disadvantagesFor all configurations

Two kinds of messagesAddressed to single device

MulticastStar

Master slave kind of arrangement Device to device communication must go through masterTransmit

Device at center directs activities and message exchangeWith all other devices

ReceiveMaster transmits to desired destinationsFailure

If one device or link fails

Communication with others continuesRing

Variants are common in communication networksBasis for token ring networks

Embedded processors in an automobileThere is typically no bus masterDevice accepts all messages circulating in ring

If device receiving message ADDRESSED deviceMessage accepted

Else Message passed on o next device

TransmitSome protocol used to decide who is able to transmit messagesTo use the bus

ReceiveAll devices can listen for message

FailureRing usually implemented as two concentric rings

If device fails or ring severedCan repair itself by reconfiguring

Traditional BusVariation on the star architecture

May or may not be a bus masterSimple bus probably one of more common architecturesDevice interconnection several ways

All can transmit or receiveSome transmit or receive onlyControl bus to all or request / grant configuration

TransmitIf bus master

It addresses deviceSends informationPermits another device to transmit

ElseSome protocol used to decide who is able to transmit messagesTo use the bus

Messages may be

Broadcast Multicast Polled

ReceiveAll devices can listen for message and act on message

FailureIndividual device failure will not compromise netSevered net can prevent communication beyond severed point

Elements of a BusWhichever scheme we choose

Generally must provide three basic functions Data Address Control

AddressAn important question

How do we define and establish an addressInitial address for a deviceSubsequent addresses as device added to system

Current schemesGeographic addressing

Addresses are dynamically assigned during initial configurationSometimes called enumeration

As new device attached to system and detectedForward capabilities

Serial System Address sent down same path as dataAppears first to select receiver

Typically address and data Have some means to distinguish

Bit pattern

Parallel SystemAddress may be handled in two main ways

Transmit over same bus as dataPrecedes data

Works like serial method only fasterTagged to distinguish from data

Either as part of transmission or with control lines

Transmit each over separate busBus may be same size as data

Depending upon architectureMay be larger if also used to access memorySmaller is special bus

Transmitted simultaneously with data

Now gain greater throughputAddress and data simultaneously sent

In either caseStrobes are essential

Identifies when signals on a bus are Stable and valid

Without strobe No way to tell

ControlNumber and structure depend upon nature of systemTypical signals may include

Read / WriteAddress / Data present or stableClock

Where does the clock come fromSeparate lineEncoded in the data

Transmission DirectionReady or ActiveSynchronizeResetPower

May or may not be counted as control signal

DataWhether serial or parallel

Data lines carry information we wish to transmit or receiveWhen in parallel

Will typically carry one wordFor system with 32 bit words

Bus would be 32 bits wideCarry DB0 - DB31

Important to determine which is the MSB and which the LSB

Data Source or DestinationData may be exchanged with external world

Two waysI/O ports Memory address space

I/O PortsInput / Output Ports

Number of lines on processor dedicated Bringing data into processorSending data out of processor

Direction

Lines may be InputOutputInput and Output

Unidirectional lines tend to be staticDirection established

HardwareDuring initialization

Bi-directional lines are dynamicDirection selected

Based upon nature of transactionUsually grouped in sets of 4 or 8

Direction for entire group set

Memory Address SpaceRead from or written to

Locations within the processorsPrimary memory address space

Will elaborate shortlyWhen discuss memory mapped I/O

Where is the ProcedureAlthough state of embedded systems art changingPresently embedded system limited to

MicrocontrollerROMRAMAssorted support chips

Generally do not have luxury peripheral processor Consequently I/O routine resides within

Address space of embedded processorAs driver or set of drivers

Associated with the I/O ports

Several primary ways procedure implementedWith and without help from processor

Memory Mapped I/O Program Controlled I/O Peripheral Processor

Memory Mapped I/OBasic idea is to for memory and I/O to share the same address space

That is map I/O space into an memory addressI/O reads and writes are done to memory addresses

Traditional scheme used in PCSuch a scheme places the responsibility of external communication

Onto CPUSimple to implementAdds extra task

ImplementationAssign address to each input or output deviceSome devices may have multiple addresses

ReadWrite

Such addresses are typically hard codedUsing switches or jumpers

Early PCs used such a schemeExpansion led to

Address conflictsIRQ conflictsLimited expansion

AdvantageEasy to implementLow cost

DisadvantageExtra burden on CPUPotentially slow

Let’s see how this works

Device connected to system Address bus

80196 Address linesA0 - A15Shared with Ports 3 and 4

Appear during address portion of external bus cycleA0 - A15 Muxed with Data in 16 bit modeA0 - A7 Muxed with Data in 8 bit mode

Data Bus

80196 Data linesD0 - D7

Appear on P3D0 - D16

Appear on P3 and P4

Control Bus80196

ALE - Address Latch EnableHigh Going Trailing Edge identifies valid address

RD - Low GoingTrailing Edge identifies data read

WR - Low GoingTrailing Edge identifies data read

Decode its addressRespond as appropriate for control signalsAddress lines usually stored in buffer

As seen in accompanying figureData lines usually buffered

Prevent interfering with other data signalsAccompanying figure illustrates

Bi-directional busHigher speed systems

Hard constraintsHave two unidirectional buses

ALE

Address Out Data In

Address Out Data Out

RD

WR

Don’t want cost of turning bus around

Data transfer may beSingle wordBlock of words

For 80196Must set EA to logic 0 level

EA input to select external memory accessGenerally hardwired

Recognized during chip resetMust partition address space

CodeDataI/O Devices

Code fragmentsC

*anAddress = aValue;aValue = *anAddress;

AssemblerLD aReg, anAddress ;Register <- dataST anAddress, aReg ;Register -> an address

Program Controlled I/OInstructions exist in the CPU instruction set

Execute the transfer of dataIN type instruction used to transfer data

From Specified memory location or I/O Port

ToSpecified memory location or Register

OUT type instruction used to transfer data From

Specified memory location or RegisterTo

Specified memory location or I/O Port

For 80196These instructions are

LDB breg, baop

Code fragmentsC

ioport1 = aValue;aValue = ioport1;

return (ioport1);

AssemblerLDB ioport1, aReg;LDB aReg, ioport1;

Peripheral ProcessorAs noted with memory mapped I/O

CPU must be involved in all transactionsIncluding detailed timing

Can place significant burden on CPUPeripheral processor scheme

Dedicates processor to handle all I/O tasksBasic architecture appears as

Peripheral processor May or may not be connected to memory

Several interface schemes utilizedVarious levels of involvement of

System BusCPUNon peripheral devices

Alternative protocolsBased upon level of CPU involvement

CPU send / receive from peripheral processorPP

Manages all I/O Uses bus in bursts during exchangeSignals CPU when data available

CPU tells peripheral processor where to find / put data in memoryPP

Exchanges data with memoryManages all I/O Signals CPU when data available Uses bus

In bursts during exchangeFor duration of exchange

DMAUsing address passing and shared buffer

CPU enables non-peripheral device and peripheral processor to communicate

PP Exchanges data with deviceManages all I/O Signals Device when data available May signal CPU when completeUses bus

In bursts during exchangeFor duration of exchange

AdvantageI/O speed independent of CPUUnburdens CPU

DisadvantageHigher costComplex

Nature of the ExchangeThree types possible

EventShared VariableMessageObserve these are abstractions

Within each typeVariety of related signals

Exchange may be usedOutside world

Between tasks within processorExchange typesEvent

Event is change in state signalUsually assumed to be single signalGenerally asynchronous to executing processEvery occurrence of event

Simultaneously activates Functions procedures to tasks

Linked to itOccurrence of event

May or may not be stored in some wayBecomes important issue in real time systems

Acquired in several waysSampled

One example called pollingArrives in form of asynchronous input

One example called interruptProcessor may or may not respond

GeneratedUnder software control of

I/ O port or lineWrite to data line accompanied by control signal

Shared VariableVariable may be read or written by multiple

ProcessorsI/O devices

Used to exchange data between asynchronous functionsBecause no inter process timing constraints

Integrity of data must be respectedSuch shared data

Represent critical sectionProtect with

SemaphoreMonitor

As we learned earlier with shared dataAmong tasks and threads

Shared variable(s) may be Global

Normally discouraged in traditional programmingWe use such schemes in real time embedded systems

Eliminate cost of passing parameters via stackHere we may designate

A global buffer area into which to store dataPointer to buffer area

PassedUsually done as pointer to buffer areaPassed by task or thread

Wishing to do I/O

DirectionUnidirectionalBi-directional

ModificationReadRead/Write

Nature may beComplete word

If in memory space1 to several bits if in I/O port spaceComplex data type

Pointer exchangedMessage

May be exchanged via

Proprietary networkOne of several standards

Which ever approach usedTypically implemented as hierarchy virtual networks

Above the hardwareVarying number of software layers or levels

At each level A different language is spoken

Referred to as a protocolThe function is to provide services for the level aboveRelationship

Service providerService consumer

Entire collection called A network architecture

Set of protocols used by a machine calledA protocol stack

Information sent on each level calledA message or messagesIt is possible that message on higher level

Composed of several lower level messages

Two major protocol schemes or stacks usedOSI

Open Systems Interconnection modelProposed and developed by

The International Standards OrganizationComprises 7 layer virtual machine

TCP /IPTransmission Control Protocol / Internet ProtocolComprises 5 layer virtual machinePhysical and data link layers of OSI

Combined intoHost to network layer

When we elect to communicate via either standardWe generally integrate a

Commercially available protocol stack

OSI TCP/IP

Physical Host to NetworkData LinkNetwork InternetTransport TransportSession Not PresentPresentation Not PresentApplication Application

Messages compriseSeveral complete words

Simple1 - 2 words transferred

ComplexSeveral blocks of data

Message exchange Can be viewed as producer - consumer relationshipUsually follows some protocol

Start of messageHeader informationBodyError managementEnd of message

Message may be transmitted Serial / Parallel

SerialData transferred into out of processor1 - 2 lines

1 Line May be

UnidirectionalInput or output onlyHalf duplex

Bi-directionalOne direction at a timeControlled by protocolDuplex

2 LinesData transferred in both directions

SimultaneouslyFull duplex

Perhaps some control lines

ParallelUsually width of wordTransmission

UnidirectionalInput or output only

Bi-directionalOne direction at a time

Timing and Data ExchangeInterface can be designed to be synchronous or asynchronousLet’s look first at the asynchronous

Asynchronous No clockExchanges co-ordinated using some form of handshaking protocolSuch protocols can be simple or complexTypical examples

Strobe associated with each data wordNo acknowledgment of acceptance

ObserveStrobe can be of either polarity

Strobe associated with each data wordEach data word acknowledged

With return strobe

Full handshakeReady for dataHere’s dataI’ve got itOKExchange looks like this

Time from bit transitionOften used in serial protocolsAgreed upon

Change in state on data line signals Start of transmissionEnd of transmission

Potential problems

Difficult to testClock noise more difficult to filter outPotentially complex protocol

To identify start / end of transmission

Potential advantagesDevices may run at different / differing speedNo clock skew on long busses

Synchronous There are several drawbacks of the asynchronous transmission schemes

Extra overhead of control bitsBit clock synchronization scheme less reliable at higher data rates

Problems can be alleviated with synchronous transmissionStill must achieve

Bit, character, frame synchronizationFrame synchronization usually derived from the formerGenerally includes clock in control lines

Exchanges between sender and receiverSynchronized to the clock

Directly Signals derived from the clock

Manchester phase encodingSerial Exchange

Clock either separate or encoded in dataParallel Exchange

Clock one of control lines

Bit Synchronization

Two schemes typically usedEncode the clock in the dataRe-derive the clock from the data

Encoded Clock

Three different methods generally used

Bipolar Encoding

Binary 0’s and 1’s are represented by Different polarity signals

Each bit cell contains clocking informationObserve

Signal returns to zero level after each encoded bitReferred to as return-to-zero RZ signal

Scheme requires 3 distinct signal levels

Manchester Phase Encoding

Binary 0 - high to low signal transitionBinary 1 - low to high signal transitionTransition in the center of each bit cell

0 11 0Provides the clock information

Observe Signal does not return to zero level after each encoded bitReferred to as non-return-to-zero NRZ signal

Manchester Differential Encoding

Transition in the center of each bit cell

0 11 0Provides the clock information

Transition at the start of each bit cell Only if next bit to be encoded is a binary 0

Re-derive the Clock

Use a preamble including sync sequenceDone using phase lock loop- PLLBased upon very stable receiver clockPLL used to keep sample clock locked

Signal transitions of incoming signalData encoded to ensure a sufficient number of signal transitionsAt each transition sample timing adjusted to ensure

Sampling in center of bitScheme will tolerate intervals without transitions

Based upon stability of the clock

Bit / Character / Frame Synchronization

Once individual bits are identified

Potential problemsAll devices must run at same speedClock skew on long busses

Because of different loadingHave propagation delay along busClock arriving at different times with respect to data

Along busClock noise in system

Potential advantagesEasier to testSimpler protocolEasier to stay in sync with data

Interrupts and PollingOnce we have decided upon a the physical configuration

Outside world connectionSeveral aspects of exchange remainWill often be interacting with several devices

Must determine How best to share resources

Cannot afford to continually watch device To determine if it

Has some informationIs ready to receive (more) information

Exactly like we do inside the processorSeveral methods by which the is done

PollingInterrupts

Let’s examine eachPolling

With polling schemeWe need a control device

Controller can be eitherCPUPeripheral Processor

Execution proceeds as follows

In the polling loopInterrogate each external device

That may be servicedSuch service may be necessary on several occasions

During power up On demand As part of normal flow of

control1. Send device address2. Receives response

Response may consist ofSingle signalWord

StateStatus

a. If goal to transmit or receive data to device

When device ready received Transfer to appropriate routineExecute transferReturn to polling loop

b. If goal is to collect statusCan do so and continue polling other devicesStatus may include

Self test resultsReady condition after power upAvailability for additional transferData available

In such loopControl device knows with whom it is communicating

This is important

Problem with pollingControl device can do nothing else while polling

Advantage howeverProcess deterministicTime to complete predictable

InterruptGoal of interrupt scheme same as that of polled scheme

DifferenceControl device not dedicated to monitoring external devices

External interrupts are going to be hardware basedI/O system may have from 1 to many interrupt linesEach line may be connected to 1 or several devices

Let’s look at the interrupt hierarchy

Single Interrupt Line with Single Device

Let’s first examine how single interrupt might workAs name suggests

Interrupt signal interrupts foreground activity

Identifying the interrupting device easyOnly single device

When interrupt occurs several actions possibleIgnoreRespond

IgnoreWill discuss shortly

RespondResponding to interrupt much like subroutine callProcedure

1. Suspend current process2. Branch to ISR appropriate to interrupting device3. Execute routine4. Resume former process

Single Interrupt Line with Multiple DevicesDealing with multiple devices on single interrupt

Only slightly more complicated

One method of connecting to the interrupt lineIllustrated in figure below

Each source uses open collector driver to connect to the interrupt line

Interrupt connected to controller as shownController responds with ack

Indicates acknowledge of interruptAck is chained through the peripheral devices

If devicei has not generated Passes ack to devicei+1

ElseProceeds with task associated with interrupt

Observe priority determined byPhysical proximity to controller

Closest device has highest priority

Identifying the Interrupt SourceWith multiple sources on single interrupt

Dilemma of courseIdentifying which device is requesting service

Several alternatives available to identify source of interruptPollingVector

PollingStraight forwardSequence

Interrupt occursSuspend current taskBranch to high level handler

Poll devices to identifyBranch to appropriate handler routine

Handle Return

Resume suspended task

VectorWith vector schemeDevice requesting service

InterruptsWhen acknowledged

Returns identifier of some sortCan be

Device nameAddress of service routine

Sequence then proceeds as with polled alternative

Multiple Simultaneous InterruptsWith several devices on the same lineMust now address question

How to accommodate multiple Simultaneous interrupts Sequential interrupts

Simultaneous InterruptsMust have priority schemeCan be

Physical proximityAssigned

Higher priority device gets serviced first

Sequential InterruptsIf second interrupt occurs while handling first

Ignore until finished with firstAssign each device priority

If interrupting device has higher priorityHandle in same waySimilar to calling subroutine from subroutine

Multiple Interrupt Lines with Single Device on EachFor each line

Same as single line with single device

With multiple linesMust assign priority to eachSame as single line with multiple devices

Can manage priority in several waysExternal hardware

Internal hardwareInternal softwareExternal Hardware

Can use device called priority encoder

For such a deviceWe assume int0 is the highest priority

If Int0 is assertedOut0 will be asserted

If Int0 is not asserted and any other interrupt input, Inti is assertedCorresponding output Outiwill be assertedIf subsequently Int0 is asserted

Out0 will be assertedProcessing of Inti is suspended

Int0 processing commences

Internal HardwareSame scheme as described above

Implemented in hardwareInside controller chip

Internal SoftwareSame scheme as described above

Implemented in softwareInside controller chip

Multiple Interrupt Lines with Multiple Devices on EachFor each line

Same as single line with multiple devices

With multiple linesMust assign priority to eachSame as single line with multiple devices

Masking InterruptsMasking is process of ignoring interrupt

By preventing propagation of occurrenceTo interrupt management

HardwareSoftware

As with other concepts we’ve looked atCan be implemented in

Software or hardwareLet’s look at a hardware implementation

Software would implement same idea

An interrupt is Enabled

By placing a logical one on the enable input

DisabledBy placing a logical zero on the enable input

Observe The interrupt can still happen

Blocked from affecting signal - Interrupt

We could incorporate a priority schemeGeneral term is of the form

ei * ii * !ii+1 * !ii+2 *….Higher priority interrupts are

Those to the right

How I/O Procedure InvokedI/O procedure resides in primary memory space

As collection of functionsWritten to perform some task

Invocation can occur in several waysObserve these are event type signals

Polled LoopIf timing on event critical

Sit in loop waiting for change in state of some variableWhen state change occurs

Invoke procedure by giving its nameThis is a foreground task

InterruptChange in state on interrupt lineInvokes interrupt process

Generally causes context change to location in memoryContains addresses of all interrupt procedures

Interrupt identifiedAppropriate procedure selectedProcedure invoked by giving its nameReturn to original context

This is a background task