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Introduction to VHDL (part 1)
EE 162 Digital Circuit Design
Vojin Oklobdzija
by Vishal Nawathe
What is HDL and VHDL?
HDL is short for Hardware Description Language
VHDL is short for VHSIC HDL
(Very High Speed Integrated Circuit)
VHDL is a programming language
Its purpose is to assist digital/circuit
designers to describe the characteristics
of a circuit.
VHDL Design Flow
SIMULATION
DESIGN IDEA
SYNTHESIS
CIRCUIT GENERATION
CIRCUIT IMPLEMENTATION
VHDL MODEL
SIMULATED WAVEFORMS
Program Structure
ARCHITECTURE
LIBRARY/PACKAGE
ENTITY
For sake of comparison to C, library is similar to C header file (#include <stdio.h>) and entity/architecture can be considered as the ‘main()’ function
The program may contain other modules like configuration declaration and package declaration/body (discussed later)
Naming Conventions
Valid names:
◦ decode8
◦ just_in_time array_4
Invalid names:
◦ 8decide (begins with a digit)
◦ my design (space inside a name)
◦ signal (reserved word/keyword)
◦ your_words? (special character ? not allowed)
◦ _what_4 (begins with underscore)
◦ in__time (two consecutive underscores)
Code
library ieee;
use ieee.std_logic_1164.all;
entity latch is
port (s,r: in bit;
q, nq: out bit);
end latch;
architecture arch1 of latch is
begin
q<= r nor nq;
nq<= s nor q;
end arch1;
Library
and
Package
Entity
Architecture
Entity/Architecture
ENTITY: ◦ A hardware description of a digital system is called an
entity
◦ An entity is the most basic building block in a VHDL design
◦ It describes the interface and how the component or circuit interacts with the outside world via ‘ports’ (similar to I/O pins)
◦ Ports can be in, out, inout or buffer
ARCHITECTURE : ◦ The architecture contains the internal description of the
entity
◦ It describes the functionality and behavior of the entity
◦ It is always associated with an entity
Entity/Architecture (contd.)
entity latch is
port (s,r: in bit;
q, nq: out bit);
end latch;
Entity syntax Name of Entity Name of Input Pins
Name of Output pins
Latch
s
r nq
q
Name of architecture
architecture arch1 of latch is
begin
q<= r nor nq;
nq<= s nor q;
end arch1;
Entity name
architecture belongs to
Description of circuit
s
r
nq
q
Architecture syntax
Description types entity entity-name is
port (port1: port1-type; port2: port2-type);
end entity-name;
architecture architecture-name of entity-name is
….signal declaration
begin
…circuit description
end architecture-name
VHDL module can be constructed in three different ways:
◦ Structural
◦ Data flow
◦ Behavioral
Usually, a mixture of all three methods are used in the design of a circuit
Structural Description
Structural description uses text to show how components of a circuit are put together
◦ Similar to a schematic capture approach to designing a circuit
◦ The idea is to combine smaller blocks or predefined components into a larger circuit by describing the way the blocks interact
The structural method is similar to a block diagram
◦ Smaller components are used to make a circuit without knowing what is happening in the block
It can be thought of as a netlist
◦ A netlist is used to describes how components are connected together form a circuit
Structural Syntax
entity latch is
port (s,r: in bit;
q, nq: out bit);
end latch;
architecture structure of latch is
component nor port (a,b: in bit;
c: out bit);
end component;
begin
n1: nor port map (r, nq, q);
n2: nor port map (s=>a, q=>b, nq=>c);
end structure;
Component Pin Specifications
These are used to describe the
input and output pins of the
component nor_gate that will be
used in the architecture section
Mapping pins to component
The command port map is used to
show how the input and output pins
are connected to the component
nor_gate
Architecture description
Describes the architecture is of
the method structure
description and belongs to the
entity latch
Advantages of Structural description
Hierarchy allows for the simplification of the design
Component Reusability allows the re-use of specific components of the design (Latch, Flip-flops, half-adders, etc)
Design Independent allows for replacing and testing components without redesigning the circuit
s
r nq
q
Architecture
Entity
nor
nor
Internal Signals It is also possible to use internal signals to the architecture
These are signals that are only used for connectivity within the
architecture.
This would be used if two components inputs and outputs are
connected together without being connected to any pin described in
the entity
They are defined between the architecture line and the ‘begin’ line
architecture structure of full_adder is
component halfadder
port (a,b: in bit;
carry, sum: out bit);
end component;
signal link : bit;
begin
. . .
End structure;
A
B
C
HalfAdder b
a
carry
sum
HalfAdder b
a
carry
sum link Sum
Carry
Full Adder
Data Flow Description
Data flow describes how the data flows through the circuit, from input to output
It uses built-in functions to describe the flow of data
All commands in Data flow are concurrent (occur at the same time)
Data flow operates in discrete time, when changes occur on the input, it immediately affects the output of the circuit
This method is like the more traditional way of designing a circuit using gates
For some traditional hardware designers, it is easier to use the data flow method, since it deals with the traditional method of designing circuits.
Data Flow Syntax entity latch is
port (s,r: in bit;
q, nq: out bit);
end latch;
architecture dataflow of latch is
begin
q <= r nor nq;
nq <= s nor q;
end dataflow;
Architecture description
Describes the architecture is
of the method data flow
description and belongs to
the entity latch
Logical Data Assignment
Shows that the value of the
output pins are derived from
a logical function of the input
pins
“<=” is used for a signal
assignment, which describes
how the data on the right
hand side of the operator to
the left hand side.
nq
q
s
r
Signal Propagation in Data Flow
design
start : r='0',s='0',q='1',nq='0'
round 1: r='1',s='0',q='1',nq='0', The value '0' is scheduled on q. round 2: r='1',s='0',q='0',nq='0', The value '1' is scheduled on nq. round 3: r='1',s='0',q='0',nq='1', No new events are scheduled.
round 4: r='0',s='0',q='0',nq='1', No new events are scheduled.
nq
q
s
r
Types of delay models
Inertial
◦ Use keyword ‘after’
q<=r nor nq after 1ns;
nq<=s nor q after 1ns;
◦ It may not register short delays
Transport
◦ Use keyword ‘transport’ along with ‘after’
◦ Will absorb ‘short’ pulses
q<=transport r nor nq after 1ns;
nq<=transport s nor q after 1ns;
Concept of Delta delay
A delta (or delta cycle) is essentially an
infinitesimal, but quantized, unit of time
Default signal assignment propagation delay,
if no delay is explicitly specified ◦ E.g. out <= not in -- out will be updated
-- after 1 delta delay
Order in which concurrent statements are
written does not affect simulation output
Because it makes the circuit realistic – it
makes it problematic!!!
Example : V.1
Draw the circuit represented by the
following VHDL statements and write
complete code:
G <= not A and not B and C;
E <= B and D;
D <= A and not C;
J <= G and E;
Circuit Diagram for V.1
A
B
C
J G
E D
VHDL Code for V.1
library ieee;
use ieee.std_logic_1164.all;
entity latch is
port (A,B,C: in bit;
J: out bit);
end latch;
architecture dataflow of latch is
signal D, E, G : bit;
begin
G <= not A and not B and C;
E <= B and D;
D <= A and not C;
J <= G and E;
end dataflow;
Thank You
Time for signal types??? std_logic
bit_vector
std_logic_vector