introduction to vhdl by mr. fazrul faiz zakaria school of computer and communication engineering...
TRANSCRIPT
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Introduction to VHDLBy Mr. Fazrul Faiz ZakariaSchool of Computer and Communication EngineeringUniMAP
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VHDL ???
Very Hard Difficult Language
VHSIC Hardware Description LanguageVery High Speed Integrated Circuits
VHDL is an IEEE standard
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3
Why VHDL?
• HDL is a software solution due to limits in hardware solutions and to:– Increasing design complexity– Increasing cost in time and investment– Increasing knowledge requirement– Inadequacy of other existing languages
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VHDL main Features • Supports the whole design process:
• system level• RT level• logic level• circuit level (to some extent)
• Suitable for specification in• behavioral domain• structural domain
• Precise simulation semantics is associated with the language constructs
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Behavioral Modeling • Only the functionality of the circuit, no structure• Synthesis tool creates correct logic• For the purpose of synthesis as well as simulation
outputsif (shift_left) for (j=0; j<8; j=j+1) #5 out[j]=out[j-1];else for (j=0; j<8; j=j+1) #5 out[j] = out[j+1];
Input
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Structural Modeling • Functionality and structure of the circuit• Call out the specific hardware• For the purpose of synthesis
input1
inputn
output1
outputn
Higher-level Component
Lower-levelComponent1
Lower-levelComponent1
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VHDL Architectures
Behavioral
Structural
Algorithmic
FSM
RTL
Gate
Layout
Abstraction Levels VHDL Architectures
How it works
How it is connected
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Basic VHDL Modeling Structure
Library / Package Declaration
Entity Declaration
Architecture Flow
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LIBRARY / PACKAGE DECLARATIONlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;
library work;use work.my_package.entity_name;use work.my_package.function_name;
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Entity Declaration • Specifies the input and output signals of the entity• modes : in, out, inout, buffer• Format :
Entity name isport (port_name : mode
data_type);End name;
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Entity Declaration (2)
entity reg4 isport ( d0, d1, d2, d3, en, clk : in bit;
q0, q1, q2, q3 : out bit );end entity reg4;
entity name port names port mode (direction)
port typereserved words
punctuation
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Rules for Entity Name• Any alphanumeric character may be used in the name, as well as
the ‘_’ underscore character.• It is not case sensitive• Cannot be a VHDL keyword• Cannot begin with a number, must begin with a letter• Cannot have 2 straight ‘_ _’ underscores• Cannot end with an ‘_’ underscore• Cannot have a blank space
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ARCHITECTURE
• The Internal Aspect of a Design Unit• Can be behavioral (RTL) or structural• Always associated with single entity• Single entity can have multiple architectures
architecture architecture_name of entity_name is{architecture_declarative_part}
begin{architecture_descriptive_part}
end [architecture_name];
architecture architecture_name of entity_name is{architecture_declarative_part}
begin{architecture_descriptive_part}
end [architecture_name];
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Operators
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Architecture : Behavioral Modeling• Architecture body
– describes an implementation of an entity– may be several per entity
• Behavioral architecture– describes the algorithm performed by the
module– contains
• process statements, each containing– sequential statements, including
» signal assignment statements and» wait statements
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Architecture : Behavioral Modeling
architecture behav of reg4 isbegin
process (d0, d1, d2, d3, en, clk) variable stored_d0, stored_d1, stored_d2, stored_d3 : bit;
beginif en = '1' and clk = '1' then
stored_d0 := d0; stored_d1 := d1; stored_d2 := d2; stored_d3 := d3;
end if;q0 <= stored_d0 after 5 ns;
q1 <= stored_d1 after 5 ns; q2 <= stored_d2 after 5 ns; q3 <= stored_d3 after 5 ns;
end process;end behav;
simulates real-world propagation delays.
notice := syntaxused for equating valuesfrom signals...
sensitivity list
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Behavioral Way’s Example
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Behavioral Way’s Example (2)
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Architecture : Structural Modeling
• Structural architecture– implements the module as a composition of
subsystems– contains
• signal declarations, for internal interconnections– the entity ports are also treated as signals
• component instances– instances of previously declared entity/architecture pairs
• port maps in component instances– connect signals to component ports
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Structural way’s example
int_clk
d0
d1
d2
d3
en
clk
q0
q1
q2
q3
bit0
d_latch
d
clk
q
bit1
d_latch
d
clk
q
bit2
d_latch
d
clk
q
bit3
d_latch
d
clk
q
gate
and2
a
b
y
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Structural way cont..• First declare D-latch and and-gate entities and architectures
entity d_latch isport ( d, clk : in bit;
q : out bit );end entity d_latch;
architecture basic of d_latch isbegin
process (clk, d)begin
if clk = ‘1’ thenq <= d
after 2 ns;end if;
end process;end basic;
entity and2 isport ( a, b : in
bit; y : out bit );end entity and2;
architecture basic of and2 isbegin
process (a, b)begin
y <= a and b after 2 ns;
end process ;end basic;
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Structural way...• Declare corresponding components in register architecture body
architecture struct of reg4 iscomponent d_latch
port ( d, clk : in bit; q : out bit );end component;component and2
port ( a, b : in bit; y : out bit );end component;signal int_clk : bit;
...
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Structural way..• Now use them to implement the register
...begin
bit0 : d_latchport map ( d0, int_clk, q0 );
bit1 : d_latchport map ( d1, int_clk, q1 );
bit2 : d_latchport map ( d2, int_clk, q2 );
bit3 : d_latchport map ( d3, int_clk, q3 );
gate : and2port map ( en, clk, int_clk );
end struct;
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Mixed Behavior and Structure• An architecture can contain both behavioral and structural
parts• process statements and component instances
• collectively called concurrent statements• processes can read and assign to signals
• Example: register-transfer-level (RTL) Model• data path described structurally• control section described behaviorally
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Mixed Example
shift_reg
reg
shift_adder
control_section
multiplier multiplicand
product
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Mixed Exampleentity multiplier is
port ( clk, reset : in bit;multiplicand, multiplier : in integer;product : out integer );
end multiplier;
architecture mixed of mulitplier issignal partial_product, full_product : integer;signal arith_control, result_en, mult_bit, mult_load : bit;
beginarith_unit : entity work.shift_adder(behavior)
port map ( addend => multiplicand, augend => full_product,sum => partial_product,add_control => arith_control );
result : entity work.reg(behavior)port map ( d => partial_product, q => full_product,
en => result_en, reset => reset );...
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Mixed Example
…multiplier_sr : entity work.shift_reg(behavior)
port map ( d => multiplier, q => mult_bit,load => mult_load, clk => clk );
product <= full_product;
process (clk, reset)-- variable declarations for control_section-- …
begin-- sequential statements to assign values to control signals-- …
end process;end mixed;
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Concurrent vs Sequential
• Behavioral part for a combinational system divided into 2 categories
• Concurrent assignment statements• Simple signal assignment• Conditional signal assignment (when…else)• Selected signal assignment (with…select)
• Sequential assignment statements• If statement (if…then…else)• Case statement (case…when)• Loop statement (For-Loop & While-Loop)
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Concurrent Assignment Statements
• Defines an interconnected block by assigning values to signals• Executes continuously• Order of statements in a body is not affected
• Eg :signal_name <= expression;
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“when…else” Statements
Architecture beh of dec_norm_we isBeginI0 <= ‘1’ when D = “00” else ‘0’;I1 <= ‘1’ when D = “01” else ‘0’;I2 <= ‘1’ when D = “10” else ‘0’;I3 <= ‘1’ when D = “11” else ‘0’;
End beh;
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“when…else” StatementsEntity dec_we isPort( D : in std_logic_vector(1 downto 0);
I : out std_logic_vector(3 downto 0));End dec_we;
Architecture beh of dec_we isBegin
I <= “0001” when D=“00” else“0010” when D=“01” else“0100” when D=“10” else“1000” when D=“11”;
End beh;
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“with…select” Statements
Architecture beh of dec_sel isBegin
with D select
I <= “0001” when “00”,“0010” when “01”,“0100” when “10”,“1000” when “11”;
End beh;
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Sequential Assignment Statements
• The order of the statements is significant and can affect the semantics of the code
• To differentiate from concurrent assignment, sequential assignment must be separated
• Sequential assignments are enclosed inside a “process statement” to distinguish from concurrent assignments
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“if…then…else” StatementsArchitecture beh of dec_if isBeginprocess (D)begin
if D=“00” thenI <= “0001”;
elsif D=“01” thenI <= “0010”;
elsif D=“10” thenI <= “0100”;
elseI <= “1000”;
end if;end process;
End beh;
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“case…when” StatementsArchitecture beh of dec_cs isBeginprocess (D)begin
case (D) iswhen “00” => I <= “0001”;when “01” => I <= “0010”;when “10” => I <= “0100”;when “11” => I <= “1000”;end case;
end process;End beh;
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Loop StatementsLibrary ieee;Use ieee.std_logic_1164.all;
Entity numbits isPort( D : in std_logic_vector(1 to 3);
count : out integer range 0 to 3);End numbits;
Architecture beh of numbits isBegin
process (D)variable tmp : integer;begin
tmp := 0;for i in 1 to 3 loop
if D(i) = ‘1’ thentmp := tmp + 1;
end if;end loop;count <= tmp;
end process;End beh;
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Mixed Behavioral Statements
• Processes are concurrent• Sequential activity within each process
Nesting of statements :• Concurrent statements in a concurrent statement• Sequential statements in a concurrent statement• Sequential statements in a sequential statement
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Basic Design Methodology
Requirements
SimulateRTL Model
Gate-levelModel
Synthesize
Simulate Test Bench
ASIC or FPGA Place & Route
TimingModel Simulate