introduction to programmable logic devices and fpgas edward freeman stfc technology department...
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Introduction to Programmable Logic Devices and FPGAs
Edward Freeman
STFC Technology Department
Detector & Electronics Division
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)[email protected]
Lecture Outline
Introduction Why Programmable Logic Devices and FPGAs
FPGA Field Programmable Gate Array Architecture
Design Flow Hardware Description Languages Design Tools
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)[email protected]
Programmable Logic is a Key Underlying Technology for PP Experiments.
First-Level and High-Level Triggering
Data Transport (Networks)
Computers interacting with Hardware (Networks)
Silicon Trackers (Millions of Data Channels)
Commercial Devices. Developments driven by Industry.
Telecomms, Gaming, Aerospace, Automotive, Set-top boxes….
Why Programmable Logic Devices and FPGAs
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)[email protected]
CMS DAQ/Trigger Architectures
CMS
“Telecoms Network” ~ 1 Tbps
Fully custom PP ASICs
CPUs Commodity PCs
Programmable LogicDIGITAL
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)[email protected]
Particle Physics Electronics
Special Dedicated Logic Functions (not possible in CPUs) Ultra Fast Trigger Systems (Trigger Algorithms) Clock Accurate
Timing Massively Parallel Data Processing (Silicon Trackers with Millions of
Channels)
Custom DesignedPrinted Circuit Boards PCBs.
CommercialProgrammable LogicDevices, FPGAs
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)[email protected]
Lecture Outline
Introduction Why Programmable Logic Devices and FPGAs
FPGA Field Programmable Gate Array Architecture
Design Flow Hardware Description Languages Design Tools
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)[email protected]
Digital Logic
Logic Gates
Transistor Switches
< 40 nm ! $$$
MOORE’S LAW
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)[email protected]
Digital Logic
Black BoxSUM of PRODUCTS
Truth Table(Look Up Table LUT)
Digital Logic Function
3 Inputs
Product AND (&)Sum OR (|)
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)[email protected]
Digital Logic
Black BoxSUM of PRODUCTS
Truth Table(Look Up Table LUT)
Digital Logic Function
3 Inputs
Product AND (&)Sum OR (|)
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)[email protected]
Logic Blocks
Logic Functions implemented in Look Up Table LUTs. Flip-Flops. Registers. Clocked Storage elements. Multiplexers (select 1 of N inputs)
16-bit SR
flip-flop
clock
muxy
qe
abcd
16x1 RAM
4-inputLUT
clock enable
set/reset
FPGA Fabric Logic Block
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)[email protected]
Look Up Tables LUTs LUT contains Memory Cells to implement small logic functions Each cell holds ‘0’ or ‘1’ . Programmed with outputs of Truth Table Inputs select content of one of the cells as output Configured by re-programmable SRAM memory cells
16-bit SR
flip-flop
clock
muxy
qe
abcd
16x1 RAM
4-inputLUT
clock enable
set/reset
3 Inputs LUT -> 8 Memory Cells
SRAM
Static Random Access MemorySRAM cells
SRAM
3 – 6 Inputs
Multiplexer MUX
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)[email protected]
Logic Blocks
Larger Logic Functions built up by connecting many Logic Blocks together
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)[email protected]
Logic Blocks
Larger Logic Functions built up by connecting many Logic Blocks together
Determined by SRAM cells
SRAM SRAM cells
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)[email protected]
Sequential Circuits
RegisterCLOCK
New Output every clock edge
Shift Registers,Pipelines,Finite State Machines…
Combinational Logic (Larger circuits difficult to predict) Synchronous Logic driven by a CLOCK Registers, Flip Flops (Memory)
Clock Rate determines speed
Comb Logic Must meet Timing=> Predictable circuits
Inputs
Intermediate
EDGES
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)[email protected]
Clocked Logic
Registers on outputs. CLOCKED storage elements. Synchronous FPGA Logic Design, Pipelined Logic. FPGA Fabric Pulse from Global Clock (e.g. LHC BX frequency)
16-bit SR
flip-flop
clock
muxy
qe
abcd
16x1 RAM
4-inputLUT
clock enable
set/reset
FPGA Fabric
Clock from Outside world (eg LHC bunch frequency)
Special Routing for Clocks
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)[email protected]
Field Programmable Gate Arrays FPGA
Field Programmable Gate Array ‘Simple’ Programmable Logic Blocks Massive Fabric of Programmable Interconnects Standard CMOS Integrated Circuit fabrication process as for
SRAM memory chips (Moore’s Law) “Hard blocks” for complex high speed functions
Huge Density of Logic Block ‘Islands’
1,000 … 100,000’s
in a ‘Sea’ of Interconnects
FPGA Architecture
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)[email protected]
Field Programmable Gate Arrays FPGA
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)[email protected]
Input Output I/O Getting data in and out
01
54
6
7
3
2
General-purpose I/Obanks 0 through 7
FPGA
Differential pairs
Transceiver block
Up to > 1,000 I/O “pins” (several 100 MHz)
Special I/O SERIALISERS~ 10 Gbps transfer rates
Optical TRx
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)[email protected]
Lecture Outline
Introduction Why Programmable Logic Devices and FPGAs
FPGA Field Programmable Gate Array Architecture
Design Flow Hardware Description Languages Design Tools
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)[email protected]
Designing Logic with FPGAs
Design Capture. High level Description of Logic Design.
Graphical descriptions Hardware Description Language (Textual)
Graphical State Diagram
Graphical Flowchart
When clock rises If (s == 0) then y = (a & b) | c; else y = c & !(d ^ e);
Textual HDL
Top-levelblock-levelschematic
Block-level schematic
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)[email protected]
Hardware Description Languages
Language describing hardware (Engineers call it FIRMWARE) Doesn’t behave like “normal” programming language ‘C/C++’ Describe Logic as collection of Processes operating in
Parallel Language Constructs for Synchronous Logic
Compiler (Synthesis) Tools recognise certain code constructs and generates appropriate logic
Not all constructs can be implemented in FPGA!
2 Popular languages are VHDL , VERILOG Easy to start learning… Hard to master!
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)[email protected]
VHDLENTITY Declaration Input Output to Module (STD LOGIC)
SIGNALS Declaration WIRES
CONCURRENT ASSIGNMENTS
CONDITIONAL ASSIGNMENTS => MULTIPLEXERS
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)[email protected]
VHDL
COMPONENT Declaration
PROCESS Declaration. CONCURRENT functions. Synchronous Logic.
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)[email protected]
Designing Logic with FPGAs High level Description of Logic Design
Hardware Description Language (Textual)
Compile (Synthesis) into NETLIST. Boolean Logic Gates.
Target FPGA Device Mapping Routing
Bit File for FPGA
Commercial CAE Tools(Complex & Expensive)
Logic Simulation
Gate-levelnetlist
BEGIN CIRCUIT=TEST INPUT SET_A, SET-B, DATA, CLOCK, CLEAR_A, CLEAR_B; OUTPUT Q, N_Q; WIRE SET, N_DATA, CLEAR;
GATE G1=NAND (IN1=SET_A, IN2=SET_B, OUT1=SET); GATE G2=NOT (IN1=DATA, OUT1=N_DATA); GATE G3=OR (IN1=CLEAR_A, IN2=CLEAR_B, OUT1=CLEAR); GATE G4=DFF (IN1=SET, IN2=N_DATA, IN3=CLOCK, IN4=CLEAR, OUT1=Q, OUT2=N_Q);
END CIRCUIT=TEST;
Fully-routed physical(CLB-level) netlist
Schematiccapture
Mapping
Packing
Place-and-Route Timing analysis
and timing report
Gate-level netlistfor simulation
SDF (timing info)for simulation
Design Flow
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)[email protected]
Configuring an FPGA Millions of SRAM cells holding LUTs and Interconnect Routing Volatile Memory. Lose configuration when board power is
turned off. Keep Bit Pattern describing the SRAM cells in non-Volatile
Memory e.g. PROM or Digital Camera card Configuration takes ~ secs
Configuration data in
Configuration data out
= I/O pin/pad
= SRAM cell
SRAM
JTAG Testing
JTAG Port
ProgrammingBit File
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Not just logic
Hard blocks (built into the FPGA) High speed serialises (1Gb, 10Gb, hyper-transport ect) Complex multiplier units (DSP) Embedded processors (PPC404, PPC440, ARM Cortex-A9) PCI express (Gen 2) Multi clock multi phase clock managers. Built in ultra fast RAMs Programmable IO. (LVDS, SSTL and 100’s of others)
Plus the millions of gates of programmable logic from the FPGA fabric its self.
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Serialisers
A number of types and speeds.
We are currently supporting projects with multi 1Gb Ethernet readout.
10Gb is working in the lab and 1st boards are in testing now PCI express endpoint (Gen 1) Camera link
[email protected] PCI express
Can use off the self switches to make backend system
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Embedded processors and multipliers
Processors
Fast image processing and control loop feedback in C code
software. (20KHz image rate) Large ping pong (image) frame buffer System monitoring, house keeping, reporting and logging Can also have an army of small “soft” processor cores
Multipliers (DSP blocks) Complex FFT for machine frequency control.
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Block RAMs and Clock managers Block RAMs
Small high speed buffers Look up tables and scratch pads. FIFO’s to help adjust data rates between processing blocks.
Clock Managers
Generate different frequency's from a reference clock. Generate phase shits of the clocks. Distribute the clocks to the different areas of the FPGAs
(Not of much interest but nothing works without them)
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Other technology you can add to an FPGA Memory interfaces
DRAM, DDR, QDR, SRAM, ZBTRAM ect. Industry standard memory modules DDR2, DDR3,
Maths functions Floating point units Complex Multiplier Integer Add, Sub, Multiply, Div Digital signal processing functions FFT, FIR, reed-solomon
encoders Or any other digital system that can be described with custom
logic.
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)[email protected]
Field Programmable Gate Arrays FPGA
Large Complex Functions Re-Programmability, Flexibility.
Massively Parallel Architecture Processing many channels simultaneously cf MicroProcessor
Fast Turnaround Designs Standard IC Manufacturing Processes. Moore’s Law Mass produced. Inexpensive. Many variants. Sizes. Features.
PP Not Radiation Hard Power Hungry No Analogue
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)[email protected]
FPGA Trends State of Art is 32nm on 300 mm wafers Top of range >500,000 Logic Blocks >1,000 pins (Fine Pitched BGA)
Logic Block cost ~ 1$ in 1990 Today < 0.1 cent
Problems Power. Leakage currents. Design Gap
CAE Tools
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The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)[email protected]
Summary
FPGA Field Programmable Gate Arrays Architecture
Design Flow Hardware Description Languages Design Tools Exploit industry hardware and protocols
Importance for Particle Physics Experiments
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)[email protected]
References and contacts
The Design Warrior’s Guide to FPGAs Clive Maxfield, Newnes Elsevier
FPGA manufacturer web sites www.xilinx.com www.altera.com
FPGA Online www.pldesignline.com www.fpgajournal.com www.doulos.com
Technology Rob Halsall – [email protected] John Coughlan – [email protected]