Introduction to VLSI and SOC Design

Introduction to Full-Custom Circuit Design with HSPICE and Laker

Course Instructor: Prof. Lan-Da Van

T.A.: Tsung-Che Lu

Department of Computer Science

National Chiao Tung University

Taiwan, R.O.C.

Fall, 2009

VLSI Design

Environment Setup

Tool

Pietty

http://ntu.csie.org/~piaip/pietty

Xming

http://sourceforge.net/projects/xming

VLSI Design

Environment Setup (Xming)

Open Xming

No Access Control

VLSI Design

Environment Setup (Pietty)

• Server: hwlab01.cs.nctu.edu.tw ~ hwlab08.cs.nctu.edu.tw

• Password could be changed on hwlab01 only.

Your IP:0

Introduction to VLSI and SOC Design

Simulation with HSPICE

VLSI Design

A Typical SPICE Script* cmos inverter.include „mosistsmc180.sp‟

* sub circuit component netlist.subckt inv in out gnd vddma out in gnd gnd NMOS L=0.18u W=0.36umb out in vdd vdd PMOS L=0.18u W=0.72u.ends

* voltage sourceX1 in out gnd vdd invv1 vdd 0 1.8Vv2 gnd 0 0Vv3 in 0 pulse (0 1.8 0.3ns 0.01ns 0.01ns 0.5ns 1ns)

* simulation environment.option post.tran 0.05ns 3ns.meas tran td1 trig v(in) val=0.9 rise=1 targ v(out) val=0.9 fall=1.meas tran td2 trig v(in) val=0.9 fall=1 targ v(out) val=0.9 rise=1

.end

Specification Measurement

Transistor Type

Model File VDD

GND

in outPart 1

Part 2

Part 3

Annotation(with * start)

End of the script

VLSI Design

Basic Syntax in HSPICE (1/2)

• MOS Transistor:• ma out in gnd gnd NMOS L=0.18u W=0.36u• Mx (drain) (gate) (source) (body) (Type of MOST) + L=(length) W=(width)

• Capacitor: C1 1 0 5p : There‟s a 5pF capacitor C1between node 1 & node 0

• Resistor: R1 2 0 5k : There‟s a 5k(ohm) resistor R1between node 2 & node 0

• DC Voltage Source• V1 VDD 0 1.8V : There‟s a 1.8V voltage source V1

between node VDD & node 0• Notice:

• Node 0 is considered as GROUND in SPICE simulation.• Never use a node name with numbers in the front part.

(Ex: 2P, 3A)

VLSI Design

Basic Syntax in HSPICE (2/2)

• Subcircuit Syntax:

• This is a sub-circuit called inv which has 4 nodes called in , out , gnd and vdd

• Subcircuit Calls:

• X1 in out gnd vdd inv

A subcircuit X1 is called by netlist and its type is inv

.subckt inv in out gnd vddma out in gnd gnd NMOS L=0.18u W=0.36umb out in vdd vdd PMOS L=0.18u W=0.72u

.ends

VLSI Design

Analysis Type

• Transient Analysis:

• .tran 0.05ns 3ns

• Above syntax will ask SPICE to simulate the circuit‟s waveform from 0ns to 3ns with a interval of 0.05ns.

• DC Analysis:

• .dc vds 0 1.8 0.05

• Above syntax will ask SPICE to simulate the circuit‟s DC operating point as the variable vds changing from 0to 1.8 with a interval of 0.05.

VLSI Design

Pulse Source Function

Figure Source: 王朝琴, SPICE Training Manual, CIC, July, 2005

VLSI Design

Piecewise Linear Function

Figure Source: 王朝琴, SPICE Training Manual, CIC, July, 2005

VLSI Design

MEASURE: Application Examples

Figure Source: 王朝琴, SPICE Training Manual, CIC, July, 2005

VLSI Design

Run HSPICE

Job Concluded

• Command: hspice –i xxx.sp -o xxx.lis

• If “Job Aborted”, see xxx.lis file for detailed imformation.

• The measured specifications and power consumption will be listed in .lis file.

• The simulated waveform will be saved in .tr0 file.

VLSI Design

.meas Output Format in .lis file

****** transient analysis tnom= 25.000 temp= 25.000 ******

td1= 6.9407E-12 targ= 3.1194E-10 trig= 3.0500E-10td2= 3.1324E-11 targ= 8.4632E-10 trig= 8.1500E-10

***** job concluded

VLSI Design

Waveform Viewer - nWave (1/3)

• Command: nWave &

.tr0

File

Open…

*.*

VLSI Design

Waveform Viewer - nWave (2/3)

Get Signals

Choose input & output node

VLSI Design

Waveform Viewer - nWave (3/3)

Press 100% button

Introduction to VLSI and SOC Design

Layout with Laker

VLSI Design

CMOS Cross-section

Figure Source:

F. Maloberti, “Analog Design for CMOS VLSI Systems”

N. H. E Weste and D. Harris, ”CMOS VLSI Design”

VLSI Design

NMOS

Figure Source:http://www.ece.gatech.edu/research/labs/vc/theory/devchar.html

Contact

PIMP

Poly

Diffusion

NIMP

Metal1

Length (L)

Width (W)

VLSI Design

PMOS

Figure Source:http://www.ece.gatech.edu/research/labs/vc/theory/devchar.html

NIMP

PIMP

NWell

Contact Metal1

Diffusion

Poly

VLSI Design

Laker - Create a New Library (1/1)

LibraryNew…

Create a new library

VLSI Design

Laker - Create a New Library (2/2)

Enter library name

/cad/CBDLIB/cic18/laker/laker.tf

VLSI Design

Laker - Create a New Cell

Cell New…

VLSI Design

Laker – Change Grid

Change Gird…

0.01

VLSI Design

Laker - Hotkeys

r: rectangle

u: undo

k: ruler

Shift + k: remove

rulers

Delete: delete shapes

or lines

Esc: back to

cmd(selecting)

Shift + p: polygon

Ctrl + z: zoom in

Shift + z: zoom out

f: fit design

c: copy

m: move

p: path

l: text

cmd(selecting) + ctrl

+ a: select all

VLSI Design

Inverter (1/3)

Figure Source: http://cnx.org/content/m1029/latest/

Schematic Stick Diagram

VDD

GND

Vin Vout

P-diff

N-diff

VLSI Design

Inverter (2/3)

Figure Source: http://larc.ee.nthu.edu.tw/~hp/

VLSI Design

Inverter (3/3)

Figure Source: http://larc.ee.nthu.edu.tw/~hp/

VLSI Design

0.18um 1P6M Process Layers

Diffusion

N-Well

P ImplantPoly

Metal 1VIA

CONT

N Implant

VLSI Design

Verification and Extractionwith Calibre

DRC (Design Rule Check)

Check for design rule violations

LVS (Layout versus Schematic Check)

Check for inconsistencies between the physical layout and

the schematic

PEX (Parasitic Extraction) / LPE (Layout

Parameter Extraction)

Extract layout parameters, such as transistors, parasitic

capacitor, and parasitic resistors

Extracted netlist

VLSI Design

DRC with Calibre (1/3)

Verify Calibre

Run DRC…

/cad/CBDLIB/cic18/calibre/Calibre_DRC/rule.drc

VLSI Design

DRC with Calibre (2/3)

Must be selected!

VLSI Design

DRC with Calibre (3/3)

Total Errors Count

Double Click

Detailed Information about errors

The errors of DRC must be modified for error free!

Highlight on your layout

Clear Highlight

VLSI Design

Lab Requirement

Copy is strictly prohibited, and doing the assigned

labs on your own is required. Otherwise, you will get

zero score for no excuse.

Please notice the lately delivered reports will not be

accepted after due date.

Detailed information and report format will be

announced on the course forum/website.

The designate model file (mosistsmc180.sp) can be

downloaded from “SPICE and Verilog code” link in

textbook’s website.

http://www.cmosvlsi.com/

The course forum is available now. Any question/

discussion can be posted on board or email TAs.

http://viplab.cs.nctu.edu.tw/forums/index.php