introduction to cortexm3

8/18/2019 Introduction to CortexM3

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Introduction to Cortex M3


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Cortex M3 Features

• The Cortex™-M3 is a

– 32-bit microprocessor.

– It has a 32-bit data path,

– a 32-bit register bank, – and 32-bit memory interaces

– The processor has a !ar"ard architecture.

– an optiona# Memory $rotection %nit &M$%'

– (oth #itt#e endian and big endian memorysystems are supported.

– Inc#udes interna# debugging components.


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Cortex M3 Features


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Cortex M3 -)egisters


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• R0–R12: General-Purpose Registers – )*+)2 are 32-bit genera#-purpose registers or data

operations.

– ome -bit Thumb/ instructions can on#y access a subset

o these registers o0 registers, )*+)1'.• R13: Stack Pointers

– The Cortex-M3 contains t0o stack pointers &)3'. They arebanked so that on#y one is "isib#e at a time.

– The t0o stack pointers are as o##o0s•

Main Stack Pointer (MSP): The default stack pointer, used by theoperating system (OS) kernel and exception hand#ers

• Process Stack Pointer (PSP): Used by user application code

– The #o0est 2 bits o the stack pointers are a#0ays *, 0hichmeans they are a#0ays 0ord a#igned.


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• R14: The Link Register

– hen a subroutine is ca##ed, the return address is stored in the #inkregister.

• R15: The Progra !ounter – The program counter is the current program address. This register

can be 0ritten to contro# the program 4o0.

• Special Registers – The Cortex-M3 processor a#so has a number o specia# registers.

– They are as o##o0s• $rogram tatus registers &$)s'

• Interrupt Mask registers &$)IM56, F5%7TM56, and (58$)I'• Contro# register &C9:T)97'

– These registers ha"e specia# unctions and can be accessed on#y byspecia# instructions. They cannot be used or norma# dataprocessing .


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Cortex M3 + 9perationModes

• The Cortex-M3 processor has t0o modes and t0o pri"i#ege #e"e#s.

• The operation modes &thread mode and hand#er mode' determine0hether the processor is running a norma# program or running anexception hand#er #ike an interrupt hand#er or system exceptionhand#er.

• The pri"i#ege #e"e#s&pri"i#eged #e"e# and user #e"e#' pro"ide amechanism or saeguarding memory accesses to critica# regionsas 0e## as pro"iding a basic security mode#.

• The separation o pri"i#ege and user #e"e#s impro"es systemre#iabi#ity by pre"enting system con;guration registers rom being

accessed or changed by some untrusted programs. I• an M$% is a"ai#ab#e, it can be used in con


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Cortex M3 + 9perationModes


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Cortex M3-:=IC

• The "uilt -#n $este% &ectore% #nterrupt!ontroller – The Cortex-M3 processor inc#udes an interrupt

contro##er ca##ed the :ested =ectored InterruptContro##er &:=IC'.

– It is c#ose#y coup#ed to the processor core andpro"ides a number o eatures as o##o0s• :ested interrupt support

• =ectored interrupt support• >ynamic priority changes support

• )eduction o interrupt #atency

• Interrupt masking


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Cortex M3-:=IC

$este% #nterrupt Support

• The :=IC pro"ides nested interrupt support.

• 5## the externa# interrupts and most o the system exceptions can beprogrammed to di?erent priority #e"e#s.

• hen an interrupt occurs, the :=IC compares the priority o this interrupt

to the current running priority #e"e#.• I the priority o the ne0 interrupt is higher than the current #e"e#, the

interrupt hand#er o the ne0 interrupt 0i## o"erride the current runningtask.

• &ectore% #nterrupt Support

• The Cortex-M3 processor has "ectored interrupt support.

• hen an interrupt is accepted, the starting address o the interruptser"ice routine &I)' is #ocated rom a "ector tab#e in memory.

• There is no need to use sot0are to determine and branch to the startingaddress o the I). Thus, it takes #ess time to process the interruptre@uest.


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Cortex M3-:=IC

• '(naic Priorit( !hanges Support

– $riority #e"e#s o interrupts can be changed by sot0are during runtime.

• Re%uction o) #nterrupt Latenc( – The Cortex-M3 processor a#so inc#udes a number o ad"anced

eatures to #o0er the interrupt #atency.

– These inc#ude automatic sa"ing and restoring some registercontents, reducing de#ay in s0itching rom one I) to another, andhand#ing o #ate arri"a# interrupts.

• #nterrupt *asking

– Interrupts and system exceptions can be masked based on theirpriority #e"e# or masked comp#ete#y using the interrupt maskingregisters (58$)I, $)IM56, and F5%7TM56.

– They can be used to ensure that time-critica# tasks can be ;nishedon time 0ithout being interrupted.


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Cortex M3 -Memory Map


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Cortex M3 -Memory Map

• The Cortex-M3 has a prede;ned memorymap.

• This a##o0s the bui#t-in periphera#s, such as

the interrupt contro##er and the debugcomponents, to be accessed by simp#ememory access instructions.

• Thus, most system eatures are accessib#e

in C program code.• 9"era##, the A B( memory space can be

di"ided into ranges as sho0n in Figure.


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Cortex M3- "us #nter)ace

• There are se"era# bus interaces on the Cortex-M3 processor.

• They a##o0 the Cortex-M3 to carry instruction etches anddata accesses at the same time.

• The main bus interaces are as o##o0s –

Code memory buses• The code memory region access is carried out on the code memory buses,

0hich physica##y consist o t0o buses, one ca##ed #-!o%e and other ca##ed '-!o%e.

– ystem bus• The system bus is used to access memory and periphera#s. This pro"ides

access to the tatic )andom 5ccess Memory &)5M', periphera#s, externa#

)5M, externa# de"ices, and part o the system #e"e# memory regions.

– $ri"ate periphera# bus• The pri"ate periphera# bus pro"ides access to a part o the system-#e"e#

memory dedicated to pri"ate periphera#s, such as debugging components.

introduction to cortexm3

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