introduction to asic

8/22/2019 Introduction to Asic

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INTRODUCTION TO ASIC - Part-2

Field Programmable Gate Arrays:

None of the layers is customized.

Basic logic cells and interconnect can be programmed.

Basic cells can be SRAM based, Flash Memory based or fuse-based (One timeprogrammable)

Advantages & Disadvantages of FPGA:

Advantages:

A shorter time to market

Ability to re-program in the field to fix bugs

Lower non-recurring engineering costs

For smaller designs and/or lower production volumes, FPGAs are morecost effectivethan an ASIC design.

Disadvantages:

Usually slower than their ASIC & Cannot handle a complex design
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Draw more power.

No layers customized (standard devices) & Can be used for Digital only

Complex Programmable Logic Device (CPLD):

A CPLD is a programmable logic device with complexity between that of PALs andFPGAs, and architectural features of both.

No customized mask layers or logic cells.

A single large block of interconnects.

Macro-cells consist of programmable array logic followed by a flip flop or latch.

A CPLD has non-volatile configuration memory like PALs.

Unlike many FPGAs, an external configuration ROM isn't required

CPLD can function immediately on system start-up.

Features in common with FPGAs:

Large number of gates available.

Some provisions for logic more flexible than sum-of-product expressions, includingcomplicated feedback paths between macro cells, and specialized logic.

The most noticeable difference between a large CPLD and a small FPGA is thepresence of on-chip non-volatile memory in the CPLD

As CPLDs and FPGAs become more advanced the differences between the two devicetypes will continue to blur
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Comparison:

Advantages of ASIC:

Reducing the size of your finished product, i.e. consumes reduced area compared totheir counterparts.

Allowing you to include greater functionality.

Assembly cost is reduced and reliability is increased.

Removes the need for in-house testing of a substantial part of the circuit.

Power consumption of a single chip is normally far less.

Design security.

ASIC has more speed compared to CPLD and FPGA.

Disadvantages of ASIC:

Requires a higher level of commitment both financially and technically at a relativelyearly stage in the development of a project.

Level of risk is too much high at every stage of chip Designing.

High Non Recurrent Engineering (NRE) cost.

Much higher skill requirement on the part of the design team.
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The cost of development and Time to market is more for ASIC.

Packaging of ASIC:

The various types of IC Packaging are:

Flip Chip, Wire Bond, Multi chip Module (MCM), Chip Scale Package (CSP), Quad FlatPacks (QFP), Stacked Die Packages, Ball Grid Array Packages (BGA), Land Grid Array(LGA), SiP, Quad No-lead Packages (QFN), Plastic Leaded Chip Carriers (PLCC), SO,SOT, TSOP, WLP.

The metric to select the packaging are:

Cost (Should be Less) & Reliability

Form factor (Packing Density)

Performance {Simultaneous Switching Noise, Signal Propagation, Powerground distribution}

Thermal (Efficient heat removal) and Electrical (Low parasitic) Enhanced

Wire Bond:

Flexible, Cost effective & Suitable for limited number of padsOnly periphery of chip available for IO connections
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Mechanical bonding of one pin at a time (sequential)Cooling from back of chipHigh inductance (~1nH) & Capacitance (~1pF)

Challenges involved in Wire bonding:

Reduction in Wire Diameter

Wire length Increase

Loop height minimum achievable

Wire Bond pitch reduction (pitch-range is of 60u)

Pad Size Opening reduction & BGA Package total height reduction

Flip Chip (Controlled Collapse Chip Connection, or C4):

The final wafer processing step deposits solder bumps on the chip pads, which areused to connect directly to the associated external circuitry.
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Does not require any wire bonds

Good Power and Ground Distribution possible.

With the Area array more I/O density is possible.

Low stress over active area.

Targeted for High device speed.

Low Inductance (~0.1nH) & Capacitance (~0.5pF)

Costlier.

Production area array pitch around 178 micron.

Whole chip area available for IO connections

Automatic alignment

One step process (parallel)

Cooling via balls (front) and back if required

Thermal matching between chip and substrate required

Future Technologies:

WLBI (Wafer Level Burn in)

Optical Interconnects

Multiple Die-Stacking

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INTRODUCTION TO ASIC - Part-1Evolution of VLSI:
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What is an ASIC?

Application-specific integrated circuit

Customized for a particular use customized for a particular use, rather than

intended for general-purpose use

For example, a chip designed solely to run a cell phone is an ASIC. [Not

ASICs: General-purpose processors, memory chips and other standard

components]

Dedicated to single function, or limited range of functions.

A typical ASIC is a circuit, where functions are designed by the customer

andlayout and the fabrication is done by the silicon vendor.

Designers of digital ASICs use a hardware description language (HDL), such

as Verilog or VHDL, to describe the functionality of ASICs.

The maximum complexity (and hence functionality) possible in an ASIC has

grown from 5,000 gates to over 100 million

Types of ASIC:

1. Full Custom ASICs
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2. Standard Cell Based ASICs (CBIC)

3. Gate Array Based ASICs

3. a. Channeled Gate Array

3. b. Channel-less Gate Array

3. c. Embedded Gate Array

4. Programmable Logic Devices

4. a. Field Programmable Gate Arrays

4. b. Complex PLD (CPLD)

Full Custom ASIC:

In a full-custom ASIC, an engineer designs some or all of the logic

cells,circuits, or layout specifically for one ASIC. This means the designer

abandons the approach of using pre-tested and pre-characterized cells for

all or part of that design.

It makes sense to take this approach only if there are no suitable existing cell

libraries available that can be used for the entire design. This might be

because existing cell libraries are not fast enough, or the logic cells are not

small enough or consume too much power.

Hand drawn geometry and all layers are customized.

Can be used for both, Digital and analog.

High density, High performance & Long design time.

Standard Cell Based ASIC (CBIC):


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Acell-based ASIC (cell-based IC, or CBIC uses pre-designed logic cells

(AND gates, OR gates, multiplexers, and flip-flops, for example) known

as standard cells.

The advantage of CBICs is that designers save time, money, and reduce riskby using a pre-designed, Pre-tested, and pre-characterizedstandard-cell

library

Standard cells organized in rows (and, or, flip-flops, etc.)

Cells made as full custom by vendor (not user).

Medium- high density, Medium-high performance & Reasonable design

time.

All layers are customized.

Standard Cell:
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Cells are configured in rows and have constant height and variable width.

Each cell is optimized for an efficient implementation.

Gate Array:

A gate array chip contains prefabricated adjacent rows of PMOS and NMOS

transistors.

The gate array is configured by the interconnect structure.

Predefined transistors connected via metal

Only metal layers customized

Fixed array sizes (normally 5-10 different)

Digital cells in library (and, or, flip-flops, etc.)

Simulation at gate level (digital)

Medium density & Medium performance

Reasonable design time

Channeled Gate Array:
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Only the interconnect is customized.

The interconnect uses spaces between rows of base cells

Channel-less Gate Array (Sea of Gates):


Cells are connected via unused transistors

Embedded Gate Array:
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Custom Blocks can be embedded.
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