Introduction of M2M NetworksIntroduction of M2M NetworksHeterogeneous Sensor System  on Chip

Chih Ting LinChih‐Ting LinYi‐Chang Lu

Graduate Institute of Electronics EngineeringGraduate Institute of Electronics EngineeringNational Taiwan University

Billions of Connected DevicesBillions of Connected Devices

Applications of M2M Systems

Infrastructures of M2M System

OSI 7‐Layer Network Modely• Open System Interconnection model

– A reference model developed by ISO at 1984A reference model developed by ISO at 1984– Layer 7: Application layer

• Defines interface to user processes for communication and data transfer in networktransfer in network

– Layer 6: Presentation layer• Masks the differences of data formats between dissimilar systems

L 5 S i L– Layer 5: Session Layer• Manages user sessions and dialogues

– Layer 4: Transport Layer• Manages end‐to‐end message delivery in network

– Layer 3: Network Layer• Determines how data are transferred between network devices

– Layer 2: Data Link Layer• Defines procedures for operating the communication links

– Layer 1: Physical Layer– Layer 1: Physical Layer• Defines physical means of sending data over network devices

M2M Network LayersM2M Network Layers

Sensor NetworksSensor Networks• Sensor network systemsy

– A system consisting of a collective of networked sensor nodes designed to communicate to each other

– Integrate sensor, micro processor, and communication capabilities

– Sense environment acquire information and handle– Sense environment, acquire information , and handle message

– Limited resourcesS 範圍Sensor 範圍

網路、衛星或其他傳輸媒介

Previous Sensor Network  Applicationspp• UC Berkeley – Habitant Monitoring 2002

– Develop a habitat monitoring kit– Monitor sensitive wildlife and habitatsE i th i t i d di ti– Engage in the non‐intrusive and non‐disruptive method

http://www.greatduckisland.net/

Previous Sensor Network  Applications

• UC Berkeley ‐ Firebug 2003 

pp

y g– Install GPS system with sensor network– Enable temperature monitoring with coordination – Monitor wildfire in forest

http://firebug.sourceforge.net/

Previous Sensor Network  Applications• UC Berkeley ‐ Structural Health Monitoring of the Golden Gate Bridge 2005

pp

g– Measure ambient structural vibration– Install 64 nodes on GGB– Collect vibrations synchronously at 1kHz rate

http:// www.eecs.berkeley.edu/~binetude/ggb/

Previous Sensor Network  Applications• Duke Univ. ‐ Observation of Ecosystem Processes

pp

– Deploy dense spatial‐temporal sensing of environments Build awareness of the benefits of the technology– Build awareness of the benefits of the technology 

http://www.nicholas.duke.edu/people/faculty/clark/pages/research.html

Previous Sensor Network  Applications• NTU (Prof. 李世光)‐ Structural Monitoring 2002

Founded by勞委會勞工安全衛生研究所

pp

– Founded by 勞委會勞工安全衛生研究所– Monitor the safety of 建築鷹架

strain Up and low limit of admission strain

2

3

5

4

1

Previous Sensor Network  Applications• NTUT (Prof. 李仁貴) ‐ Semiconductor Fab

pp

Monitoring– Monitor the equipment vibration

Previous Sensor Network  Applications• NTU (Prof. 黃寶儀) ‐ BL‐Live: The Elevator Report

k th t t f th l t i th b ildi

pp

– know the status of the elevators in the building– Establish mid/large‐scale sensor network testbed for everyday useeveryday use

Sensor Network

Previous Sensor Network  Applications• CGU (Prof. 林仲志) ‐無線感測網路居家型退化偵測設備之研發

pp

化偵測設備之研發– Measure reaction force and motion balance of elderselders

Previous Sensor Network  Applications• NTU (Prof. 江昭皚) ‐東方果實蠅生態監測與預警系統

pp

預警系統– Measure the population of flies

Basic Infrastructure of Sensor Node• A sensor node in WSN

– Microprocessor p– Data storage– Sensor

i Microprocessor Transceiver– RF transceiver– Energy source

Microprocessorunit

Transceiverunit

Power Supplyunitunitunitunit

Sensor – light and temperature

Sensor Network Design ConsiderationSensor Network Design Consideration• Consideration of sensor network developments– Application EnvironmentApplication Environment– Transmission Media– Scalability– Scalability– Sensor Network TopologyH d C t i t– Hardware Constraints

– Power Consumption– Fault Tolerance– Sensor Costs

Sensor Node Design ConsiderationSensor Node Design Consideration

• The requirement of sensor networks– Robustness, effectiveness, low cost, and small size

• Sensing unit– Passive/active sensors– Power consumption

• Microprocessor unit– Power saving– Cost/performance C i ti it• Communication unit– IEEE 802.15.4 (low data rate wireless PAN)

P i– Power saving

M2M Physical Device: Smart Sensor NodeM2M Physical Device: Smart Sensor Node• Sensors bridge physical events to systems– Networking concept is rarely considered in traditional sensor designs

E h i i l• Emphasize single sensor characterization

• Concentrate at different kind of sensing performance

• Stress the network latency• Stress the network latency as the complexity sensing scope increases

MicrophoneMicrophone• Measure the sound

Accelerometer

• Measure the accelerationeasu e t e acce e at o

GyroscopeGyroscope

M th• Measure the orientation

Pressure SensorPressure Sensor

• Measure the pressure

Optical SwitchOptical Switch• Change the light pathChange the light path

Turbine EngineTurbine Engine

• Generate the air thrust

Biomolecular Detector

• Measure the biomarker

M2M Physical Device: Smart Sensor NodeS d i i M2M k• Smart sensor node is necessary in M2M network– Promote scopes of sensors and systems– Improve system performance– Lower sensor manufacturing cost– Increase value of sensor nodes

• This project aims at heterogeneous Sensor‐System‐on‐ChipThis project aims at heterogeneous Sensor System on Chip– CMOS compatible stacking technology– Pseudo 3D architecture

Efficient and compact design of smart sensor node– Efficient and compact design of smart sensor node

3D ICs in the 80’s3D ICs in the 80 s• A parallel image processor from Mitsubishi

T Nishimura et al “Three dimensional IC for high performance image signal processor” IEEE International Electron Device Meeting

YC Lu  2011 Graduate Institute of Electronics Engineering, National Taiwan University

T. Nishimura et al.,  Three dimensional IC for high performance image signal processor,  IEEE International Electron Device Meeting Technical Digest, pp. 111‐114, Dec 1987.

3D ICs in the 80’s3D ICs in the 80 s• A gate‐array‐and‐memory chip from NEC

Kunio et al “Three dimensional ICs having four stacked active device layers ” IEEE International Electron Device Meeting Technical

YC Lu  2011 Graduate Institute of Electronics Engineering, National Taiwan University

Kunio et al.,  Three dimensional ICs, having four stacked active device layers,  IEEE International Electron Device Meeting Technical Digest, pp. 837‐840, Dec 1989.

Possible ApplicationsPossible Applications• Sensor systems

• Heterogeneous integration

• Memory-processor systemsMemory processor systems• Signaling/timing

N t k hi• Network-on-chip• Topology

• Field-programmable-gate-arrays • Redundancy

YC Lu  2011 Graduate Institute of Electronics Engineering, National Taiwan University

3D Technology3D Technology• Package stacking

• Die/Wafer stacking

• Device stacking

Lu “3D technology based circuit and architecture design ” Proceedings of International Conference on

YC Lu  2011 Graduate Institute of Electronics Engineering, National Taiwan University

Lu,  3D technology based circuit and architecture design,  Proceedings of International Conference on Communications, Circuits, and Systems, pp. 1124‐1128, July 2009.

Die/Wafer StackingDie/Wafer Stacking• Face‐to‐back stacking

Koyanagi et al “Three dimensional integration technology based on wafer bonding with vertical buries interconnections ” IEEEKoyanagi et al.,  Three‐dimensional integration technology based on wafer bonding with vertical buries interconnections,  IEEE Trans. Electron Devices, Vol. 53, No. 11, November 2006.

YC Lu  2011 Graduate Institute of Electronics Engineering, National Taiwan University

Device StackingDevice Stacking6 S ll• 6T‐SRAM cells

Jung et al., “Highly cost effective and high performance 65nm S3 (stacked single‐crystal Si) SRAM technology with 25 F2, 0.16um2 cell and doubly stacked SSTFT cell transistors for ultra high density and high speed applications,” Symposium on VLSI Technology Digest of

YC Lu  2011 Graduate Institute of Electronics Engineering, National Taiwan University

and doubly stacked SSTFT cell transistors for ultra high density and high speed applications,  Symposium on VLSI Technology Digest of Technical Papers, pp. 220‐221, June, 2005. (also see IEDM 2004)

Design ConsiderationsDesign Considerations• Through-silicon-vias(TSVs) &

micro-bumps (MBs)• Density• Operating frequencyp g q y• Parasitic• Styles• Yield• Yield

Davis et al “Demystifying 3D ICs: the pros and cons of going vertical ” IEEE Design & Test of Computers vol 22 no 6 pp 498

YC Lu  2011 Graduate Institute of Electronics Engineering, National Taiwan University

Davis et al., Demystifying 3D ICs: the pros and cons of going vertical,  IEEE Design & Test of Computers, vol. 22, no. 6, pp. 498‐510, Nov.‐Dec. 2005. 

Capacitive CouplingCapacitive Coupling

Gu et al “Two 10Gb/s/pin low power interconnect methods for 3D ICs ” IEEE International Solid State Circuit

YC Lu  2011 Graduate Institute of Electronics Engineering, National Taiwan University

Gu et al., Two 10Gb/s/pin low-power interconnect methods for 3D ICs, IEEE International Solid-State Circuit Conference, pp. 448-449, February, 2007.

Inductive CouplingInductive Coupling

Davis et al “Demystifying 3D ICs: the pros and cons of going vertical ” IEEE Design & Test of Computers vol 22

YC Lu  2011 Graduate Institute of Electronics Engineering, National Taiwan University

Davis et al., Demystifying 3D ICs: the pros and cons of going vertical, IEEE Design & Test of Computers, vol. 22, no. 6, pp. 498-510, Nov.-Dec. 2005.

Design ConsiderationsDesign Considerations• Device characteristics

• Thermal• Flatness• StressStress

• Device optionsSili t th d• Silicon at the same node

• Silicon at different nodes• Silicon and other materials• Active and passive

YC Lu  2011 Graduate Institute of Electronics Engineering, National Taiwan University

Design ConsiderationsDesign Considerations• Thermal issues

• Timing• NBTI• LeakageLeakage

• Thermal modeling and simulationFE/FD l• FE/FD solvers

• RC network

Chen et al., “Thermal modeling and device noise properties of three dimensional‐SOI technology," IEEE Trans. Electron Devices, Vol. 

YC Lu  2011 Graduate Institute of Electronics Engineering, National Taiwan University

, g p p gy, ,54, No. 4, pp. 656‐664, Apr. 2009.

Thermal NetworkThermal Network• Analogy

Electrical Thermal

Parameters Parameters

Voltage Temperature

Current Heat Transfer Rate

Charge Heat

][VV ][KT

][Ai ][Wq

][JQ][CQgResistance Thermal Resistance

Capacitance Thermal Capacitance

][JQT][CQ

]/[ AVRE]/[ VCCE

]/[ WTRT]/[ KJCT

Equations Equations

Transient TransientVCRV 2 TCRT 2

][JCT

Steady State Steady State

Vt

CRV EE T

tCRT TT

2

TqRT EiRV

YC Lu  2011 Graduate Institute of Electronics Engineering, National Taiwan University

Design ConsiderationsDesign Considerations• Cooling techniques

• Better heat sink• Thermal vias• Microfluidic channelsMicrofluidic channels• Micro TE coolers

Mizunuma et al., “Thermal modeling for 3D‐ICs with integrated microchannel cooling,” IEEE/ACM Proceedings of International 

YC Lu  2011 Graduate Institute of Electronics Engineering, National Taiwan University

, g g g, / g fConference on Computer‐Aided Design, Nov. 2009.

Design ConsiderationsDesign Considerations• Power integrity

• IR drops• Supply domains

• Timing strategies• Synchronization

S lf ti d• Self-timed

• Signaling strategiesg g g• I/Os• Level shifters

YC Lu  2011 Graduate Institute of Electronics Engineering, National Taiwan University

Arithmetic UnitsArithmetic Units f k d h l• Wafer‐stacked technology

Davis et al “An 8192 point Fast Fourier Transform 3D IC case study” IEEE Proceedings of MWCAS pp 438 441 Aug 2008

YC Lu  2011 Graduate Institute of Electronics Engineering, National Taiwan University

Davis et al., An 8192‐point Fast Fourier Transform 3D‐IC case study,  IEEE Proceedings of MWCAS, pp. 438‐441, Aug. 2008. 

Nonvolatile SRAM CellNonvolatile SRAM Cell

i k d h l• Device‐stacked Technology

YC Lu  2011 Graduate Institute of Electronics Engineering, National Taiwan University

Wang et al., “Nonvolatile SRAM cell,” IEEE International Electron Devices Meeting Technical Digest, Dec 2006.

Flexible ElectronicsS

Flexible Electronics• Sensors

Someya et al “Conformable flexible large area networks of pressure and thermal sensors with organic transistor active matrixes ”

YC Lu  2011 Graduate Institute of Electronics Engineering, National Taiwan University

Someya et al.,  Conformable, flexible, large‐area networks of pressure and thermal sensors with organic transistor active matrixes,  PNAS, pp. 12321‐12325, Aug. 2005.

Heterogeneous Sensor System on Chip (S2oC)Heterogeneous Sensor‐System‐on‐Chip (S2oC)• Instead of fully integration sensing device into 

f b h l hCMOS fabrication at the same layer with circuits– Low temperature processes stack sensing device on the CMOS circuitthe CMOS circuit

• The advantages by harnessing synergies of different materials and processes 

• The capability of low cost, large area fabrication, multi‐functions, and local data fusion

– Low power consumption CMOS circuits promoteLow power consumption CMOS circuits promote functionalities of each sensor node

• The improvement of network communication by local DSP capabilitiescapabilities

• The self‐intelligent network achieved by local fusion and computation

Sensor on Chip based on Inkjet printingSensor‐on‐Chip based on Inkjet‐printing• Gas Sensor: Quasi‐3D architecture

– Configurable sensing elementsNon contact patterning for CMOS chip stacking– Non‐contact patterning for CMOS chip stacking

– Stacking sensing layer on the top of CMOS chip

Expected Advantages of Heterogeneous S2oCExpected Advantages of Heterogeneous S2oC• Configurable sensing functions on a chipg g p

– Printing different material for different scope– Lowering manufacturing cost– Promoting applied value of smart sensor nodes

• Low power consumption design of smart sensor dnode

– Low power organic sensing materialE ffi i t hit t– Energy efficient architecture

• Reduced manufacturing cost of sensor nodesSt ki hit t– Stacking architecture

– Low‐cost post process for sensing elements

Challengesg• Un‐stability of organic materials

– Employing long‐chain polymer to enhance stability in– Employing long‐chain polymer to enhance stability in both thermal and electrical interference

– Utilizing parallel process elements design to minimize g gthe interference from circuit closed to sensing material

• Low selectivity of polymer sensing elements• Low selectivity of polymer sensing elements– Improving by the cross‐calibration of multiple sensing elementselements 

• Fabrication compatibility of heterogeneous nature– Using ion‐free polymer‐based sensing material– Taking the advantage of low temperature process of inkjet‐printing technology

ConclusionsConclusions

hif h d i di f• Shift the new design paradigm of sensor nodes– More sensing elements– More calculation capabilitiesp– Lower power consumptions– Lower manufacturing costLower manufacturing cost

• Harness advantages heterogeneous integrationintegration

• Pave the way toward M2M applications