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I/O System CharacteristicsDependability is importantParticularly for storage devices

Performance measuresLatency (response time)Throughput (bandwidth)Desktops & embedded systemsMainly interested in response time & diversity of devicesServersMainly interested in throughput & expandability of devicesI/O# Computer Organization IICS@VT2005-2013 McQuain3DependabilityFault: failure of a componentMay or may not lead to system failureService accomplishmentService deliveredas specifiedService interruptionDeviation fromspecified serviceFailureRestorationI/O# Computer Organization IICS@VT2005-2013 McQuain4Dependability MeasuresReliability: mean time to failure (MTTF)

Service interruption: mean time to repair (MTTR)

Mean time between failuresMTBF = MTTF + MTTR

Availability = MTTF / (MTTF + MTTR)

Improving AvailabilityIncrease MTTF: fault avoidance, fault tolerance, fault forecastingReduce MTTR: improved tools and processes for diagnosis and repairI/O# Computer Organization IICS@VT2005-2013 McQuain5Disk StorageNonvolatile, rotating magnetic storage

I/O# Computer Organization IICS@VT2005-2013 McQuain6Disk Sectors and AccessEach sector recordsSector IDData (512 bytes, 4096 bytes proposed)Error correcting code (ECC)Used to hide defects and recording errorsSynchronization fields and gaps

Access to a sector involvesQueuing delay if other accesses are pendingSeek: move the headsRotational latencyData transferController overheadI/O# Computer Organization IICS@VT2005-2013 McQuain7Disk Access ExampleGiven512B sector, 15,000rpm, 4ms average seek time, 100MB/s transfer rate, 0.2ms controller overhead, idle disk

Average read time4ms seek time+ / (15,000/60) = 2ms rotational latency+ 512 / 100MB/s = 0.005ms transfer time+ 0.2ms controller delay= 6.2ms

If actual average seek time is 1msAverage read time = 3.2msI/O# Computer Organization IICS@VT2005-2013 McQuain8Disk Performance IssuesManufacturers quote average seek timeBased on all possible seeksLocality and OS scheduling lead to smaller actual average seek times

Smart disk controller allocate physical sectors on diskPresent logical sector interface to hostSCSI, ATA, SATA

Disk drives include cachesPrefetch sectors in anticipation of accessAvoid seek and rotational delayI/O# Computer Organization IICS@VT2005-2013 McQuain9Contemporary Examples

I/O# Computer Organization IICS@VT2005-2013 McQuain10Flash StorageNonvolatile semiconductor storage100 1000 faster than diskSmaller, lower power, more robustBut more $/GB (between disk and DRAM)6.4 Flash Storage

I/O# Computer Organization IICS@VT2005-2013 McQuain11Flash TypesNOR flash: bit cell like a NOR gateRandom read/write accessUsed for instruction memory in embedded systems

NAND flash: bit cell like a NAND gateDenser (bits/area), but block-at-a-time accessCheaper per GBUsed for USB keys, media storage,

Flash bits wears out after 1000s of accessesNot suitable for direct RAM or disk replacementWear leveling: remap data to less used blocksI/O# Computer Organization IICS@VT2005-2013 McQuain12Contemporary Examples

I/O# Computer Organization IICS@VT2005-2013 McQuain13Interconnecting ComponentsNeed interconnections betweenCPU, memory, I/O controllers

Bus: shared communication channelParallel set of wires for data and synchronization of data transferCan become a bottleneck

Performance limited by physical factorsWire length, number of connections

More recent alternative: high-speed serial connections with switchesLike networksI/O# Computer Organization IICS@VT2005-2013 McQuain14Bus TypesProcessor-Memory busesShort, high speedDesign is matched to memory organization

I/O busesLonger, allowing multiple connectionsSpecified by standards for interoperabilityConnect to processor-memory bus through a bridgeI/O# Computer Organization IICS@VT2005-2013 McQuain15Bus Signals and SynchronizationData linesCarry address and dataMultiplexed or separate

Control linesIndicate data type, synchronize transactions

SynchronousUses a bus clock

AsynchronousUses request/acknowledge control lines for handshakingI/O# Computer Organization IICS@VT2005-2013 McQuain16I/O Bus ExamplesFirewireUSB 2.0USB 3.0PCI ExpressSerial ATASerial Attached SCSIIntended useExternalExternalExternalInternalInternalExternalDevices per channel63127127114Data width4242/lane44Peak bandwidth400 Mb/s or800 Mb/s1.6 Mb/s, 12 Mb/s, or 480 Mb/s5 Gb/s,10 Gb/x2 Gb/s/lane1, 2, 4, 8, 16, 322.4 Gb/s2.4 Gb/sHot pluggableYesYesYesDependsYesYesMax length4.5m5m?0.5m1m8mStandardIEEE 1394USB ImplementersForumUSB ImplementersForumPCI-SIGSATA-IOINCITS TC T10I/O# Computer Organization IICS@VT2005-2013 McQuain17

Typical x86 PC I/O SystemI/O# Computer Organization IICS@VT2005-2013 McQuain18I/O ManagementI/O is mediated by the OSMultiple programs share I/O resourcesNeed protection and schedulingI/O causes asynchronous interruptsSame mechanism as exceptionsI/O programming is fiddlyOS provides abstractions to programsI/O# Computer Organization IICS@VT2005-2013 McQuain19I/O CommandsI/O devices are managed by I/O controller hardwareTransfers data to/from deviceSynchronizes operations with software

Command registersCause device to do something

Status registersIndicate what the device is doing and occurrence of errors

Data registersWrite: transfer data to a deviceRead: transfer data from a deviceI/O# Computer Organization IICS@VT2005-2013 McQuain20I/O Register MappingMemory mapped I/ORegisters are addressed in same space as memoryAddress decoder distinguishes between themOS uses address translation mechanism to make them only accessible to kernel

I/O instructionsSeparate instructions to access I/O registersCan only be executed in kernel modeExample: x86I/O# Computer Organization IICS@VT2005-2013 McQuain21PollingPeriodically check I/O status registerIf device ready, do operationIf error, take action

Common in small or low-performance real-time embedded systemsPredictable timingLow hardware cost

In other systems, wastes CPU timeI/O# Computer Organization IICS@VT2005-2013 McQuain22InterruptsWhen a device is ready or error occursController interrupts CPU

Interrupt is like an exceptionBut not synchronized to instruction executionCan invoke handler between instructionsCause information often identifies the interrupting device

Priority interruptsDevices needing more urgent attention get higher priorityCan interrupt handler for a lower priority interruptI/O# Computer Organization IICS@VT2005-2013 McQuain23I/O Data TransferPolling and interrupt-driven I/OCPU transfers data between memory and I/O data registersTime consuming for high-speed devices

Direct memory access (DMA)OS provides starting address in memoryI/O controller transfers to/from memory autonomouslyController interrupts on completion or errorI/O# Computer Organization IICS@VT2005-2013 McQuain24DMA/Cache InteractionIf DMA writes to a memory block that is cachedCached copy becomes stale

If write-back cache has dirty block, and DMA reads memory blockReads stale data

Need to ensure cache coherenceFlush blocks from cache if they will be used for DMAOr use non-cacheable memory locations for I/OI/O# Computer Organization IICS@VT2005-2013 McQuain25DMA/VM InteractionOS uses virtual addresses for memoryDMA blocks may not be contiguous in physical memory

Should DMA use virtual addresses?Would require controller to do translation

If DMA uses physical addressesMay need to break transfers into page-sized chunksOr chain multiple transfersOr allocate contiguous physical pages for DMAI/O# Computer Organization IICS@VT2005-2013 McQuain26