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DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING

CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN

UNIT 3

DESIGN WITH MSI DEVICES

Decoders and encoders – Multiplexers and demultiplexers – Memory and programmable logic – HDL for combinational circuits

3.1 DECODERS

Often, digital information represented in some binary form must be converted into some alternative digital form. This is achieved by a multiple-input, multiple output network referred to as a decoder. The most commonly used decoder is the n-to-2n-line decoder:

The structure of a such decoder is straightforward. Consider the truth table of a 3-to-8-line decoder:

This corresponds to the logic diagram shown below:

A particular application for this decoder is binary to-octal conversion. The input variables represent a binary number, and the outputs represent the eight digits in the octal number system.

3.1.1 Decoders with an Enable Input

Some decoders include one or more enable inputs to control the circuit operation. The logic diagram and truth table of a 2-to-4-line decoder are shown below:

A decoder with enable input can function as a demultiplexer. The above decoder can function as a 4-to-1-line demultiplexer when E is taken as a data input line and A and B are taken as the selection inputs.

Decoders with enable inputs can be connected together to form a larger decoder circuit. A 4-to-16-line decoder realized using two 3-to-8-line decoders is shown below:

When w = 0, the top decoder is enabled and the other is disabled. The bottom decoder outputs are all 0’s, and the top eight outputs generate minterms 0000 to 0111.

When w = 1, the enabled conditions are reversed; the bottom decoder generates minterms 1000 to 1111, while the outputs of the top decoder are all 0’s.

3.1.2 Combinational Logic Implementation An n-to-2n-line decoder is a minterm generator. Recall that any

Boolean function is describable by a sum-of-minterms. Thus, by using OR-gates in conjunction with an n-to-2n-line decoder realizations of Boolean functions are possible. However, these realizations do not correspond to minimal sum-of-products.Consider the pair of expressions:

F1(X2,X1,X0) = F2(X2,X1,X0) =

Using a single 3-to-8-line decoder and two ORgates, the following realization is obtained:

When more than ½ the total number of minterms must be OR-ed, it is usually more economical to use NOR-gates rather than OR-gates to do the summing. Consider the pair of expressions:

F1(X2,X1,X0) = F2(X2,X1,X0) =

These may be realized with a 3-to-8-line decoder and two OR-gates having a total of 11 terminals between them. However, a more efficient realization is to re-write the expressions as:

F1’’(X2,X1,X0) = F1’(X2,X1,X0) = F2’’(X2,X1,X0) = F2’(X2,X1,X0) =

This corresponds to the realization shown below:

A total of five gate-input terminals are needed.

3.2 ENCODER

Perform the inverse operation of decoders. An encoder has 2n (or fewer) input lines and n output lines. The output lines generate the binary code corresponding to the input value. An example of an encoder is the octal-to-binary encoder whose truth table is as follows:

The equations for the three outputs are:Z = D1 + D3 + D5 + D7y = D2 + D3 + D6 + D7x = D4 + D5 + D6 + D7

The encoder can be realized with three OR-gates.

3.2.1 Priority Encoder The encoder defined before has the limitation that only one input

can be active at any given time. If two inputs are active simultaneously, the output produces an undefined combination. This is resolved by establishing an input priority function. The truth table of a four-input priority encoder is:

In addition to the two outputs, x and y, the circuit has a third output V; this is a valid bit indicator and is set to 1 when one or more inputs are equal to 1. X’s in the output represent don’t-care conditions.

X’s in the input columns are for representing the truth table in condensed form. Instead of listing all 16 minterms of four variables, the truth table usesan X to represent either 1 or 0.

According to the table, D3 has the highest priority followed by D2 and D1. The maps for simplifying outputs x and y are shown below:

The condition for output V is an OR function of all the input variables:V = D0+D1+D2+D3

The priority encoder is implemented as follows:

3.3 MULTIPLEXERS

A multiplexer is a circuit that selects binary information from one of many input lines and directs it to a single output. Normally, there are 2n input lines and n selection lines whose bit combination determine which input is selected.

The logic and block diagrams of a 2-to-1-line multiplexer are shown below:

The circuit has two data input lines, I1 and I2, one output line Y,

and one selection line S. When S = 1, the lower AND gate is enabled and I1 has path to

the output. This multiplexer acts like a switch that selects one of the two sources.A 4-to-1-line multiplexer is shown below:

A multiplexer is also called a data selector, since it selects one of

many inputs and steers the binary information to the output line.

In general, a 2n-to-1-line multiplexer is constructed from an n-to-2n decoder by adding to it 2n input lines, one to each AND gate. The outputs of the AND gates are applied to a single OR gate.

As in decoders, multiplexers may have an enable input to control the operation of the unit.

By interconnecting several multiplexers in a treelike structure, it is possible to produce a larger multiplexer. For example, a 16-to-1 line multiplexer may be constructed using five 4-to-1-line multiplexers as follows:

3.3.1 MUX/DeMUX Transmission System

One of the primary applications of multiplexers is to provide for the transmission of information from several sources over a single path. This process is known as multiplexing. E.g., the multiplexing of conversations on the telephone system.

When a multiplexer is used in conjunction with a demultiplexer, an effective means is provided for connecting information from several source locations to several destination locations. This basic application is illustrated below:

By using n of the structures shown above in parallel, an n-bit word from any of four source locations is transferred to the four destination locations.

3.4 MEMORY AND PROGRAMMABLE LOGIC DEVICES

A memory unit is a collection of cells capable of storing a large quantity of binary information. There are two types of memories that are used in digital systems:

Random-Access Memory (RAM): Accepts new data for storage to be available later for use. RAM can perform both write and read operations. A RAM loses its stored data when power is turned off, thus it is a volatile memory.

Read-Only Memory (ROM): Cannot have its contents changed during normal operation. Its contents are determined either at the time

of manufacture or during a special write mode. A ROM retains stored data even if power is switched off, thus it is a non-volatile memory.

The ROM is an example of a programmable logic device. Other such units are the programmable logic array (PLA), the programmable array logic (PAL), and the field-programmable gate array (FPGA). Programming of these devices involves blowing fuses at specified locations.

3.4.1 Random-Access Memory

The time it takes to transfer information to or from any desired random location is always the same, hence, the name random-access memory (RAM).

A memory unit stores binary information in groups of bits called words. A group of eight bits is called a byte. The capacity of a memory unit is usually stated as the total number of bytes it can store.

A block diagram of the memory unit is:

The n data input lines provide the information to be stored in memory and the n output lines specify the binary data coming out of the memory. The k address lines specify the particular word chosen. The two control inputs specify the direction of data transfer required.

Each word in memory is assigned an identification number, called an address (0 up to 2k-1). The selection of a specific word inside the memory is done by applying the k-bit address to the address lines.

A decoder accepts this address and opens the paths needed to select the word specified.

Memories vary greatly in size and may range from 1024 words, requiring an address of 10 bits. To 232 word requiring 32 address bits.

The possible content of the first three and the last three words in a 1024 x 16

memory (2K bytes) are:

Write and Read Operations

The steps that must be taken for the purpose of transferring a new word to be stored into memory are as follows:

1. Apply the binary address of the desired word to the address lines.

2. Apply the data bits that must be stored in memory to the data input lines.

3. Activate the write input.

The steps that must be taken for the purpose of transferring a stored word out of memory are as follows:

1. Apply the binary address of the desired word to the address lines.

2. Activate the read input.

Some memory chips have a different configuration of control inputs; one input selects the unit and the other decides the operation. The operations that result from these control inputs are:

3.4.1.1 Types of RAM

Integrated circuit RAM units are available in two possible operating modes:

Static RAM (SRAM): Consists essentially of internal latches that store the binary data. The stored information remains valid as long as power is applied to the unit.

Dynamic RAM (DRAM): Stores the binary data in the form of electric charges on capacitors. The capacitors are provided inside the chip by MOS transistors. The stored charge on the capacitor tends to discharge with time and the capacitors must be periodically recharged by refreshing the DRAM. Refreshing is done by cycling through the words every 2 to 10ms to restore the decaying charge. DRAM is also a volatile memory.

DRAM offers reduced power consumption and larger storage capacity in a single memory chip.

SRAM is easier to use and has shorter read and write cycles.

3.4.1.2 RAM Memory Decoding

In addition to the storage elements in a memory unit, there is a need for decoding circuits to select he memory word specified by the input address.

Internal Construction

The internal construction of a RAM of m words and n bits per word consists of m x n binary storage cells and associated decoding circuits for selecting individual words. The binary storage cell is the basic building block of a memory unit. The logic of a binary cell (BC) that stores one bit of information is shown below:

The logical realization of a small 4 x 4 RAM is:

The decoder is enabled with the memory enable input. Once a word is selected, the Read/Write input determines the operation. During the read operation, the four bits of the selected word go through OR gates to the output terminals. During the write operation,

the data available in the input lines are transferred into the four binary cells of the selected word.

3.4.2 Read-Only Memory A read-only memory (ROM) is a memory in which permanent

binary information is stored. A block diagram of a ROM is shown below:

The inputs give the address for the memory and the outputs give the data bits of the stored word selected. ROM chips also have enable inputs. Consider the following 32 X 8 ROM:

The 256 interconnections are programmable. For example, the partial content of a 32 x 8 ROM may be specified by the following truth table:

hardware procedure that programs the ROM results in blowing fuse links according to a given truth table. The above truth table results in:

3.4.2.1 Combinational Circuit Implementation The programmed ROM shown previously may be considered as a

combinational circuit with eight outputs, each being a function of five input variables. E.g., output A7 can be expressed in sum of minterms as:

A7(I4, I3, I2, I1, I0 ) = Example: Design a combinational circuit using a ROM. The circuit accepts a 3-bit number and generates an output binary number equal to the square of the input number.Solution:The first step is to generate the truth table of the combinational circuit:

Only outputs B3 – B6 need be generated with a ROM; the other two are readily obtained. The ROM required must be of size 8 X 4. The ROM realization is shown below:

The following truth table specifies the information needed for programming the ROM:

Note that when implementing Boolean functions with a ROM, minimisations are not necessary. Boolean functions are realized as sum of P-terms.

3.4.2.2 Types of ROMs There are three main types or ROMs and they differ in the way

they are programmed:Mask ROM: Contents programmed at factory according to the desired specification, and no changes are possible afterwards. This type is uneconomical for small quantities because the vendor charges the customer a special fee for custom masking the particular ROM.PROM: User programmable using a PROM programmer. Once programmed the contents can not be changed. The factory settings are all 1’s and the user sets specified bits to 0’s by blowing up fusible links. Fairly economical for small quantities.

EPROM: User programmable and erasable by means of ultraviolet radiation (UV EPROM) or electrical pulses (EEPROM). It use an n-MOS memory array with isolated-gate structure. The isolated gate has no electrical connections and can store electrical charge for indefinite periods of time. Erasure of data bits is done by removing the gate charge.

3.4.2.3 Combinational PLDs The PROM is a combinational programmable logic device (PLD). A

combinational PLD is an IC with programmable gates divided into an AND array and an OR array to provide an AND-OR sum-of product implementation.

There are three major types of combinational PLDs and they differ in the placement of the programmable connections in the AND-OR array:

3.4.3 Programmable Logic Array

Consists programmable AND and OR arrays and output XOR gates (controllable inverters). The internal logic of a PLA with three inputs and two outputs is shown below:

The particular Boolean functions implemented are:F1 = AB’+ AC+A’ BC’F2=( AC+ BC)’

The fuse map of a PLA may be specified in a tabular form. For example, the programming table that specifies the PLA shown previously is:

The first section list the product terms numerically. The second section specifies the required paths between inputs and AND gates. The third section specifies the paths between the AND and OR gates. The product terms listed on the left are included for reference only.

As with a ROM, the PLA may be mask or field programmable. When implementing a combinational circuit with a PLA, care must be

taken to reduce the number of distinct product terms, since a PLA has a finite number of AND gates. This can be done by simplifying each Boolean function (both the true and complement).

3.4.4 Programmable Array LogicThe PLA is a device with a fixed OR array and a programmable

AND array. Unlike a PLA, a product term cannot be shared amongst two or more OR gates. Thus, no optimum solutions are required as would be the case for PLA implementations.

The logic configuration of a typical PAL is:

Consider the following Boolean functions:

W(A,B,C,D) = X(A,B,C,D) = Y(A,B,C,D) = Z(A,B,C,D) =

The simplified Boolean functions are:W = ABC’ + A’B’CD’X = A+BCDY = A’B + CD + B’D’Z = ABC’ + A’B’CD’ + AC’D’ + A’B’C’D + = W + AC’D’ + A’B’C’D

The resulting PLA programming table is:

The logic diagram of the programmed PAL is:

3.5 HDL FOR COMBINATIONAL CIRCUITS3.5.1 Gate-Level Modeling

Here a circuit is specified by its logic gates and their interconnections.

It provides a textual description of a schematic diagram. Verilog recognizes 12 basic gates as predefined primitives.

4 primitive gates of 3-state type. Other 8 are: and, nand, or, nor, xor, xnor, not, buf

When the gates are simulated, the system assigns a four-valued logic set to each gate – 0,1,unknown (x) and high impedance (z)

4-bit Full Adder

//Gate-level hierarchical description of 4-bit adder module halfadder (S,C,x,y); input x,y; output S,C; //Instantiate primitive gates xor (S,x,y); and (C,x,y);endmodule module fulladder (S,C,x,y,z); input x,y,z; output S,C; wire S1,D1,D2; //Outputs of first XOR and two AND gates //Instantiate the half adders halfadder HA1(S1,D1,x,y), HA2(S,D2,S1,z); or g1(C,D2,D1);endmodule

3.5.2 Dataflow Modeling Dataflow modeling uses a number of operators that act on

operands to produce desired results. Verilog HDL provides about 30 operator types. Dataflow modeling uses continuous assignments and the

keyword assign. A continuous assignment is a statement that assigns a value to a

net. The value assigned to the net is specified by an expression that

uses operands and operators.

//Dataflow description of a 2-to-4-line decoder module decoder_df (A,B,E,D); input A,B,E;

output [0:3] D; assign D[0] = ~(~A & ~B & ~E), D[1] = ~(~A & B & ~E), D[2] = ~(A & ~B & ~E), D[3] = ~(A & B & ~E);endmodule

3.5.3 Behavioral Modeling Behavioral modeling represents digital circuits at a functional

and algorithmic level. It is used mostly to describe sequential circuits, but can also be

used to describe combinational circuits. Behavioral descriptions use the keyword always followed by a list

of procedural assignment statements. The target output of procedural assignment statements must be

of the reg data type. A reg data type retains its value until a new value is assigned. The procedural assignment statements inside the always block

are executed every time there is a change in any of the variable listed after the @ symbol. (Note that there is no “;” at the end of always statement)

//Behavioral description of 2-to-1-line multiplexermodule mux2x1_bh(A,B,select,OUT); input A,B,select; output OUT; reg OUT;

always @(select or A or B) if (select == 1) OUT = A; else OUT = B;endmodule