intrin. freq. limits - mit opencourseware · 2020. 7. 10. · 6.012 - microelectronic devices and...

6.012 - Microelectronic Devices and Circuits Lecture 24 - Intrin. Freq. Limits - Outline

• Announcements Final Exam - Tuesday, Dec 15, 9:00 am - 12 noon

• Review - Shunt feedback capacitances: Cµ and Cgd Miller effect: any C bridging a gain stage looks bigger at the input Marvelous cascode: CE/S-CB/G (E/SF-CB/G work, too - see µA741)

large bandwidth, large output resistance used in gain stages and in current sources

Using the Miller effect to advantage: Stabilizing OP Amps - the µA741

• Intrinsic high frequency limitations of transistors General approachMOSFETs: fT

biasing for speed impact of velocity saturation design lessons

BJTs: fβ, fT, fα biasing for speed design lessons

Clif Fonstad, 12/8/09 Lecture 24 - Slide 1

Summary of OCTC and SCTC results

• OCTC: an estimate for ωHI

log !

log |A vd |

!b !c!d!a

!LO !LO*

!4 !5!2!1 !3

!HI* !HI

Mid-band Range

1. ωHI* is a weighted sum of ω's associated with device capacitances: (add RC's and invert)

2. Smallest ω (largest RC) dominates ωHI * 3. Provides a lower bound on ωHI

• SCTC: an estimate for ωLO 1. ωLO * is a weighted sum of w's associated with bias capacitors:

(add ω's directly) 2. Largest ω (smallest RC) dominates ωLO * 3. Provides a upper bound on ωLO


The Miller effect (general)

+

-

vin

(1-Av)vin

Cm vout = Avvin

+

-

+ -iin

Consider an amplifier shunted by a capacitor, and consider how the capacitor looks at the input and output terminals:

Note: Av is negative

vout

+

-

Cm

vin

+

-

Av

!

iin

= Cm

d 1" Av( )vin[ ]

dt= 1" A

v( )Cm

dvin

dt

+

-

voutCm+

-

vin (1-Av)Cm

Cin looks much

!

Cm

1" Av( )

Av

# Cm

bigger than Cm Cout looks like Cm


The cascode when the substrate is grounded: High frequency issues:

L.E.C. of cascode: can't use equivalent transistor idea here because it didn't address the issue of the C's!

ro2

vgs1

gm1vgs1

ro1

+

-

(gm2+gmb2)vgs2

+

-

vgs2

+

-

voutrl

Cdb1 +Cgs2 +Cbs2

Cgd2 +Cbd2

Cgd1

Cgs1

g1 d1,s2,b2 d2

s1,b1,b2 s1,b1,g2,b2 g2,b2

Voltage gain ≈ -1 so Voltage gain ≈ g rl,mminimal Miller effect. without Miller effect.

Common-source gain without the Miller effect penalty!


Multi-stage amplifier analysis and design: The µA741

Figuring the circuit out: Emitter-follower/

Current mirror load Simplified schematic

Push-pulloutput

common-base "cascode" differential gain stage

EF

CB

The full schematic © Source unknown. All rights reserved. This content is excluded from our Creative Commons license. For more information, see http://ocw.mit.edu/fairuse.

Darlington common-emitter gain stage

© Source unknown. All rights reserved. Clif Fonstad, 12/8/09 This content is excluded from our Creative Commons license. Lecture 24 - Slide 5

For more information, see http://ocw.mit.edu/fairuse.

http://ocw.mit.edu/fairuse


Multi-stage amplifier analysis and design: Understanding the µA741 input "cascode"

Begin with the BJT building-block stages:

+

-

voutv t

+

-

rtiout iin

gmv!

+

-

v in

+

-

voutgo

c

e e

b

Common emitter

iout

g!

+

-

v!

v in

+

-

v in

+

-

vout

gsl +

!/(rt+r!)

e

cc

b

Emitter follower

iiniout

r" +

!/gl

+

-

iin

+

-

v in

+

-

vout

d

g,bg,b

s

Common base

! go/!

iiniout

!(gm+g!)

+

-

v in rl = 1/gl

iin

Relative sizes: gm: large gπ: medium go: small

gt, gl: cannot generalize


Multi-stage amplifier analysis and design: Two-port models Two different "cascode" configurations, this time bipolar:

+

-

voutv t

+

-

rtiout

+

-

v in rl = 1/gl

iiniin

gmv!

+

-

v in

+

-

voutgo

c

e e

b

Common emitter

iout

g!

+

-

v!

+

-

voutv t

+

-

rtiout

+

-

v in rl = 1/gl

iiniin

gmv!

+

-

v in

+

-

voutgo

c

e e

b

Common emitter

iout

g!

+

-

v! iin

+

-

v in

+

-

vout

d

g,bg,b

s

Common base

! go/!

iiniout

!(gm+g!)

+

-

v in rl = 1/gl

iin

iin

+

-

v in

+

-

vout

d

g,bg,b

s

Common base

! go/!

iiniout

!(gm+g!)

+

-

voutv t

+

-

rtiout

!v in

+

-

v in

+

-

vout

! !/(rt+r!)

e

cc

b

Emitter follower

iiniout

r" +

!/gl

+

-

In a bipolar cascode, starting with an emitter follower still reduces the gain, but it also gives twice the input resistance, which is helpful.


Multi-stage amplifier analysis and design: MOSFET 2-port models Reviewing our building-block stages:

+

-

voutv t

+

-

rtiout

gmv in

+

-

v in

+

-

voutgm+go+gl

s,b

dd

g

Source follower

iiniout

(gm+

gmb)v in

+

-

v in

+

-

vout gogt

gm+gmb+gt

d

g,bg,b

s

Common gate

gm+

gmb

iiniout

iin

gmv in

+

-

v in

+

-

voutgo

d

s,gs,g

g

Common source

iout+

-

v in rl = 1/gl

iin

Relative sizes: large gm, gmb:

go: small gt, gl: cannot

generalize


Multi-stage amplifier analysis and design: Two-port models

Two different "cascode" configurations:

+

-

voutv t

+

-

rtiout

+

-

v in rl = 1/gl

iiniin

gmv in

+

-

v in

+

-

voutgo

d

s,gs,g

g

Common source

iout

+

-

voutv t

+

-

rtiout

+

-

v in rl = 1/gl

iin

(gm+

gmb)v in

+

-

v in

+

-

vout gogt

gm+gmb+gt

d

g,bg,b

s

Common gate

gm+

gmb

iiniout

iin

gmv in

+

-

v in

+

-

voutgo

d

s,gs,g

g

Common source

iout

gmv in

+

-

v in

+

-

voutgm+go+gl

s,b

dd

g

Source follower

iiniout

+

-

voutv t

+

-

rtiout

+

-

v in rl = 1/gl

iin

(gm+

gmb)v in

+

-

v in

+

-

vout gogt

gm+gmb+gt

d

g,bg,b

s

Common gate

gm+

gmb

iiniout

With MOSFETs, starting a cascode with a source follower costs a factor of two in gain

Clif Fonstad, 12/8/09 because rout for an SF is small, so it isn't very attractive. Lecture 24 - Slide 9


The circuit: a full schematic

The monolithic capacitor made the µA741

"complete" and a big success. Why is it

needed? What does it do?

C1

is in

a Miller

position

across

Q16

Clif Fonstad, 12/8/09 Lecture 24 - Slide 10 © Source unknown. All rights reserved. This content is excluded from our Creative Commons license. For more information, see http://ocw.mit.edu/fairuse.



Why is there a capacitor in the circuit?: the added capacitorintroduces a low

frequency polethat stabilizes

the circuit.

Without it the gain is still greater than 1 when the phase shift exceeds 180˚ (dashed curve). This can result in positive feedback and instability.

With it the gain is less than 1 by the time the phase shift exceeds 180˚

(solid curve).

Lowfrequency

pole


Intrinsic performance - the best we can do We've focused on ωHI, the upper limit of mid-band, but even when ω > ωHI

the |Av| > 1, and the circuit is useful. For example, for the common source stage we had

!

Av

j"( ) =#g

tg

m# j"C

gd( )j"( )

2

CgsC

gd+ j" g

l+ g

o( )Cgs+ g

l+ g

o+ g

t+ g

m( )Cgd[ ] + gl+ g

o( )gt{ }

gm /(gl+go)

log |Av,oc |

log !

!1 ! 2! 31

!1gm /(gl+go)

A Bode plot of Av is shown to the right:

this and ask how high can a device in isolation have provide voltage or current gain?

When we look for a metric to compare the ultimate performance limits of transistors, we make note of


Intrinsic performance - the best we can do, cont. Consider the two possibilities shown below, one for a voltage input and

output where the metric would be the open circuit voltage gain, Av,oc, and the other for a current input and output with the metric being the short circuit current gain, Ai,sc (commonly written βsc):

!

Av,oc

s( ) "v

out( j#)

vin

( j#)= $

gm$ j#C

gd

go$ j#C

gd

+

-

vgs gmvgsgo

Cgs

Cgd d

s,bs,b

g

iiniout

+

-

vgs gmvgsgo

Cgs

Cgd d

s,bs,b

g

v in

+

-

+

-

vout

!

"sc

j#( ) $id

j#( )ig

j#( )=

gm% j#C

gd

j# Cgs

+ Cgd( )

Of these two alternatives, β is the more useful. A is derived with a sc v,oc voltage source driving a capacitor, something that doesn't give a mean-ingful result and leads to ever increasing input power. It also does not involve gm and Cgs. Consequently, short circuit current gain is used as the intrinsic high frequency performance metric for transistors.


Intrinsic ωHI's for MOSFETs - short-circuit current gain

+

-

vgs gmvgsgoig

Cgs

Cgd idd

ss

g

The common-source short-circuit current gain is:

!

"sc

j#( ) $id

j#( )ig

j#( )=

gm% j#C

gd

j# Cgs

+ Cgd( )

there is one pole at ω = 0, and one zero, ωz:

!

"z

=g

m

Cgd

The short circuit current gain, βsc, is infinite at DC (ω = 0) , and its magnitude decreases linearly with increasing frequency.


Intrinsic ωHI's for MOSFETs - short-circuit current gain, cont.

+

-

vgs gmvgsgoig

Cgs

Cgd idd

ss

g

The magnitude of βsc decreases with ω, but it is still greater than one for a wide range of frequencies.

!

"sc

j#( ) =g

m

2 +# 2C

gd

2

# 2C

gs+ C

gd( )2

The transistor is useful until |βsc| is less than one. The frequency at which this occurs is called ωt. Setting = 1 and solving for ωt yields:

!

"t=

gm

2

Cgs

+ Cgd( )

2

#Cgd

2[ ]$

gm

Cgs

+ Cgd( )


MOSFET short-circuit current gain, βsc(jω), cont.

log !

log |"sc |

!t

!z

No 3dB point, ωb.

Low frequency value: infinity

Zero, ωz : ωz = gm/Cgd

Note: ωz > ωt

Unity gain point, ωt : ωt @ gm/(Cgs+Cgd)


MOSFET short-circuit current gain, βsc(jω), cont.

log !

log |"sc |

!t

!z!

"t(MOSFET) =

gm

Cgs

+ Cgd( )

#g

m

Cgs

=

W

Lµ

ChC

ox

*V

GS$V

T

2

3W LC

ox

*

=3

2

µCh

VGS$V

T

L2

Can we bias to maximize ωt?

What is the ultimate limit? Channel transit time!

Maximize VGS.

!

"t(MOSFET) =

3

2

µCh

VGS#V

T

L2

=3

2Lµ

Ch

VDS

L=

3

2Lµ

ChE

Ch=

3

2

sCh

L=

1

$Ch

Lessons: Bias at well above VT; make L small, use n-channel. Clif Fonstad, 12/8/09 Lecture 24 - Slide 17

An aside: looking back at CMOS gate delays

CMOS: switching speed; minimum cycle time (from Lec. 15)

Gate delay/minimum cycle time:

!

"Min Cycle

=12nL

min

2V

DD

µe

VDD#V

Tn[ ]2

For MOSFETs operating in strong inversion, no velocity saturation:

Comparing this to the channel transit time:

!

"Ch Transit

=L

min

s e,Ch

=L

min

µe#

Ch

=L

min

µe

VDD$V

Tn( ) Lmin

We see that the cycle time is a multiple of the transit time:

!

"Min Cycle

=12nV

DD

VDD#V

Tn( )"

Channel Transit= n' "

Channel Transit

When velocity saturation dominated, we found the same thing:

!

"Min.Cycle

#L

minV

DD

ssat

VDD$V

Tn[ ]= n'"

ChanTransit

!

"ChanTransit

=L

ssat

where


Intrinsic ωHI's for MOSFETs - βsc(jω) and ωt w. velocity saturation

What about the intrinsic ωHI of a MOSFET operating with full velocity saturation?

The basic result is unchanged; we still have:

!

"t

=g

m

2

Cgs

+ Cgd( )

2

#Cgd

2[ ]$

gm

Cgs

+ Cgd( )

$g

m

Cgs

However, now gm is different:

!

gm

= W ssat

Cox

*

With this we have:

!

"t#

gm

Cgs

=W s

satC

ox

*

W LCox

*=

ssat

L=

1

$Ch

In the case where velocity saturation dominates, we once again find that it is the channel transit time that is the ultimate limit.

Do you care to speculate on the intrinsic ωHI of a BJT? Clif Fonstad, 12/8/09 Lecture 24 - Slide 19

Intrinsic ωHI's for BJTs - short-circuit current gain

The common-emitter short-circuit current gain is:

!

"sc

j#( ) $ic

j#( )ib

j#( )=

gm% j#Cµ

g& + j# C& + Cµ( )[ ]

g!

+

-

v! gmv! goib

C!

Cµ icc

ee

b

there is one pole, call it ωp, and one zero, ωz:

!

"p

=g#

C# + Cµ( ), "

z=

gm

Cµ

Of these two, ωp is much smaller and this is the 3dB point of the common-emitter short-circuit current gain.

!

"# =g$

C$ + Cµ( )

We give it the name ωβ:


Intrinsic ωHI's for BJTs - short-circuit current gain, cont.

g!

+

-

v! gmv! goib

C!

Cµ icc

ee

b

The magnitude of βsc decreases above ωb, but it is still greater than one initially:

!

"sc

j#( ) =g

m

2 +# 2Cµ

2

g$2 +# 2

C$ + Cµ( )2

[ ]

The transistor is useful until |βsc| is less than one. The frequency at which this occurs is called ωt. Setting = 1 and solving for ωt yields:

!

"t=

g#2 + g

m

2( )C# + Cµ( )

2

$Cµ

2[ ]%

gm

C# + Cµ( )


BJT short-circuit current gain, βsc(jω), cont.

log !

log |"sc |

"F

!" !t

!z

Note: ωz > ωt >> ωβ

/Cµ

3dB point, ωb: ωb = gπ/(Cπ+Cµ)

Unity gain point, ωt : ωt @ gm/(Cπ+Cµ)

Low frequency value: βF

Zero, ωz : ωz = gm

(= ωt /βF)


BJT short-circuit current gain, βsc(jω), cont.

log !

log |"sc |

"F

!" !t

!z

In the limit of large IC:

!

"t#

gm

C$ + Cµ( )=

qIC

kT

qIC

kT

%

& '

(

) * + b

+ Ceb,dp

+ Ccb,dp

,

- .

/

0 1

Used C$ = gm+

b+ C

eb,dp

Can we bias to maximize ωt?

Maximize IC.

!

limIC "#$ t

%1

&b

=2D

min,B

wB

2=

2µmin,B

Vthermal

wB

2

Base transit time

Base transit time

Lessons: Bias at large IC; make wB small, use npn. Clif Fonstad, 12/8/09 Lecture 24 - Slide 23

6.012 - Microelectronic Devices and Circuits

Lecture 24 - Intrinsic Limits of Transistor Speed - Summary

• Intrinsic high frequency limits for transistorsGeneral approach: short-circuit current gains

• Limits for MOSFETs: Metric - CS short-circuit current unity gain pt: ωT = gm/[(Cgs+Cgd)2 -Cgd

2]1/2

ωT is approximately g /C = 3µ (VGS-VT)/2L2 m gs e

g = (W/L)µ C *(VGS-VT) and C = (2/3)WLC * m e ox gs ox

so ωT ≈ 3µe(VGS-VT)/2L2 = 1/τch

Design lessons: bias at large ID minimize L (win as L2; as L in velocity saturation) use n-channel rather than p-channel (µ >> µh)

• Limits for BJTs: e

Metrics - CE short-circuit current gain 3B pt: ωb = gp/(Cπ + Cµ) CE short-circuit current gain unit gain pt: ωT = gm/(Cπ + Cµ)

ωT approaches 1/τb as Ic increases and τb = wB2/2Dmin,B

so ωT ≈ 2Dmin,B/wB2 = 2µeVt/wB

2 = 1/τb

CB short-circuit current gain unit gain pt: ωα = gm/Cπ

Design lessons: bias at high collector current minimize wB (win as wB

2) use npn rather than pnp (µ >> µh)e


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6.012 Microelectronic Devices and Circuits Fall 2009

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