interviewquentions

8/8/2019 InterviewQuentions

1/5

Interview Questions (Must Prepare):

1st round (telephonic)

- around 45 mins plus

- almost all about PCI express protocol

- at last about verilog- what is parameters ?

- what is generic?

- what is package in VHDL ?

- what is generate statement?

- generic ?

- difference between `define and params ? ifdefine ??

now all F2F round

2nd round:

- aound 1 hour- designer ...

- explain about one project- how was FIFO build in that ?

- how data xfer was done ?- grey code and its usage?

- bus synchronization

- write state machine

- write about edge detector

- write code for shown waveform (wave form was of posedge and negedge detector)

- synch FIFO or asych FIFO ? why to use grey code ?

- what to do when there is post tapeout violations ?

- setup and hold equations

- verilog code for synch and asynch flops

- latch inference

- SoC architectures like .. AHB bus etc ...

3rd round- just 15 mins max

- scripting expert- just asked me about an algorith of scripting

- told to develope algorith to grep something from one file .. and print line numbers ..

- print given line numbers from other file ..- how do we exclude comments from counting keyword ..- will this always work kind of questions ..

- than he made scenrio much complex ... by asking in depth questions

4th round

- around 45 mins plus

- tech lead

- asked about ALL of my project and each line of it


2/5

- how do meet timing if there is chain of logic ?- what to for CDC paths ?

- can we safely put CDC path as false paths ?- what is CDC flops are lying at 2 corners of the chip ?

5th round

- around 45 mins plus- manager

- class and its object

- what is differnece between caling constructor and writing new () etc etc ...

- write code to detect position of first one among 32 bits ..

- write synthesizable code ..

- what is DFT ?

- are 100% flops scanable?

- why few are not scale?

- under which conditions they are not scanble ?

- what is reset synch- draw its design

- how dos this work- no ... reset synch u have drawn is wrong .. it is this way .. what do you say?

- how to verify metastability ?- what to do for bus synchronization?

- and why ???

6th round

- manager,

- around 20 mins

- half of the time he spent in asking my interest and why am i chaing job

- setuo and hold equation

- what if capture flops clock is inverted ?

- what happend during clock domain crossing ?

- how to do bus synchronization?

- what if valid signal is stable and data is changing during bus synch ??

7th round

- architect

- 1 hour- few questoins from profile

- basic about state machine and digital truith table- write SM code

- what happen if 2 inputs of mux are 1 .. but select is toggling ?

- optimiza FSM code ..- latch based design ? ever worked oni t ?- write counter design

- how do we make it using latch ?

- any 2 wire commmunication protocol .. like REQ and ACK ..

- explain AHB protocol

- drwan some flops and clocks and made some connection and asked me to do STA

- why to have reset ?? non-reetable flops are okay ?


3/5

8th round

- some BIG BOSS- around 30 mins

- all HR related questiuns

- like what does integrity and ethics mean to you?

- how do you interact with US people?- strengths ? and where u want to improve ?

- after 5 years where will u be ?

- what extra do you do?

- what kind of books u read and tell some learning from it ..

- why r u leaving ... and why only .............. (:-)) .. why not qualcomm, etc ...

9th round:

- 40 mins

- some PD engineer

- what is power saving tachniques- cell delay calulation

- clock gating- explain ..

- dran ckt and told me to reduce its power- what is state retention?

- how does power islands work?- state machince code ..

- problem in verilo code he had written ..

- blocking non-blocking


4/5


5/5

- top down or bottom up? complexity ? percentage wise how much on verification and howmuch on design?

- design -> edge detector- ramdom, verification, task and function

- task based environment

- rate your self

-

- RC and EP connection, software perspecive, verilog delays, intra and inter assignment

delay, wire and cell delay, FPGA debugging, how do u come to conclusion, FPGA design

flow

- lane and link, hex and binary and decimal and BCD conversion, BAR reading, enumeration,

BDF, CPL boundary, 1K of data in one completion? , multiple completion allowed?, max

payload size, max read request size, RCB ?? ,

- design, verilog, 4 bytes by 4 bytes than pack them into 8 bytes, write verilog code

- simulation dependancies, blocking and non-blocking assignments, graph etc, counter codeand block diagram

- expectation, why to leave- lunch

- if reset is given, not given, sensitivity list is incomplete, VHDL configuration, VHDL flop

derivation- digital, MUX, no of muxes, 8 to 1 mux from 2 to 1, how many muxes is required, LUT,

RAM, FPGA architect

- type of paths, clock gating, recently faced and solved issue, clock domain crossing, and

why? , buffer characteristics, p&r,

- why to leave, strong reason, why did u join tforce, expectation,

- experience in various domains

- design, what design, why only in this way?, randomization, constrained rabdomization,

pulse stretcher,

- memory verif, interrupt verif, arbiter verif,

- sync flops, muti cycle, fasle, same path both violation,

interviewquentions

Documents