interrupting the fault current by the...

International Journal of Science, Engineering and Technology Research, Volume 3, Issue 9, September 2014

ISSN: 2278 – 7798 All Rights Reserved © 2014 IJSETR 2495

INTERRUPTING THE FAULT CURRENT BY THE DVR

Mr. D. Ramakrishna Mrs. S. B. ArunaM. Tech Student, Dept. of EEE Assistant Professor, Dept. of EEE

Sree Vidyanikethan Engg. College, Tirupati Sree Vidyanikethan Engg. College, Tirupati

Abstract - The paper presents a control scheme for the purpose of interrupting the fault current by the DVR (Dynamic Voltage Restorer) which is present on down-stream side of the DVR. The control scheme provides compensation for the voltage sags. PLL is not required in this scheme and it can control the magnitude and phase angle of the injected voltage independently. To estimate the magnitude and phase of the measured voltages, FLES digital filters are used. These are capable of to reduce the impacts of noise and harmonics. The simulation is performed in the MATLAB/simulink software. The proposed scheme i) can interrupt the fault current within two cycles ii) limits the dc link voltage rise so that no restrictions iii)gives satisfactory operation under arcing fault conditions also iv) can interrupt the fault current under low dc link voltage conditions.

1. INTRODUCTION

DVR is used to counteract voltage sags by injecting controlled three-phase ac voltages in series with the supply voltage and to enhance the quality of voltage by adjusting voltage magnitude, wave shape and phase angle [3]-[6]. In general, DVR is bypassed during down-stream fault in order to protect the components of the DVR against the high fault currents [9]-[11].

A control scheme for DVR to function as fault current limiter is provided in [9]. The main drawback of this scheme is that the dc link voltage rise due to real power absorption. The dc link voltage rise can be mitigated at the cost of a slow decaying dc fault current component using the methods proposed in [7] and [12].

To overcome the limitations which are mentioned above, this paper introduces a control strategy for DVR such that voltage sag compensation under balanced and unbalanced conditions and a function of interrupting the fault current. The former function has been presented in [13] and the latter is in this paper. Limiting fault current by the DVR disables the main and backup protection (e.g. over current relay). This can result in prolonging the duration fault. Thus, it is preferred to reduce the fault current to zero and send a trip signal to the upstream relay.

FCI function requires 100% voltage injection capability. Thus, power ratings of the series transformer and the VSC would be three times the conventional DVR. This would result in more expensive DVR system. Economic feasibility of such a DVR depends on the importance of the load protected by the DVR and the cost of DVR itself. The performance of the proposed control strategy is evaluated through simulation in MATLAB/Simulink. The results indicate that the proposed scheme i) can interrupt the fault current within two


ISSN: 2278 – 7798 All Rights Reserved © 2014 IJSETR

cycles ii) limits the dc link voltage rise so that no restrictions iii)gives satisfactory operation under arcing fault conditions also iv) can interrupt the fault current under low dc link voltage conditions.

2. THE CONTROL SCHEME

The DVR converter consists of three independent H-bridge VSCs that are connected to a common dc link capacitor. These VSCs are connected in series to the supply grid. The control scheme consists of three independent and identical controllers’ one for each VSC of the DVR. Assume supply voltage vs = Vs

load voltage vl = Vl injected voltage vinj= vl-vs = Vinj

For the estimation of magnitudes and phase angles of the phasors corresponding to vand vinj, two identical least error squares filters are used.

The digital filter acts as a phasor parameter estimator and attenuates the harmonic contents of the measured signal. For the attenuation of all harmonics, the filter must have a full cycle data window which leads to one cycle delay in the DVR response. Thus, an appropriate compromise between voltage injection speed and disturbance attenuation is made. The filter utilize a data window of 50 samples at the sampling rate of 10 kHz and hence, estimate the voltage phasor parameters in 5 ms. Ref. [13] illustrates the effectiveness of this filter in attenuating the noise, harmonics, distortions and sag compensation mode. The present paper shows that this filter also performs satisfactorily in the FCI mode, even under arcing fault conditions where the


7798 All Rights Reserved © 2014 IJSETR

imits the dc link voltage rise so that no restrictions iii)gives satisfactory operation under arcing fault conditions also iv) can interrupt the fault current under low

THE CONTROL SCHEME

The DVR converter consists of three bridge VSCs that are

connected to a common dc link capacitor. These VSCs are connected in series to the supply grid. The control scheme consists of three independent and identical controllers’ one for each VSC of the DVR.

cos(ωt+θs)

cos(ωt+θl) cos(ωt+θinj)

For the estimation of magnitudes and phase corresponding to vs

, two identical least error squares

The digital filter acts as a phasor parameter estimator and attenuates the harmonic contents of the measured signal. For the attenuation of all harmonics, the

ve a full cycle data window which leads to one cycle delay in the DVR response. Thus, an appropriate compromise between voltage injection speed and disturbance attenuation is made. The filter utilize a data window of 50 samples at the

Hz and hence, estimate the voltage phasor parameters in 5 ms. Ref. [13] illustrates the effectiveness of this filter in attenuating the noise, harmonics, distortions and sag compensation mode. The present paper shows that this filter also

torily in the FCI mode, even under arcing fault conditions where the

measured voltage and current signals are highly distorted.

Fig. 1 Block diagram of the control scheme

Fig.1 shows per-phase block diagram of the proposed DVR control system corresponding to the FCI operation mode. Vnis the nominal rms phase voltage. The fault detection mechanism for each phase is activated when the absolute value of the instantaneous current exceeds twice the rated load current.

The multi-loop control system [8], [9], [15]-[20] includes an outer loop (voltage phasor control) and the inner control loop (instantaneous voltage control). The inner loop provides damping for transients caused by the harmonic filter [18] and [21], and improves the dynamic behavior and stability of the DVR. The inner loop shared by the sag compensation and the FCI mode of function. During a downstream fault, the outer loop controls the magnitude and phase angle of injected voltage for the faulty phase(s) and reduces the voltage at load side to zero, to interrupt the fault current and restore the PCC voltage.


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measured voltage and current signals are

Fig. 1 Block diagram of the control scheme

phase block diagram of the proposed DVR control system corresponding to the FCI operation mode.

is the nominal rms phase voltage. The fault detection mechanism for each phase is activated when the absolute value of the instantaneous current exceeds twice the

loop control system [3], [20] includes an outer loop

(voltage phasor control) and the inner control loop (instantaneous voltage control). The inner loop provides damping for transients caused by the harmonic filter [18] and [21], and improves the dynamic

or and stability of the DVR. The inner loop shared by the sag compensation and the FCI mode of function. During a down-stream fault, the outer loop controls the magnitude and phase angle of injected voltage for the faulty phase(s) and reduces

t load side to zero, to interrupt the fault current and restore the PCC



2.1 Voltage phasor control system

In the FCI operation mode, the required injected voltage phasor is equal to the source voltage phasor but in phase opposition. The performance in terms of transient response, speed and steady-state error is enhanced by independent control of the magnitude and phase. The steady-state errors of magnitude and phase of the injected voltage can be eliminated by using two PI controllers (C1 and C2). Parameters of each controller are determined to achieve a fast response with zero steady-state error. The output of voltage phasor control system is a reference phasor V*inj.The magnitude and phase angle of V*inj are independently calculated and passed through a limiter. The resulting magnitude and phase angle are converted to the sinusoidal signal V*inj and is given as a reference signal to the instantaneous voltage control.

2.2 Instantaneous voltage control system

Under ideal conditions, voltage sag compensation is done if the output of the output of the phasor based controller V*inj is directly fed to the SPWM unit. However, resonances of harmonic filter can’t be eliminated. Therefore, to improve dynamic response and stability of the DVR, an instantaneous injected voltage controller and a harmonic filter capacitor current controller are used to attenuate resonances. The generated reference signal V*inj is compared with the measured injected voltage Vinj and the error is fed to the voltage controller. The output of the voltage controller i*cap acts as a reference signal for the filter capacitor current control loop. This i*cap is compared with the measured capacitor current icap, and error is fed to the current controller. The

steady state error of the system is fully eliminated by the PI controller in the outer control loop. Therefore, there is no need for higher order controllers in the inner control loop. If a large value of kv is used, it results in amplification of the DVR filter resonance and has adverse impact on the system stability [18]. Thus, the transient response of the DVR is enhanced by feed forward loop and a small proportional gain is utilized as the voltage controller. A large kc damps the harmonic resonance but it is limited by practical considerations. Therefore the lowest value of the proportional gain which can effectively damp the resonances is used. The output of the current controller is added to the feed forward voltage to derive the signal for the PWM generator.

In FCI mode, the injected voltage phasor should be equal to the source voltage phasor but in opposite direction.The voltage phasor control block consists of two PI controllers(C1 and C2) that are used to eliminate steady state errors of the magnitude and phase of the injected voltage. The output phasor of this block is V*(inj). To make the injected voltages free from the effect of dc-link voltage variations, V*(inj)

normalized by Vdc. Ideally voltage sag can be compensated effectively if the output of voltage phasor control is directly fed to the sinusoidal pulse width modulation(SPWM) unit. However, resonances of harmonic filter can’t be eliminated.Therefore to improve transient stability and dynamic response of DVR, an instantaneous injected voltage controller and a harmonic filter capacitor current controller are used to attenuate resonances. The generated reference signal for V*(inj) is compared with the measured



injected voltage V(inj) and error is given to voltage controller.

3. STUDY RESULTS

Fig. 2 represents a sdiagram of the test system which is used to evaluate the performance of the proposedDVR control systedifferent fault conditions, in theMATLAB/Simulink software. A 525DVRsystem is installed on the 0.4feeder, to protect a 500-kVA,0.90 lagging power factor load against voltage sags.

Fig. 2 Single-line diagram of the test system

Parameters of the simulated power systemare

TABLE 1 TRANSFORMER SPECIFICATIONS

TABLE 2 VSC PARAMETERS



and error is given to

a single-line which is used to

evaluate the performance of the proposedDVR control system under

s, in the. A 525-kVA

DVRsystem is installed on the 0.4-kV ,0.90 lagging

power factor load against voltage sags.

line diagram of the test system

d power systemare

TRANSFORMER

Specifications of the power system

Short circuit current at BusX/R at BusLength of transmission line = 4 km 1.876 Ω, Lline = 0.0774 H Cable length = 150 m9.6 mΩ , Lcable

Load = 400kW, 300kVAR

Fig. 3 Simulink model of the test system

The simulink model of the test system with incorporating DVR is as shown in fig. 3.


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Specifications of the power system

Short circuit current at Bus1= 31.5 kA X/R at Bus1= 5.67 Length of transmission line = 4 km Rline =

= 0.0774 H Rcable =

= 340 mH

Fig. 3 Simulink model of the test system

The simulink model of the test system with own in fig. 3.



Fig. 4 a) Voltages at bus3 b) fault currents, during 3phase fault when DVR is bypassed

3.1Three-Phase Downstream Fault The system is subjected to a three

short circuit fault with a fault resistance approximately equal to zero at t = 20 ms as shown in fig. 3.Before the occurrence of the fault, the DVR is inactive.During the fault if the DVR is bypassed, the voltage at Bus3 drops to 0.77p.u.and the fault current risesabout 17 times the rated load current.voltage at bus3 and current waveforms during three phase fault (when the DVR is inactive) is shown in the fig 4. Fig. 5FCI performance of the proposed DVR control system during the fault. Fig. 5(a)shows the three-phase injected voltages, the restored three-phase supply-side voltages, and the three-phase load-side voltages respectively. It is clear from fig. 5(c) that tthree-phase load-side voltages are reduced to zero to interrupt the fault currents. The slightly injected voltage by the DVR befthe fault occurrence [Fig. 5(a)] is the voltage drop across the series impedance of the DVR series transformer secondary winding. Fig. 5(d) shows the line currents (i.e., the currents flowingthrough the DVR) andillustrates that the proposed method limits the maximum fault current to about 2.times the rated load current and interrupts the fault currents in less than 2 cycles. Fig. 5(e) illustrates the variations of the dcvoltage during the FCI mode, and indicatesthat the dc-link voltage rise under the worst case (i.e., a severe three phase fault) is about

a)

b)



b) fault currents, during 3-

Phase Downstream Fault The system is subjected to a three-phase

a fault resistance at t = 20 ms as

Before the occurrence of the , the DVR is inactive.During the fault if

d, the voltage at Bus3 and the fault current rises to

es the rated load current.The and current waveforms

during three phase fault (when the DVR is inactive) is shown in the fig 4. Fig. 5 shows FCI performance of the proposed DVR

fault. Fig. 5(a)–(c)hase injected voltages, the

side voltages, side voltages

respectively. It is clear from fig. 5(c) that the side voltages are reduced

to zero to interrupt the fault currents. The injected voltage by the DVR before

(a)] is the voltage drop across the series impedance of the DVR series transformer secondary winding.

ents (i.e., the currents flowingthrough the DVR) and

method limits the maximum fault current to about 2.5

load current and interrupts in less than 2 cycles. Fig.

variations of the dc-link , and indicates

link voltage rise under the worst case (i.e., a severe three phase fault) is about

15% and occurs during the first 5 ms after fault inception.

Fig. 5 (a) Injected voltages. (b) Source voltages. (c) Load voltages. (d) Line currents. (e) DCduring the three-phase downstream fault.active)

Fig. 6 (a) Voltages at bus3 , (b) Fault currents, during downstream phase-tophasefault when the DVR is inactive (bypassed).

3.2Line - Line Downstream Faults

The system is subjected to a phasephase-Cfault with the resistance of 0.05

a)

b)

c)

d)

e)

a)

b)


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15% and occurs during the first 5 ms after

Injected voltages. (b) Source voltages. (c) Load voltages. (d) Line currents. (e) DC-link voltage,

phase downstream fault. (DVR is

, (b) Fault currents, during tophasefault when the DVR is

Line Downstream Faults

is subjected to a phase-A to Cfault with the resistance of 0.05 Ω,



at 20 ms. When the DVR is inactive during the fault (Fig. 6), the voltage at bus0.88 p.u., and the fault current incrabout 11times the nominal value of thecurrent. Fig. 7 illustrates that when the DVR is in service, the proposedcontrol successfully interrupts the fault current andrestores the PCC voltage of the faulty phases within two cycles. Fig. 7that the dc-link voltage rise is les

Fig. 7 (a)Injected voltages. (b) Source voltages. (c) Load voltages. (d) Linecurrents. (e) DCduring the phase-to-phase downstream fault.

3.3Line – to - Ground Downstream Fault

Phase-A of the system is subjected to a fault withthe resistance of 0.2length of the cable, at t = 20 ms. If the DVR is inactive (Fig. 8), the voltage drop at PCC (bus3) is not much and the fault current

a)

b)

c)

d)

e)



inactive during at bus3drops to

0.88 p.u., and the fault current increases to about 11times the nominal value of the load

illustrates that when the DVR is in service, the proposedcontrol scheme successfully interrupts the fault current

voltage of the faulty Fig. 7(e) shows

link voltage rise is less than 7%.

a)Injected voltages. (b) Source voltages. (c) Load voltages. (d) Linecurrents. (e) DC-link voltage,

phase downstream fault.

Ground Downstream

is subjected to a fault withthe resistance of 0.2Ω at 10%

. If the DVR is inactive (Fig. 8), the voltage drop at PCC

and the fault current

isabout 2.5 p.u. Though the PCC voltagedrop is not considerable, the fault current must be interruptedby the DVR to prevent possible damages to the VSC before thefault is interrupted by the relays. Becausethe operationtime of the overcurrent relays is considerable for a fault currentof about 2.5 p.u.

Fig. 9 illustrates that the proposed DVR control scheme successfully interrupts the fault current in the faulty phase within two cycles. Fig. 9(e) shows that the dcvoltage rises less than 1.8%. From fig. 9it is clear that only the faulty phase ofthe DVR reacts to fault current, and the healthy phases are notinterrupted.

Simulation study made a conclusionthe dc-link voltage risecaused by thproposed FCI mode is proportionalto the fault current, and depends on the typfault. The resultsalso indicate that the maximum dc-link voltage rise occursthe most severe three-phase fault which is about 15%,and can be tolerated based on DVR appropriate design. It shouldthat to prevent operation of threeinductionmotors under unbalanced voltage conditions, they mustbe equipped with protective devices which detect such conditionsand disconnect the load when any of the phases is de-energizedby the singlephase operation of the FCI function.


2500

hough the PCC is not considerable, the fault

current must be interruptedby the DVR to prevent possible damages to the VSC before

y the relays. Becausethe operationtime of the overcurrent relays is considerable for a fault currentof about 2.5

he proposed DVR successfully interrupts the

t current in the faulty phase within two (e) shows that the dc-link

less than 1.8%. From fig. 9it is only the faulty phase ofthe DVR

reacts to fault current, and the healthy

Simulation study made a conclusion that link voltage risecaused by the

is proportionalto the fault current, and depends on the type of fault. The resultsalso indicate that the

link voltage rise occursunder phase fault which is

about 15%,and can be tolerated based on It should be noted

that to prevent operation of three-phase nductionmotors under unbalanced voltage

conditions, they mustbe equipped with protective devices which detect such conditionsand disconnect the load when any

energizedby the single-phase operation of the FCI function.



Fig. 8 (a) Voltages at bus3. (b) Fault currents, during the downstream single phase-to-groundthe DVR is inactive (bypassed).

Fig. 9 (a)Injected voltages. (b) Source voltages. (c) Load voltages. (d) Linecurrents. (e) DCduring the phase-to-ground downstream fault.

4. CONCLUSION

This paper introduces an auxiliary control scheme to have an additional function for the DVR to interrupt downstream fault currents in a radial feeder. This control function is an addition tothe voltage-sag compensation control of the DVR. The performanceof the proposed controller, under different fault conditions is

a)

b)

a)

b)

c)

d)

e)



. (b) Fault currents, during ground fault when

(a)Injected voltages. (b) Source voltages. (c) Linecurrents. (e) DC-link voltage,

downstream fault.

s an auxiliary control scheme to have an additional

the DVR to interrupt downstream fault currents in a radial feeder.

function is an addition tothe sag compensation control of the

DVR. The performanceof the proposed under different fault conditions is

investigated on time-domain in the MATLAB/simulink environment.The study results conclude that: the proposed control scheme

provides a desirable transient response and steadyperformance and effectively damps the potential resonant oscillations caused by the LC harmonic filter the DVR;

the proposed control strategyand effectively interrupts the various downstream fault currents within two cycles (of 50 Hz);

the proposed fault current interruption strategy limits theDVR dc-link voltage rise, caused by active power absorption,to less than 15% and enables the DVR to restorethe PCC voltage without interruption; in addition, it interruptsthe downstream fault currents even under low dclinkvoltage conditions.

5. REFERENCES

[1] N. G. Hingorani, “Introducing custom power,” IEEE Spectr.32, no. 6, pp. 41–48, Jun. 1995.

[2] J. G. Nielsen, F. Blaabjerg, and N. Mohan, “Control strategies for dynamic voltage restorer compensating voltage sags with phase jump,” in Proc. IEEE APEC’2001, pp. 1267–1273.

[3] G. J. Li, X. P. Zhang, S. S. T. Lie, and Y. Z. Sun, “Control strategy for dynamic voltage restorers to achieve minimum power injection without introducing sudden phase shift,” Inst. Eng. Technol. Gen. Transm. Distrib., vol. 1, no. 5, pp. 847–853, 2007.

[4] S. S. Choi, B. H. Vilathgamuwa, “Design and analysis of the inverter-side filter used in the dynamic voltage restorer,”


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domain in the environment.The study

roposed control schemeprovides a desirable transient response and steady-state performance and effectively damps the potential resonant oscillations caused by the LC harmonic filter of

the proposed control strategy detects and effectively interrupts the various downstream fault currents within two

the proposed fault current interruption strategy limits theDVR

link voltage rise, caused by active power absorption,to less than 15%

DVR to restorethe PCC voltage without interruption; in addition, it interruptsthe downstream fault currents even under low dc-linkvoltage conditions.

N. G. Hingorani, “Introducing IEEE Spectr., vol. 48, Jun. 1995.

J. G. Nielsen, F. Blaabjerg, and N. Mohan, “Control strategies for dynamic voltage restorer compensating voltage sags with

Proc. IEEE APEC’, 1273.

G. J. Li, X. P. Zhang, S. S. Choi, T. T. Lie, and Y. Z. Sun, “Control strategy for dynamic voltage restorers to achieve minimum power injection without introducing sudden

Inst. Eng. Technol. Gen. , vol. 1, no. 5, pp.

S. S. Choi, B. H. Li, and D. M. Vilathgamuwa, “Design and analysis

side filter used in the dynamic voltage restorer,” IEEE



Trans. Power Del., vol. 17, no. 3, pp. 857–864, Jul. 2002.

[5] B. H. Li, S. S. Choi, and D. M. Vilathgamuwa, “Design considerations on the line-side filter used in the dynamic voltage restorer,” Proc. Inst. Elect. Eng., Gen. Transm Distrib., vol. 148, no. 1, pp. 1–7, Jan. 2001.

[6] S. S. Choi, B. H. Li, and D. M. Vilathgamuwa, “Dynamic voltage restoration with minimumenergy injection,” IEEE Trans. Power. Syst., vol. 15, no. 1, pp. 51–57, Feb. 2000.

[7] D. M. Vilathgamuwa, P. C. Loh, and Y. Li, “Protection of microg rids during utility voltage sags,” IEEE Trans. Ind. Electron., vol. 53, no. 5, pp. 1427–1436, Oct. 2006.

[8] Y. W. Li, D. M. Vilathgamuwa, F. Blaabjerg, and P. C. Loh, “A Robust control scheme for medium-voltage-level DVR implementation,” IEEE Trans. Ind. Electron., vol. 54, no. 4, pp. 2249–2261, Aug. 2007.

[9] B. Delfino, F. Fornari, and R. Procopio, “An effective SSC control scheme for voltage sag compensation,” IEEE Trans. Power Del., vol. 20, no. 3, pp. 2100–2107, Jul. 2005.

[10] S. S. Choi, T. X. Wang, and D.M.Vilathgamuwa, “A series compensator with fault current limiting function,” IEEE Trans. Power Del., vol. 20, no. 3, pp. 2248–2256, Jul. 2005.

[11] C. Zhan, V. K. Ramachandaramurthy, A. Arulampalam, C. Fitzer, S. Kromlidis, M. Barnes, and N. Jenkins, “Dynamic voltage restorer based on voltage-space-vector PWM control,” IEEE Trans. Ind. Appl., vol. 37, no. 6, pp. 1855–1863, Nov./Dec. 2001.

[12] Y. W. Li, D.M. Vilathgamuwa, P. C. Loh, and F. Blaabjerg, “A

dualfunctional medium voltage level DVR to limit downstream fault currents,” IEEE Trans. Power. Electron., vol. 22, no. 4, pp. 1330–1340, Jul. 2007.

[13] F. BadrkhaniAjaei, S. Afsharnia, A. Kahrobaeian, and S. Farhangi “A fast and effective control scheme for the dynamic voltage restorer,” IEEE Trans. Power Del., vol. 26, no. 4, pp. 2398–2406, Oct. 2011.

[14] M. S. Sachdev and M. A. Barlbeau, “A new algorithm for digital impedance relays,” IEEE Trans. Power App., Syst., vol. PAS-98, no. 6, pp. 2232–2240, Nov./Dec. 1979.

[15] S. R. Naidu and D. A. Fernandes, “Dynamic voltage restorer based on a four-leg voltage source converter,” Inst. Eng. Technol. Gen. Transm Distrib., vol. 3, no. 5, pp. 437–447.

[16] D. M. Vilathgamuwa, H. M. Wijekoon, and S. S. Choi, “A novel technique to compensate voltage sags in multiline distribution system—the interline dynamic voltage restorer,” IEEE Trans. Ind. Electron., vol. 53, no. 5, pp. 1603–1611, Oct. 2006.

[17] D.M. Vilathgamuwa, A. A. D. R. Perera, and S. S. Choi, “Voltage sag compensation with energy optimized dynamic voltage restorer,” IEEE Trans. Power Del., vol. 18, no. 3, pp. 928–936, Jul. 2003.

[18] Y.W. Li, F. Blaabjerg, D. M. Vilathgamuwa, and P. C. Loh, “Design and comparison of high performance stationary-frame controllers for DVR implementation,” IEEE Trans. Power. Electron., vol. 22, no. 2, pp. 602–612, Mar. 2007.

[19] H. Kim and S. Sul, “Compensation voltage control in dynamic voltage restorers by use of feed forward and state feedback scheme,” IEEE



Trans.Power Electron., vol. 20, no. 5, pp. 1169–1177, Sep. 2005.

[20] B. Wang, G. Venkataramanan, and M. Illindala, “Operation and control of a dynamic voltage restorer using transformer coupled H-bridge converters,” IEEE Trans. Ind. Electron., vol. 21, no. 4, pp. 1053–1061, Jul. 2006.

[21] M. J. Newman, D. G. Holmes, J. G. Nielsen, and F. Blaabjerg, “A Dynamic Voltage Restorer (DVR) with selective harmonic compensation at medium voltage level,” IEEE Trans. Ind. Appl., vol. 41, no. 6, pp. 1744–1753, Nov./Dec. 2005.

[22] J. G. Nielsen, H. Nielsen, and F. Blaabjerg, “Control and test of dynamic voltage restorer on the medium voltage grid,” in Proc. 38th Ind. Appl. Conf., Ind. Appl. Soc. Annu. Meeting, 2003, pp. 948–955.

[23] J. G. Nielsen, M. Newman, H. Nielsen, and F. Blaabjerg, “Control and testing of a Dynamic Voltage Restorer (DVR) at medium voltage level,” IEEE Trans. Power. Electron., vol. 19, no. 3, pp. 806–813, May 2004.

[24] D.M.Vilathgamuwa, A. A. D. R. Perera, and S. S. Choi, “Performance improvement of the dynamic voltage restorer with closed-loop load voltage and current-mode control,” IEEE Trans. Power. Electron., vol. 17, no. 5, pp. 824–834, Sep. 2002.

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