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EEL 4744C: Microprocessor Applications

Lecture 7

Part 1

Interrupt

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• M&M: Chapter 8 Or• Software and Hardware Engineering (new

version): Chapter 12

Reading Assignment

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• An interrupt is an important asynchronous event thatneeds to be recognized and dealt with by the CPU thatis executing instructions in a program

• You can keep polling the external devices, e.g. sensors,detectors, etc. But doing this periodically takes timeaway from your system and reduce overall performance

• Use interrupts! Your external sensor, when it detectssomething peculiar, generates a signal called interruptrequest, i.e. IRQ

Interrupt

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• An interrupt is an important asynchronous event thatneeds to be recognized and dealt with by the CPU thatis executing instructions in a program

• You can keep polling the external devices, e.g. sensors,detectors, etc. But doing this periodically takes timeaway from your system and reduce overall performance

• Use interrupts! Your external sensor, when it detectssomething peculiar, generates a signal called interruptrequest, i.e. IRQ

Interrupt

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• The IRQ is asynchronous, i.e. the time it happens hasno relation to the instructions being executed by theCPU

• The IRQ requires an ISR, or interrupt service routine, tobe executed immediately. The ISR should be part of therunning program

• Interrupts can also be used to synchronize a real-timesystem to control exactly when things are performed bythe system, e.g. A/D IRQ to CPU signaling completion ofA-to-D conversion

Interrupt

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• Allow for asynchronous events to occur and berecognized

• Wait for the current instruction to finish before takingcare of any interrupt

• Branch to the correct ISR to service the external devicethat issued the IRQ

• Return to the interrupted program where it wasinterrupted

• Allow for a variety of interrupting signals, includingsignal levels and edges (rising/falling)

• Signal the interrupting device with ACK signal when itsIRQ is recognized

Interrupt System Specifications

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• Allow the programmer to selectively enable and disableall interrupts

• Allow the programmer to selectively enable and disableselected interrupts

• Disable further interrupts while the first is beingserviced

• Deal with multiple sources of interrupts

• Deal with multiple simultaneous interrupts

Interrupt System Specifications

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• ISR is executed when an IRQ occurs

Process Control with Interrupts

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• The sequence controller can be modified to check foran IRQ before fetching the next instruction

• More states can be added to the sequential statemachine to cover IRQ sampling, IRQ ACK, etc.

Interrupts and Sequence Control

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• IRQ is usually active low, and many IRQ’s are oftenwire-ORed together

• An IRQ flip-flop (IRQ-FF) is used to “catch” and“remember” an IRQ until the CPU gets a chance toacknowledge and service it

• When IRQ-FF is set, it generates a signal for thepending interrupt (a.k.a. the IRQ that has not been actedupon). This signal is sent toward the sequencecontroller

Interrupt Hardware

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• The IRQ-FF is reset when it receives the INTA (a.k.a.interrupt acknowledge) signal from CPU

• The interrupt enable flip-flop (INTE-FF) allows theprogrammer to enable or disable interrupts withprogram instructions

• Setting the INTE-FF enables interrupts through the ANDgate. When the INTE-FF is reset, all interrupts areblocked. Input signals of the 2 OR gates give theconditions to reset the INTE-FF

Interrupt Hardware

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• The CPU generates an interrupt acknowledge(INTA) signal when: (1) the current instructionhas finished execution and (2) CPU hasdetected the IRQ

• INTA tells the interrupting device that the CPUis ready to execute the ISR

• Upon completion the ISR, the CPU executes thereturn-from-interrupt instruction

• Can you have interrupts interrupting interrupts?

Interrupt Hardware

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Interrupt Recognition andAcknowledgement Hardware

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• Determine which device generated the IRQ in order toexecute the correct ISR

• Prioritize simultaneous IRQ’s

Multiple Interrupt Sources

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• A software process where CPU reads each of thepotential interrupting device’s status register to find thedevice that generated the IRQ

Interrupt Polling

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• A vector, in this case, is an address, the address of theISR to be executed

• In response to the CPU’s INTA signal, the device placesa “vector” onto the data bus for the CPU to read. Thisvector identifies the device itself

• Can also have multiple IRQ input pins on CPU, each pinwith its own memory locations for a vector dedicated toeach IRQ signal

• Faster than polling, but needs more hardware

Vectored Interrupts

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Vectored Interrupts

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• Use a mask register to enable a specific IRQ

Multiple Interrupt Masking

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• Sequential: A pending IRQ prevents furtherinterrupts from being recognized by CPU sinceINTA resets the INTE-FF

• Nested interrupts: Programmers can enable thisby including the “enable interrupt instruction”within the ISR

• The program has to keep track of the status ofINTE-FF, re-enabling the FF if necessary at theend of the current ISR

Sequential vs. Nested Interrupts

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• Software priority resolution: Polling order fixesthe priority for each device. So a lower-prioritydevice must keep asserting its IRQ until it isrecognized and serviced

• Hardware priority resolution: Required forvectored interrupts, several methods possible

• Daisy chain: Similar to that used for parallel I/O

• Separate IRQ lines: IRQ0 > IRQ1 > IRQ2 > …

Prioritizing Simultaneous IRQs

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• Hierarchical prioritization: Based on a hierarchy of high-to low-priority IRQs

• Nonmaskable interrupts: These are reserved for criticalevents, e.g. power failure, that must not be masked (i.e.disabled). Usually this requires an IRQ line that is notaccessible by programmers

• Programmable interrupt controllers: Can resolve IRQpriorities and be programmed to generate a vector forseveral interrupting sources. For example, the MotorolaMC6828

Prioritizing Simultaneous IRQs

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• Context saving: Before executing the ISR, the CPUpushes all the register and flag values onto the stack

• Interrupt latency: The delay from when the IRQ isgenerated to when the ISR begins to execute

• This depends on many factors, e.g. length of the currentinstruction, amount of data pushed onto the stack,existence of a higher-priority IRQ and its correspondingISR that must be finished first

Transfer of Control to ISR

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• Minimize the amount of data pushed onto the stack, anddon’t modify any registers or flags in the ISR

• Re-enable or unmask interrupts at the end of the ISR ifthis is not automatically done by the CPU

• Restore registers if this is not automatically done

• Use the proper ISR return instruction

• Keep the ISR short!

Tips on ISR Design

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• An ISR return is different from a normal subroutinereturn, because this return instruction needs to performother interrupt-related tasks. For example, we have RTSand RTI

ISR Return

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• Nonmaskable interrupts (NMI): For example, apower failure NMI is asserted before the powersupply voltage goes down to 0. Then, using thevery little time left, the CPU runs a small ISRsaving critical data to nonvolatile memory!

• Software interrupts (SWI): An instruction thatactivates interrupt processing without an IRQ

• SWI is frequently used for breakpointinstructions in debuggers

Some IRQ Signals

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• Exceptions: Occurs during run time, e.g.internal bus errors, division by zero, etc. Theprogrammer can supply an ISR dealing with anexception

• Reset: CPU reset, nonmaskable, done through asignal asserted on a separate pin

Some IRQ Signals