interoperability panel applications of interoperable databases and datamodel in production flows edp...

Interoperability PanelInteroperability PanelApplications of interoperable Applications of interoperable databases and datamodel in databases and datamodel in

production flowsproduction flows

EDP 2004EDP 2004

April 26, 2004April 26, 2004

AgendaAgenda

Introduction Introduction Panel Chair - Aparna Dey - Business Panel Chair - Aparna Dey - Business

Development Director, Cadence Development Director, Cadence Presentations by Panelists – 30 mins eachPresentations by Panelists – 30 mins each

Jim Wilmore- Architect, HP Jim Wilmore- Architect, HP Noel Strader – Marketing Manager, SynopsysNoel Strader – Marketing Manager, SynopsysScott Peterson – Director, LSI LogicScott Peterson – Director, LSI Logic

Q &A – 30 minutesQ &A – 30 minutes

Building a 21st CenturyIC Design System on OpenAccess Technologyat Hewlett-Packard

Jim WilmoreHP/Systems VLSI & Technology DivisionApril 26, 2004

...

EDA Environment at HP - Background

• Microprocessor and high-end chipset development– Significant amount of custom design work– Pushing performance to edge of next-generation

process

• Long-standing investment in internal infrastructure– Proprietary database, API, and Information Model– Capacity and performance tuned for HP design system

and methodology– Allows quick and effective response to critical design

issues

• Long history of CAD Integration for our designers

...

IC Designer

Supplies Tool to :

Tool Developer

H

EDA Systems Delivery

Mass MarketTool Developer

Special Application

Tool DeveloperSupplies Tool to : Supplies Tool to :

The Evolution of CAD Roles

...

FrameworkDeveloper

Supplies Framework to :

and Tool

^CAD User

CAD User

H



Special Application



...

FrameworkDeveloper


LibraryDeveloper

Supplies Library to :

H



Special Application



...

FrameworkDeveloper


LibraryDeveloper


CAD User

CAD System Builder

(a.k.a. the CAD Integrator)

H



Special Application



...

FrameworkDeveloper


LibraryDeveloper


CAD User

CAD System Builder


CAD SystemAdministrator

Supplies Production System to :

Supplies Site SpecificProduction System to :

H


...


Special Application


FrameworkDeveloper


LibraryDeveloper


CAD User

CAD System Builder


CAD SystemAdministrator

Supplies Production System to :

Supplies Site SpecificProduction System to :

Contributes toMethodology

Definition

Supports ProductionSystem for :

The Design System 'Food Chain’

H


...

CAD User

CAD System Builder



Definition


Design System 'Food Chain’

SupportIs Our Most Important

Product

EDA Environment at HP - Background

• Microprocessor and high-end chipset development– Significant amount of custom design work– Pushing performance to edge of next-generation

process

• Long-standing investment in internal infrastructure– Proprietary database, API, and information model– Capacity and performance tuned for HP design

system and methodology– Responsiveness to critical design issues

• Key HP IC-CAD system attributes for excellent support– Fine-grained control of the system and its

components– Robust, efficient API access to design data

...

Proprietary APIs…Proprietary DBs…


CommercialEDA Tools

CommercialEDA Tools

CommercialEDA Tools

CommercialEDA Tools

HP InternalTools

HP InternalTools

HP InternalTools

HP InternalTools

HP Design Environment

HP APIHP DB

HP db

HP InternalTools

HP InternalTools

Readers/Writers

Readers/Writers

Data Files


Persistence/Data

exchange

CommercialEDA Tools

CommercialEDA Tools

dbs

ScriptsScripts

...

- Current Architecture

Driving Factors for Change - The need for OpenAccess

• Create best-in-class flows:– Reduce new tool integration cost– Reduce new tool evaluation cost

• Redirect HP’s current Infrastructure investment– Higher value-add infrastructure and components

• Higher productivity via tighter integration– Migrate toward interoperability model

• Finer grained components/engines on shared run-time data

• Essential to address complexities of nanometer design• Reduce number of design iterations

...

Timing

H

Design Loops

...

in nanometer designs

Route

PowerNoise

EM/SIERC

Analysis

ParasiticExtract

Achieving Interoperability - CAD System Architectural Vision

OA db

HP Automation

Data Files

Data Files

OpenAcess(In-Memory Design Data)

OpenAccess API

StandardWriters

StandardWriters

StandardReadersStandardReaders

...

HPEngine

HPEngineHP

EngineHP

EngineHPEngine

HPEngine

3rd PartyEngine

3rd PartyEngine3rd Party

Engine3rd PartyEngine3rd Party

Engine3rd PartyEngine

OpenAccess Migration at HP - How do we get there?

• Participate in OpenAccess Coalition & Working Groups– Provide feedback to the OAC– Review applicability of OA technology to HP– Influence OA technology

• Evaluate the Reference Implementation– Baseline capacity and performance– Support for current algorithms– Provide feedback to the OAC/Cadence

• Identify a lead tool flow to migrate– Synthesis, Place and Route flow identified– Production flow for a 90-nm design program

...

Historical SP&R Flow - Data File Transfer

DEFVerilog

Meta-data

Floorplan(HP db)

Floorplan

Config

RTL

TimingConstraints

HP CAD Data Model

Clock &TestPrep

Perl DataStructures

PhysicalSynthesis

3rd PartyData Model

Clock & Test

Perl DataStructures

Route

3rd PartyData Model

DEFVerilog

Meta-data

DEFVerilog

Meta-data

DEFVerilog

Meta-data

...

Current SP&R Flow - OpenAccess db Transfer

...

Floorplan

Config

RTL

TimingConstraints

Clock & TestPrep

PhysicalSynthesis

3rd PartyData Model

Clock & Test

OA DataModel

Route

3rd PartyData Model

DEFVerilog

OA Data Model

OA db OA db

FloorplanConstraints

HP SP&R Flow Migration - Initial Results

• Development Status– Implementation has stayed on schedule– Initial resource investment on par with previous flow

upgrade (~9 em)

• Deployment Status:– Phase 1 – Baseline SP&R released – November, 2003

• Primary flow for block build tasks• Design champions can craft their own special

stages• Platform for enhancing design methodology

...

HP SP&R Flow Migration - Continuing Results

• Deployment Status:– Phase 2 – Full SP&R production flow – April, 2003– Methodology enhancements and tuning– Enhanced data management– Interactive flow interface

• Richer query and scripting interface– Extended flow on OA

• Geometric operations for early checking

...

Advantages to using OpenAccess - Positive Experiences

• Openness of OpenAccess– Enables design debug and support for tool flows– OAC Openness to HP feedback!

• OpenAccess Quality has been excellent– Builds cleanly on HP-UX and Linux, PA-RISC and

Itanium

• Documentation and Training materials– Extensive set of reference materials

...

Challenges and Opportunities - OpenAccess Evolution and Issuesand Issues and Issues

• Enrich base utilities available to developers– Verilog Reader/Writer (developed with Cadence)– Hierarchical traversal engines– Higher level access methods

• Potential early instability of new flow:– Mixed environment of OpenAccess and legacy

infrastructure– When do we go to OA v2.2 ?

• EDA business models must evolve– Evaluate impact of “engines” vs. “tools”

• Marketing, sales, support• Distribution, integration, licensing

...

Future SP&R Flow - OpenAccess-based System with Engines

Floorplan

Config

RTL

TimingConstraints

Clock &TestPrep

PhysicalSynthesis

Route

OA db

Efficient Design Iterations

RepeaterInsertion

Clock &Test

ParasiticExtract

FloorplanConstraints

OA Timing ModelOA Data Model

...

Component-based Architecture

with Engines

Route

Fine Grained Components/Engines

Placement GeomOps

...

The Benefits of

Component-based Architecture

OA Region Query

OA Data Model

- a simple example

OpenAccess Migration at HP - Next Steps

• Expand SP&R Flow to meet other needs of HP CAD system– Evaluation of other arenas of the OpenAccess technology

• Parasitic data representation with Geometric associations

• Embedded Module Hierarchy for net-centric analysis– Migration plans for other key flows

• Electrical Rules Checking• Timing analysis

• Conversion/Evolution of applications that are currently based on legacy DB/API– Development of API Emulation layer

• Legacy API overlays on OA API and run-time OA DB– Evolutionary migration/conversion strategy

• Always able to test against existing, production system...

API Emulation Layer Architecture

...

Trantor DBOA DataOA API

OA DB

EmulationOA++

Legacy - -

DRCExtract GeomOps

Layout ServerAuto-Generated Legacy Access Interface

Legacy High Level AccessLS APILegacy+

H

EDA Lab Support for Design Community

...

CAD User

CAD System Builder



Definition


Stability

Is Pretty Darned Important Too

DRCExtract

Leveraged Verification Available Throughout Development Phase

...

GeomOps

Legacy DataLegac

y DB


Legacy High Level AccessLS APILegacy+

Evolution of HP CAD System on OA

...

Trantor DBOA DataOA API

OA DB

DRCExtract

GeomOps


Legacy High Level AccessLS API

Emulation

Legacy+

OA-

Based

Engine

OA-

Based

Engine

OA-

Based

Engine

Summary - HP’s First OpenAccess Deployment

• What we have achieved– More rapid OA adoption via commitment to real flow on real

data– Significantly greater understanding and appreciation of

OpenAccess technology

• Benefits to HP– Enables tighter integration between HP and third-party

solutions– Redirect our internal investment to higher value-add

infrastructure, applications, and methodologies

• Potential benefits to EDA vendors– Reduce investment in proprietary infrastructure– Easier path to demonstrate customer benefit– Lower cost to integrate new and acquired technologies– High potential for visionary suppliers of OA-based components

...

© 2004 Synopsys, Inc. (32)

Interoperability for Whom?

EDP 2004 ConferenceApril, 2004

Noel StraderSynopsys


What Exactly is Interoperability?

Interoperability – not found in typical hard copy or online dictionary

Interoperable – not found

Operable• treatable by surgical operation with a reasonable

degree of safety and chance of success


Interoperability (IEEE & CAD)

IEEE• The ability of two or more systems or elements to

exchange information and to use the information that has been exchanged

Typical Design User• Ability to easily access and efficiently use the tools

required to complete an integrated circuit design


Who Needs Interoperability?

Designers (actual tool users)• 30,000

Flow Developers (CAD)• 3000

Programmers (interoperability)• 300


Three Faces of Interoperability

File read/write• Verilog, VHDL, SDC, LEF, DEF, GDSII• PDEF, SPDF, DSPF, SPEF

Extension language• Tcl, SKILL, Scheme

Compiled language API• C, C++


Who Interoperates With What?

Who uses file read/write?• Everyone• Primary source of original input / final output• Widely used as stop-gap solution• Inevitably used to check data/tool integrity

Who uses extension language?• Almost everyone• Required to successfully drive tools• Widely used for simple to complicated processing

Who uses compiled language?• CAD interoperability programmers


How Does Galaxy Platform Interoperate?

File readers/writers• Verilog, SDC, LEF, DEF, GDSII, etc.- Heavily used today by customers and 3rd parties- All standard readers/writers included with Milkyway

Extension language- Replay, programming, and database access- Uses Tcl for some tools and Scheme for others- At midyear Tcl becomes primary extension language

Compiled language API- Available to customers (1998) and 3rd parties (2002, MAPin)- Used for proprietary or 3rd party tools and data exchange- Success for the largest designs in smallest technologies


Who Needs File Readers/Writers?

All design flows

Original input / final output

Library preparation

IP import (soft and hard)

Tool data exchange (as last resort)


Who Needs Extension Language?

Almost everyone• To control tools• For simple programming tasks• For database access• For command replay

Exceptions• Highly algorithmic operations• Special-purpose data structures


What’s Left for Compiled Language APIs?

Customer proprietary tools

3rd party tool interfaces

Database data exchange

NIH development


Customer Example: LSI

Gate Array Backfill

Standard Cell

Backfill Cell

Backfill Replacement Cell

Legend

• Gate-array backfill: Insertion of backfill cells into unused standard-cell placement spaces

• Performed after placement (and usually before routing.)


Customer Example: NSC

Development of custom router for special nets (power)

Development of NSC-specific spare gate flows, antenna correction, etc.

Used for 3rd party SI-repair flow by feeding repair ECO’s back to Milkyway (Scheme)


3rd Party: Silicon Canvas “Laker”

• Laker Custom Editor Basic Polygon Editing Features

• Object Creation Rectangle, Polygon, Path, Text, Instance

• Object Editing Move, Stretch, Reshape,Split, Merge,…

Point to Point router Hierarchical Net Tracer Undo/Redo DRC Rule Driven On-line DRC

• Reported less than one staff-year to move to Milkyway


3rd Party: Synchronicity’s “DesignSync”


Summary

Today’s design flows require interoperability at three distinct levels: readers/writers, extension language, and compiled language

For vast majority of users/developers, a common extension language, specifically Tcl, provides the most productivity

Compiled language APIs are absolutely required, but possibly for a diminishing set of interface applications

Applications of Applications of Interoperable Databases Interoperable Databases

and Data Models in and Data Models in Production FlowsProduction Flows

at LSI Logic at LSI Logic

Scott A. Peterson

Director RapidChip Methodology

EDP Conference 2004. 48

AgendaAgenda

BackgroundBackground RapidChip™ with the RapidWorx™ design kitRapidChip™ with the RapidWorx™ design kit Bond ApplicationBond Application SummarySummary


BackgroundBackground

LSI Logic maintains several internal databases for design kitsLSI Logic maintains several internal databases for design kits Propriety in nature and specific for feature needsPropriety in nature and specific for feature needs Maintaining propriety databases requires an investment Maintaining propriety databases requires an investment

for development and supportfor development and support LSI Logic uses commercial databasesLSI Logic uses commercial databases

Provide value add applications on commercial offeringsProvide value add applications on commercial offerings No one vendor supplies the necessary features requiredNo one vendor supplies the necessary features required

LSI Logic began investigation of OpenAccess initiative and LSI Logic began investigation of OpenAccess initiative and technology late 2001technology late 2001 Initially ported a GDSII application on OA1.0Initially ported a GDSII application on OA1.0 Determined viability of OpenAccess and proceeded to Determined viability of OpenAccess and proceeded to

develop future RapidWorx™ design kit on OpenAccess develop future RapidWorx™ design kit on OpenAccess for RapidChip™ productfor RapidChip™ product


Utilities Tcl/Tk

GUI Forms

OpenAccess1.0

API3rd PartyDatabase

API

LSI Database

LSI Logic’s API Based Applications

API Layer (DB side)

API Layer (App side)

Initial InvestigationInitial InvestigationInitial InvestigationInitial Investigation


GDSII BenchmarkingGDSII Benchmarking

LSI created a GDSII to OA converterLSI created a GDSII to OA converter Quickest way to populate testcasesQuickest way to populate testcases Centralizes OA database for translatorsCentralizes OA database for translators

– GDSII -> OA, OA -> GDSIIGDSII -> OA, OA -> GDSII

– DEF -> OA, OA -> DEFDEF -> OA, OA -> DEF

– Etc.Etc.

Sample data sets show good resultsSample data sets show good results 3x file size reduction3x file size reduction Program memory usage reasonableProgram memory usage reasonable Program runtimes reasonableProgram runtimes reasonable


GDSII BenchmarkingGDSII Benchmarking

Number of Records

Read Time (ms)

Elapesed time (ms)

GDS Size (KB)

OA Size (KB) Ratio

Design 1 464078 11456 16944 3684 1434 2.6Design 2 5177017 70101 76760 42690 14215 3.0Design 3 5774428 77201 85933 49296 16087 3.1Design 4 6758148 75459 82899 54408 18263 3.0Design 5 7078607 87235 94806 57104 19222 3.0Design 6 7186254 88538 96038 58050 19405 3.0Design 7 8405195 105321 111430 67688 22593 3.0

Run on Pentium III 700MHz processor256MBytes of memoryWin2000 operation system


Utilities Tcl/Tk

GUI Forms

OpenAccess2.0

API

LSI Logic’s API Based Applications

Natively Using OpenAccessNatively Using OpenAccessNatively Using OpenAccessNatively Using OpenAccess


RapidChip™ Product ArchitectureRapidChip™ Product Architecture

RapidChipRapidChipDesign Tools Design Tools

& Methodology& Methodology

LSI LogicLSI LogicRapidReady IPRapidReady IP

Customer Customer Logic/IPLogic/IP



System System Architecture/DesignArchitecture/Design

Rapid ReadyRapid ReadyCoreWare®CoreWare®

RapidChipRapidChipRapidSliceRapidSlice


ProjectProjectInitializationInitialization

DesignDesignCreationCreation

RTLRTLQualificationQualification

PhysicalPhysicalOptimizationOptimization

QualifiedQualifiedHand-offHand-off

RapidWorx™ High Level Design Flow RapidWorx™ High Level Design Flow ViewView

OpenAccessOpenAccessDatabaseDatabase

NetlistNetlist

ConstraintsConstraints

PlacementPlacement

Misc.Misc.

DataDataTranslationTranslation

InstanceInstanceCompletionCompletion

FinalFinalChecksChecks

Tape-OutTape-Out

FabFab

CustomerCustomer LSILSI

Hand-OffHand-Off


RapidChip™ Design StepsRapidChip™ Design Steps

1.1. Project InitializationProject Initialization Slice SelectionSlice Selection Select Soft + Firm IPSelect Soft + Firm IP Instance InitializationInstance Initialization View SliceView Slice

2.2. Design CreationDesign Creation RTL/Constraint/Floorplan CreationRTL/Constraint/Floorplan Creation

– RapidBuilderRapidBuilder Review/Optimization FloorplanReview/Optimization Floorplan

– Unconstrained SynthesisUnconstrained Synthesis– Initialize Floorplan/Personalize SliceInitialize Floorplan/Personalize Slice– Edit FloorplanEdit Floorplan

Prepare for Physical SynthesisPrepare for Physical Synthesis– Write DEFWrite DEF

3.3. RTL QualificationRTL Qualification RapidPRORapidPRO

4.4. Physical OptimizationPhysical Optimization Physical SynthesisPhysical Synthesis

5.5. Qualified Netlist Qualified Netlist HandoffHandoff Import Design for Import Design for

HandoffsHandoffs View DesignView Design RapidCheckRapidCheck

Current OA base toolsFuture OA base tools


Design Cockpit based on Design Cockpit based on OpenAccessOpenAccess


Design Viewer based on Design Viewer based on OpenAccessOpenAccess


DEFInterface

DEFInterface

DEF

File

5:15 min

75k gates + 3 rams

DEFInterface

DEF

File

DEF

File

3:02 min + hand edits

DEFInterface

OpenAccessMilkyway

Post Handoff Data Translation ExamplePost Handoff Data Translation Example

6:06 minvs.

8:17 min

PythonInterface

PythonInterface

MW to OA Python App – 5:50 min

In MemoryInterpretiveTranslators

File BasedCompiled

Translators

OA to MW Python App – 16 sec


RapidSlice “MiniMig”RapidSlice “MiniMig”





RapidSliceRapidSliceMiniMigMiniMig


RapidSlice “MiniMig”RapidSlice “MiniMig”

Slice GatesSlice Gates

1.5M Customer usable gates1.5M Customer usable gates Slice MemoriesSlice Memories

(6) 2K word x 36 bit 2rw(6) 2K word x 36 bit 2rw (8) 1K word x 36 bit 2rw(8) 1K word x 36 bit 2rw (16) 256 word x 36 bit 2rw(16) 256 word x 36 bit 2rw (4) 4K word x 36 bit 1rw(4) 4K word x 36 bit 1rw

Slice Metal Programmable PLL'sSlice Metal Programmable PLL's

(4) 100-500Mhz(4) 100-500Mhz Slice Configurable I/OsSlice Configurable I/Os

390 Customer configurable390 Customer configurable 660 Wirebond package660 Wirebond package


RapidChip™ Customer DesignRapidChip™ Customer Design



LSI LogicLSI LogicRapidReady IPRapidReady IP

Customer Customer Logic/IPLogic/IP

RapidChipRapidChipRapidSliceRapidSlice


RapidChip™ on MiniMigRapidChip™ on MiniMig

Slice GatesSlice Gates

1.5M Customer usable gates1.5M Customer usable gates Slice MemoriesSlice Memories

(6) 2K word x 36 bit 2rw(6) 2K word x 36 bit 2rw (8) 1K word x 36 bit 2rw(8) 1K word x 36 bit 2rw (16) 256 word x 36 bit 2rw(16) 256 word x 36 bit 2rw (4) 4K word x 36 bit 1rw(4) 4K word x 36 bit 1rw

Slice Metal Programmable PLL'sSlice Metal Programmable PLL's

(4) 100-500Mhz(4) 100-500Mhz Slice Configurable I/OsSlice Configurable I/Os

390 Customer configurable390 Customer configurable 660 Wirebond package660 Wirebond package

Customer Design GatesCustomer Design Gates

84K gates84K gates Customer Design MemoriesCustomer Design Memories

(4) 2K word x 36 bit 2rw(4) 2K word x 36 bit 2rw

Customer Design PLL’sCustomer Design PLL’s

(2) 106 Mhz(2) 106 Mhz Customer Design I/OsCustomer Design I/Os

204 2.5v BiDirect204 2.5v BiDirect


RapidChip™ on MiniMigRapidChip™ on MiniMig

Used PLL

Used I/Os

Unused PLL

UsedMemories

UnusedMemories

UsedGates

UnusedGates


RapidChip™ Integrator FamilyRapidChip™ Integrator Family http://lsilogic.com/products/rapidchip_platform_asichttp://lsilogic.com/products/rapidchip_platform_asic

Integrator Family (0.11µm)

RC11Si210 RC11Si211 RC11Si220 RC11Si221 RC11Si230 RC11Si231 RC11Si240

Available Gates (M) 2.4 4.1 3.4 5.4 5 7 6.3

Min-Max Usable Gates (M) 0.8-1.0 1.6-2.4 1.0-2.0 2.1-3.1 1.9-2.9 2.6-4.0 2.4-3.6

RAM: 111 (1rw) 2k x 72 0 0 0 0 0 0 6

RAM: 111 (1rw) 1k x 36 16 16 16 16 16 16 10

RAM: 222 (2rw) 512 x 36 28 28 12 12 16 16 16

RAM: 222 (2rw) 1k x 36 0 0 8 8 12 12 12

RAM: 222 (2rw) 2k x 36 0 0 12 12 16 16 24

Total RAM Bits (M) 1.1 1.1 2 2 2.5 2.5 3.7

100MHz to 500MHz PLLs 4 4 4 4 4 4 4

Packages

252 BGA - 171 Max I/O 171 171 171 0 0 0 0

480 BGA - 355 Max I/O 355 355 355 355 355 0 0

672 BGA - 491 Max I/O 0 491 491 491 491 491 491

896 BGA - 683 Max I/O 0 0 0 683 683 683 683

1152 BGA - 803 Max I/O 0 0 0 0 0 803 803


Silicon Proven Products Delivered RapidlySilicon Proven Products Delivered Rapidly


RapidSlice CreationRapidSlice Creation

Creation of the Creation of the RapidSlice has a RapidSlice has a package bonding steppackage bonding step

LSI Logic created a LSI Logic created a new bonding tool based new bonding tool based on OpenAccesson OpenAccess

““Bond” serves a dual Bond” serves a dual role in the the creation role in the the creation of RapidSlices and of RapidSlices and ASICsASICs





RapidSliceRapidSlice


IO Placement and Routing

Design Errors [ASCII]

LSI

Manufacturing Output

LSI

Non-OpenAccess Packaging ToolNon-OpenAccess Packaging Tool

Create IO Placement and Routing

Check Electrical and Mechanical Rules

Generate Output Files

Previous GenerationPackaging Tool

Netlist

Cell Libraries

LSI

Technology Library

LSI

Package Library

LSI

IO Placement Spec

LSI


Manufacturing Output

LSI

IO Placement and Routing

Design Errors

OA

OpenAccess Based Packaging ToolOpenAccess Based Packaging Tool

Netlist

Cell Libraries

OA

Technology Library

OA

Package Library

LSI

IO Placement Spec

LSI

“Bond”


Tool Modularity with OpenAccessTool Modularity with OpenAccess

RuleChecks

FileInput/Output

PackageAssignment

GUIFuture

Modules

Bond

Infrastructure

Modules interface with Modules interface with each other and the main each other and the main tool via a thin tool via a thin infrastructure. infrastructure.

Module changes have Module changes have little impact on other little impact on other modules.modules.

Different developers Different developers easily work easily work independently.independently.


Why OpenAccess For LSI Logic?Why OpenAccess For LSI Logic?

Source code availabilitySource code availability Debugging requires Debugging requires

understanding the understanding the implementationimplementation

Well defined object data model and Well defined object data model and methodsmethods Enables modular Enables modular

developmentdevelopment Extensive APIExtensive API ExtensionsExtensions

Built-in Support forBuilt-in Support for CallbacksCallbacks UndoUndo Design Error InfrastructureDesign Error Infrastructure

Excellent documentationExcellent documentation Scripting Interface built-inScripting Interface built-in

Open StandardOpen Standard Not constrained by proprietary Not constrained by proprietary

interfaces that are interfaces that are exclusionaryexclusionary

Permit best in class tools to Permit best in class tools to work togetherwork together

Independent ControlIndependent Control Stable environment that won't Stable environment that won't

change if vendors dochange if vendors do– Design migration to different systems is Design migration to different systems is

costlycostly

No internal tool DB to maintainNo internal tool DB to maintain No need to re-invent the wheelNo need to re-invent the wheel Focus on the value-addFocus on the value-add

Ability to make changesAbility to make changes Improves responsiveness to Improves responsiveness to

our customer needsour customer needs


SummarySummary

OpenAccess has been a very positive experience for LSIOpenAccess has been a very positive experience for LSI Its been OpenIts been Open Its been AccessibleIts been Accessible

No internal tool database to maintainNo internal tool database to maintain No need to re-invent the wheelNo need to re-invent the wheel Focus on the value-addFocus on the value-add Lowers costLowers cost

Ability to make changesAbility to make changes Improves responsiveness to our customer needsImproves responsiveness to our customer needs

Scheduled releases and Quality of deliverables have been well Scheduled releases and Quality of deliverables have been well executed in 2003executed in 2003

LSI Logic has been effective in leveraging technologyLSI Logic has been effective in leveraging technology Silicon proven RapidChip™ is powered by OpenAccessSilicon proven RapidChip™ is powered by OpenAccess Expanding usage of OpenAccessExpanding usage of OpenAccess

interoperability panel applications of interoperable databases and datamodel in production flows edp...

Documents

hp design system

centuryic design system

designersupplies tool

cad usercad system buildera

evolution of cad roles

design data

hp backgroundmicroprocessor

information modelcapacity