interfacing of data converters & io devices

Dr.Y.Narasimha Murthy Ph.D [email protected]

Interfacing of Data Converters and I/O Devices

Introduction : In any microprocessor /microcontroller system, peripherals can not be directly connected to the processor with out using cetain logic devices. In bus-oriented systems we need various logic devices like buffers,drivers,encoders ,decoders ,multiplexers and de-multiplexers etc..Especially ,tri-state logic devices are very much required for the proper functioning of multiplexed bus sytems. For example in a microprocessor or microcontroller we find the data and address busses are multiplexed . So , there is a need of these logic devices in every microprocessor based system.

Tri-state Devices : A logic device which has three states, logic 0,logic 1 and and high impedance state is known as a tri-state device. The term tri-state is a trade mark of “National Semiconductors” and is used to represent three logic states. The third state is also called Enable.When this line is activated the tristate device functions same way as ordinary logic device. Similarly when the third line is disabled the logic device goes to the high impedance state-as if it were disconnected from the system.

In microprocessor or microcontroller based systems ,peripherals are connected in parallel between the address bus and data bus. But they can’t load the system because of these tristate devices .The microprocessor communicates with one device at a time by enabling the tri-state line of that interfacing device. Tri-state logic prevents a bus conflict where one device is driving a signal to 1 and another device is driving it to 0 at the same time,which may generate high current through wires.

Buffer : A buffer is a logic circuit that increases or amplifies or boosts the current or power of a logic circuit or device. As it increases the driving capability of a circuit it is also known as a Driver.When the output current of a device is insufficient to drive another device ,a buffer is used to increase the current rating.

Tri-State Buffer : A tri-state buffer has a third line called Enable in addition to In and Out lines

There are two types of buffers (i) Unidirectional Buffer and (ii) Bi-directional Buffer


Unidirectional Buffers: In cases where the receiver current requirements exceed the driver’s capability, we must use buffers/drivers such as the 74LS244 is used for unidirectional address buses. This device transfers the data only in one direction,by increasing the driving capability of the Bus.For Ex: 74LS244 is a unidirectional Octal buffer. The 74LS244has simply 8 tri-state buffers in a single chip. These buffers are divided into two groups. The enabling and disabling of these groups are controlled by 1G and 2G lines, until these lines are enabled ,the output of the drivers remains in the high impedance state. It is also known as line driver or line receiver.

The address bus is unidirectional buffer,74LS244 is used to buffer higher order address bus. It consists of 8-non inverting buffers with try state outputs. Each one can sink 24 mA and source 15 mA of current.

Bi-directional Buffer : This bidirectional buffer is used to increase the driving capability of the data bus. It consists 16 non-inverting buffers, eight for each direction,with tri-state output. The direction of data flow is controlled by the pin DIR. When DIR is high, the data flow from the bus A to the bus B ,when it is low data flows from B to A. The active low enable signal and the DIR signal are ANDed to activate the bus lines. Each buffer in device can sink 24 mA and 15 mA source of current.

The IC 74LS245 is a bidirectional buffer, which is also called Octal bus transreceivers.The direction of the data flow is controlled by the pin DIR .When DIR is high ,the data flows from


Bus A to Bus B and when it is low data flows from B to A.The active low enable signal and the DIR signal are ANDed to activitate the bus lines.Each buffer in this chip can sink a current of 24mA and source a current of 15mA.The logic diagram and the functionl table of LS74245 is shown below.

This bidirectional buffer is widely used with data bus in the microprocessor/ microcontroller based systems.

Decoder : A decoder is mainly used in interfacing I/O peripherals and memory elements to the microprocessor or microcontroller systems.The decoder is used to decode an address bus to identify an output device. Decoders are also built internal to a memory chip to identify individual memory registers.

The decoder is a logic device that identifies each combination of the signals present at its input.If the input to a decoder has two binary lines ,the decoder will have four output lines. Commonly available decoders are 3-to-8 ,4- to- 16 and 4-to-10(to decode BCD input).Also some decoders have active low output lines as well as Enable lines.

74LS138 is a 3 –to-8 decoder and some times it is also called 1-out-of 8 binary decoder or demultiplexer. The 74LS138 decodes one-of-eight lines, based upon the conditions at the three binary select inputs and the three enable inputs. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding.


To enable the device to function as decoder all the three enable lines should be activated.

Encoder : The encoder is a logic circuit that provides a code (Binary or BCD) at the output for

every input signal applied to it. This is the reverse process of the Decoding.Normally digital

encoders produce outputs of 2-bit, 3-bit or 4-bit codes depending upon the number of data input

lines. An "n-bit" binary encoder has 2n input lines and n-bit output lines with common types that

include 4-to-2, 8-to-3 and 16-to-4 line configurations. The output lines of a digital encoder

generate the binary equivalent of the input line whose value is equal to "1" and are available to

encode either a decimal or hexadecimal input pattern to typically a binary or B.C.D. output code.


One of the disadvantages of the encoders is that they can generate the wrong output code when

there is more than one input present at logic level "1". For example, if we make inputs D1 and

D2 HIGH at logic "1" both at the same time, the resulting output is neither at "01" or at "10" but

will be at "11" which is an output binary number that is different to the actual input present.

Also, an output code of all logic "0"s can be generated when all of its inputs are at "0" OR when

input D0 is equal to one.

A simple method to overcome this problem is to "Prioritize" the level of each input pin and if

there was more than one input at logic level "1" the actual output code would only correspond to

the input with the highest designated priority. Then this type of digital encoder is known

commonly as a Priority Encoder or P-encoder .

The TTL 74LS148 is an 8-to-3 bit priority encoder

which has eight active LOW (logic "0") inputs and

provides a 3-bit code of the highest ranked input at

its output. Priority encoders output the highest order

input first for example, if input lines "D2", "D3"

and "D5" are applied simultaneously the output

code would be for input "D5" ("101") as this has the

highest order out of the 3 inputs. Once input "D5"

had been removed the next highest output code

would be for input "D3" ("011"), and so on.

The Encoder chip has five output lines.Three are

encoding lines and two are output enable indicators.

The output lines GS and EO can be used to encode more than eight inputs by cascading these

devices.When the encoder is enabled and two or more input signals are activated simultaneously

,it ignores the low priority inputs and encodes the highest priority inputs.

Encoders are commonly used with keyboards .For each key pressed the corresponding binary

code is Placed on the data bus.

Latches-DFlip-Flops : The simplest form of a Latch is a D-flip-flop.It is also called a

transparent latch. The 74LS75 is an example for D flip-flop.The output changes according to


input ,only when the Enable pin is High. The 7475 is a positive edge triggered flip-flopwhich is

shown below..

A typical example for transparent Latch is 74LS373 chip. When the microprocessor sends the

output data , the data is available on the data bus only for few micro seconds, there after a Latch

is used to hold the data for display.The logic diagram of the IC 74LS373 is shown below.

The IC 74LS 373 is an octal buffer latch which consists of eight D latches with tri-state buffers

and require two input signals. Enable (G) and output control(OC) The enable is an active high

signal connected to the clock input of the flip-flop. When this signal goes low,data is latched

from the data bus.the output control signal is active low and it enables the tri-state buffer to

output data to the display device.


Multiplexer (Data Selector)

A multiplexer selects one out of N inputs and makes it available at the output terminal.So, a

Multiplexer has N-inputs and one output only.This is also known as Data selector or simply

MUX.For Ex: 74LS151 is a digital multiplexer with 8-input lines, three select lines and one

strobe line and one output. The logical diagram is shown below.

In the diagram A,B and C are the select lines.Based on the value on select lines the

corresponding input is selected.For 000 input D0 is selected. Similarly for 111 input D7 is

selected..The strobe line enables the output.When it is High ,the output is enabled.Multiplexer

are used to give multiple inputs to a processor or Microcontroller.

De Multiplexer : A De-Multiplexer accepts a single input and sends it to 1 out of N output

lines.,which is selected by the select lines.It performs the reverse operation of a Mux.In a

demux ,the input data can be made available at any one of the output lines. This de mux is also

known as Decoder.Ex: The chip 74LS 154 is a 1 to 16 lines de-multiplexer and 4 to 16 line

decoder. The basic


difference between the two is that the de-Mux has Data input where as the decoder has no Data

input.

Interfacing a Octal Driver and a D-Latch to The Microprocessor :

Generally the system Bus of the Microprocessors can source only 400 microamperes and sink

about 2 mA of current.So, the bus can drive only one TTL load.Hence it is always necessary to

increase the driving capability of the busses by using the Drivers or Buffers.For this reason in

any microprocessor or microcontroller based systems the IC 74LS244 is interfaced with the


higher order address bus to improve its driving capacity as shown in the diagram.

Similarly ,in microprocessor /microcontrollers the address/data bus lines are multiplexed.The

latching of lower order address bus is done by using the ALE signal from the microprocessor.For

demultiplexing the bus , the IC 74LS373 which is transparent 8-bit Latch is used. This IC

consists of 8 D flip-flops.The ALE signal is connected to clock through the Enable pin .

So,when this ALE is high,the clock will allow any data at its input to the output.[This is the

reason for calling it as transparent Latch]. So , 74LS373 8-bit (octal) D latch latches the address

bits A0-A7 when ALE is HIGH, and keeps them available when ALE is LOW.

Interfacing a bi-directional bus Driver and a Decoder to the Microprocessor :

To work effectively with data bus and control bus of the microprocessor .a bi-directional bus

driver and one 3-to-8 decoder are required.


Bi-directional bus transceivers are required on the data bus, since data can travel not only from

the CPU to the peripheral device, but also in the opposite direction. Transceivers are required at

both the CPU and peripheral device ends.So, to increase the driving capacity of the Data bus ,the

IC 74LS245 octal bidirectional bus driver is interfaced to the microprocessor as shown above.

The IC 74LS245 is a bidirectional buffer, which is also called Octal bus transreceivers.The

direction of the data flow is controlled by the pin DIR .When DIR is high ,the data flows from

Bus A to Bus B and when it is low data flows from B to A.The active low enable signal and the

DIR signal are ANDed to activitate the bus lines.Each buffer in this chip can sink a current of

24mA and source a current of 15Ma.

Also to generate the control signals like I/O read , I/O write ,Memory Read and Memory write

the chip 74LS138 a 3- to -8 decoder is also interfaced to the microprocessor. This decoder chip

will provide the control signals as shown in the diagram.For example, the RD signal has to

generate two different read signals,one for memory and the other for input.Similarly two separate


write signals must be generated.These four signals are generated by the Decoder by combining

the RD,WR and IO/M signals .When the signal IO/M goes low ,the control signals for memory

operations are generated. Similarly when IO/M goes High , the signals corresponding to I/O are

generated.

Interfacing data convertors (DAC and ADC) :

Introduction : Data converter is a device which converts one form of data into its another

equivalent form .There are two types of data converters .They are

i. Analog to Digital Converter-(ADC)

ii. Digital to Analog converter-(DAC)

These converters are very important elements in every data acquisition system .Because the

naturally available data is always analog and all the processing devices like Microprocessors or

Microcontrollers or Digital signal processors etc.. are digital devices. So,this analog data must be

first converted into equivalent digital data before it is applied to the Microprocessor or

Microcontroller. Similarly the output of the processors is always in digital form and it will not

be convenient for common man. So,again this digital data must be converted into equivalent

analog data using a DAC. Hence without the use of data converters it is not possible to design

any Data acquisition system.

INTERFACING DAC - 8051 MICROCONTROLLER

The DAC 0800 is a simple monolithic 8-bit Digital to Analog converter. It has fast settling time of 100ns.

It can be directly interfaced to TTL, CMOS, PMOS and othersdevices. It operates at 4.5V to +18V supply.

The number of data bit inputs decides the resolution of the DAC since the number of analog output

levels is equal to 2″, where n is the number of data bit inputs. Therefore, an 8-input DAC such as the

DAC0808 provides 256 discrete voltage (or current) levels of output.

The interfacing circuit is shown below. The port 1(8 bits of the microcontroller) is connected to

the input data lines of DAC-0800 and the input is applied through this port1.The reference

current is determined by the resistor R1 and the reference voltage Vref. The resistor R2 is

generally equal to R1 to match the input impedance of reference source. The output is normally

in current form. So, to convert this current into equivalent voltage ,an op-amp circuit is used at


the output. This is a voltage to current converter and the output of the op-amp can be measured

either with a multimeter or using a cathode ray oscilloscope.

The output current Io is calculated as follows:

Io = Vref / R1[Ao/2 + A1/4 + A2/8 + … +A7/256]

A simple assembly language Program is given below.

MOV A, #DATA* ; (A) = #Data

START : MOV 90H, A ; (port -1) = (A)

INC A

LJMP START ; Repeat

Interfacing of ADC 0804 to 8051 Microcontroller :

ADC 0804 is a single channel analog to digital converter It is a single channel ADC. i.e. it can

take only one analog signal and convert it into equivalent digital value. ADC 0804 has 8 bit

resolution. The higher resolution ADC gives smaller step size. Step size is smallest change that


can be measured by an ADC. For an ADC with resolution of 8 bits, the step size is 19.53mV

(5V/255). The time taken by the ADC to convert analog data into digital form depends on the

frequency of clock source. The conversion time of ADC 0804 is around 110us. To use the

internal clock a capacitor and resistor are used as shown in the circuit. The input to the ADC is

given from a regulated power supply and a 10K potentiometer.

The 8051 Microcontroller is used to provide the control signals to the ADC. The pins P1.1, P1.0

and P1.2 are connected to the pin WR, RD and INTR of the ADC respectively. CS(chip select)

pin of ADC is directly connected to ground. When the input voltage from the preset is varied the

output of ADC also varies.

From the circuit it is clear that the ADC interfaced directly to the microcontroller. The Port1 is

used as an input port which receives the digital data from the ADC. Port pins P2.5 and P2.6 are

used for SOC and ALE operation (RD and WR).When the conversion is over the ADC will send

an interrupt signal to the microcontroller through the pin P2.7 .Now the Microcontroller receives

digital data through the Port1.This data after conversion to decimal data is displayed on the LCD

module

.


The assembly language program for ADC is given below .

MOV P1 , 0FF H ; Make the port1 high and configure port1 as Input port

BACK: CLR P2.6 ; Generation of SOC pulse

SETB P2.5 ;

LOOP JB P2.7 , LOOP ; Wait for conversion, Is conversion over?

CLR P2.5 ; Enable Read the digital data

MOV A ,P1 ; Read digital data through Port1

SETB P2.5 ; Disable read after read operation

CALL DISPLAY ; Display the data on LCD module

SJMP BACK ; Continue the conversion process

Direct Memory Access (DMA) Data Transfer :

When large amount of data is to be transferred between microprocessor and I/O device it is a

very time consuming operation and the precious time of CPU is wasted. If the I/O port can

directly access memory for data transfer, without CPU intervention, that will be more efficient.

So, in any microprocessor system, if the data transfer takes place without the intervention of the

CPU, that method is known as Direct Memory Access data transfer technique (DMA).

The data transfer between a floppy disk or CD ROM and a R/W memory in a system is

an example for DMA data transfer. To perform this DMA transfer in microprocessor based

systems two signals HOLD and HLDA (Hold Acknowledge) are used. An I/O device which

wish to transfer data using DMA scheme, sends the HOLD signal to the CPU. On receiving the

HOLD signal from an I/O device, the CPU sends a hold acknowledge signal (HLDA) to the I/O

device to indicate that it has received the HOLD request and it will giveup the buses in the next

machine cycle. The I/O device takes over the control of buses and directly transfer data to the

memory or reads data from the memory.

There are two types of DMA schemes. They are


a) Burst mode DMA

b) Cycle stealing DMA

Burst Mode DMA

This method is used when a large data block is to be transferred between a I/O device and

main memory. In each DMA cycle one byte will be transferred and the DMA controller gives up

control of system buses only after all the data has been transferred. The DMA controller

interrupts the microprocessor and HOLD request is withdrawn.

This technique was widely used by magnetic disk drives. In case of magnetic disks data

transfer can not be stopped or slowed down without loss of data. Hence burst mode data

transfer scheme is useful.

Cycle Stealing DMA

This method is used when the I/O device is relatively slow. After a DMA cycle which

results in a byte of data transfer, the I/O device withdraws the DMA request. So, the DMA

controller withdraws the Hold request by making it low. So, the CPU comes out of HOLD mode

and continues to execute the main program. After some time when the I/O device is again ready,

it once again activates the data request I/P of DMA controller. So, DMA again activates the

HOLD pin and waits for HLDA. Now the data transfer is performed again. In this way the

complete data is transferred. As the data transfer occurs during certain cycles of CPU, it is called

cycle stealing DMA.

DMA Controller - Intel 8257 : Intel 8257 is a programmable, 4-channel direct memory

access controller i.e., four peripheral devices can request data transfer at any instant. The request

priorities are decided internally. Each channel has two signals, DRQ (DMA Request) and (DMA

acknowledge). Each channel has two 16 bit registers. One for the memory address where the

data transfer should being and the second for a 14-bit count. There are also two 8-bit registers

one is the mode set register and the other is status register. It can operate both in slave and

master mode. It is a totally TTL compatible chip.

Interfacing of 8257 to Microprocessor- 8086 : Interfacing of DMA controller to the

microprocessor is shown below.


To interface the DMA controller chip to any microprocessor or microcontroller, first the address

data bus must be demultiplexed and the control lines must be generated and the driving

capability of the data bus and the address busses must be increased using suitable logic ICs. The

IC 74LS244 octal buffer is used to increase the driving capability of the address lines A 16-A19 and

the IC 74LS373 is a latch which demultiplexes the AD7-AD0 bus in to lower order address bus

and data bus. When the ALE pin is high it generates the address lines and when ALE is low it

generates the data bus .The address bus can source only about 400 uA of current only.So,to

increase the driving capability of the address lines A8-A15 the chip 74LS373 buffer is used. The

Decoder 74LS138 which is a 3 to 8 decoder will generate the control signals to read or write

the I/O or memory devices .To increase the driving capability of the data bus a bidirectional octal

bus trans-receiver 74LS245 can also be used in the circuit .


SERIAL DATA TRANSFER: Data transfer between two electronic devices (Ex Between a

microprocessor and computer or a microcontroller or a peripheral device) is generally occurs

in two ways

(i).Serial data Transfer and

(ii).Parallel data Transfer

Serial data transfer uses only one or two data lines to transfer data and is generally used for long

distance communication. In serial communication the data is sent as one bit at a time in a timed

sequence on a single wire. Serial transfer takes place in two methods, Asynchronous data

Transfer and Synchronous data Transfer.

Asynchronous data transfer allows data to be transmitted without the sender having to send a

clock signal to the receiver. Instead, special bits will be added to each word in order to

synchronize the sending and receiving of the data. When a word is given to the UART for

Asynchronous transmissions, a bit called the "Start Bit" is added to the beginning of each word

that is to be transmitted. The Start Bit is used to alert the receiver that a word of data is about to

be sent, and to force the clock in the receiver into synchronization with the clock in the

transmitter.


Serial Data transfer

After the Start Bit, the individual bits of the word of data are sent .Here each bit in the word is

transmitted for exactly the same amount of time as all of the other bits. When the entire data

word has been sent, the transmitter may add a Parity Bit that the transmitter generates. The Parity

bit may be used by the receiver to perform simple error checking. Then at least one Stop Bit is

sent by the transmitter. If the Stop Bit does not appear when it is supposed to, the UART

considers the entire word to be corrupted and will report a Framing Error.

Baud rate is a measurement of transmission speed in asynchronous communication, it represents

the number of bits/sec that are actually being sent over the serial link. The Baud count includes

the overhead bits Start, Stop and Parity that are generated by the sending UART and removed by

the receiving UART.

In the Synchronous data transfer method the receiver knows when to “read” the next bit

coming from the sender. This is achieved by sharing a clock between sender and receiver. In

most forms of serial Synchronous communication, if there is no data available at a given time to

transmit, a fill character will be sent instead so that data is always being transmitted.

Synchronous communication is usually more efficient because only data bits are transmitted

between sender and receiver , however it will be more costly because extra wiring and control

circuits are required to share a clock signal between the sender and receiver.

Devices that use serial cables for their communication are divided into two categories.

1. DTE (Data Terminal Equipment). Examples of DTE are computers, printers & terminals.

2. DCE (Data Communication Equipment). Example of DCE is modems.

Parallel Data Transfer :

Parallel communication uses multiple wires (bus) running parallel to each other, and can

transmit data on all the wires simultaneously. i.e all the bits of the byte are transmitted at a time.

So, speed of the parallel data transfer is extremely high compared to serial data transfer. An 8-bit

parallel data transfer is 8-times faster than serial data transfer. Hence with in the computer all

data transfer is mainly based on Parallel data transfer. But only limitation is due to the high

cost ,this method is limited to only short distance communications.


S.No Serial Communication Parallel Communication

1 Data is transmitted bit after the bit in a single line

Data is transmitted simultaneously through group of lines(Bus)

2 Data congestion takes place No, Data congestion

3 Low speed transmission High speed transmission

4 Implementation of serial links is not an easy task.

Parallel data links are easily implemented in hardware

5. In terms of transmission channel costs such as data bus cable length, data bus buffers, interface connectors, it is less expensive.

It is more expensive

6 No , crosstalk problem Crosstalk creates interference between the parallel lines.

7 No effect of inter symbol interference and noise

Parallel ports suffer extremely from inter-symbol interference (ISI) and noise, and therefore the data can be corrupted over long distances.

8 The bandwidth of serial wires is much higher.

The bandwidth of parallel wires is much lower.

9 Serial interface is more flexible to upgrade , without changing the hardware

Parallel data transfer mechanism rely on hardware resources and hence not flexible to upgrade.

10 Serial communication work effectively even at high frequencies.

Parallel buses are hard to run at high frequencies.

Memory and I/O Interfacing :

(i) Memory interfacing : Memory is an important and inseparable part of any microprocessor

system. During the execution of a program, the microprocessor will be frequently accerssing this

memory either for instruction codes (ROM) or data (RAM). In order to communicate with

memory, an interface is necessary between RAM and ROM memories, the address bus, the data

bus and the control bus from the microprocessor.


The address bus interface is necessary in order to send the address of the memory

location that is to be read or written to the memory.

The data bus interface is required in order to send the data from memory to the

microprocessor.

The control bus interface is necessary to enable the memory chips, so that the memory

chips knows whether the address on the address bus is a memory read or memory write

operation. So, the basic functions of memory interfacing are:

a) To identify the memory register using required number of address lines.

b) To decode the remaining address lines of the address bus to generate chip select signal and

c) Generate control signals and by combining RD and WR signals with

IO /M and use them to enable appropriate buffers.

The general interfacing circuit of microprocessor with RAM and ROM is shown in Fig below.

Both RAM and ROM have an interface with the address bus, the data bus and control bus.

The address decoder determines which memory chip is to be enabled, based upon the memory

address that comes over the address bus. In most microprocessor systems, the ROM address

are the lower bits in the address map and the RAM addresses are the higher ones.


Interfacing of RAM and EPROM to 8086 Microprocessor :

Let us assume that we have to interface a RAM and one EPROM (2764) to the 8086

microprocessor .The important ICs required are one Decoder which decodes the addresses and

one latch/ buffer as shown in the diagram. A Latch 74LS373 is used to demultiplex the address

and data lines.The Decoder will generate the necessary control signals for Memory read and

memory write operation. The memory capacity decides the number of address and data

lines.The necessary decoder circuit is used to decode the address lines and to generate chip select

and output enable signals as shown in the diagram. Both the EPROM and RAM requires 8-data

lines and 13 address lines. The remaining address lines are used in association with decoder to

generate CS signal.


Interfacing of RAM and EPROM to 8051 Microcontroller : The interfacing of

EPROM 2764 to 8051 Microcontroller is shown below.This memory element stores the program

code.To access this external memory ,the PSEN pin (program Store enable )is a very important

pin.This pin is connected to the output enable pin of the EPROM. Similarly the External

Access(EA) pin should always connected to ground to access the external memory. A 74LS373

LATCH chip is used to demultiplex the address and data lines of the microcontroller.The address

latch enable pin is connected to the Clk ,to enable the Latch. When ALE is high means,the Port0

has the address on its lines otherwise the port0 has Dta on its lines. We can also use one bi-

directional transreceiver chip for the data bus .This will increase the driving capabilities of the

data bus.

In 8051 microcontroller ,the Port 0 has the dual application of AD bus as well as I/O port. Hence

the port pins are connected to the Latch. Similarly the Port 2 has the dual application of higher

order address bus and also I/O port. These address lines can be given to any bus driver or buffer

IC to increase its driving capability. Since the EPROM is only of 8K X 8 chip, it requires only 13

address lines to decode the address of the memory chip.


I/O Interfacing : Now a days microprocessor and microcontroller based systems are very

widely used in instrumentation or automatic control applications. In such cases it is necessary

that the microprocessor reads the input devices (switches, sensors) and activate some output

devices (motors, heaters, lights). So, the I/O interface is required to enable the interface between

the microprocessor and the peripheral devices. These peripheral devices are connected on a

microprocessor system through the Input/Output ports.

The I/O interface provides the following :

(a) Isolation between the buses and the peripheral devices.

(b) Address decoding. and (c) Synchronization/Latching.

The I/O interfacing is normally done in two ways. Either by Isolated I/O scheme or Memory

mapped I/O scheme. In isolated I/O scheme the I/O locations are separate from memory

locations and special I/O instructions (Like IN and OUT ..) are used but the disadvantage is

additional control signals like (IO/M) and the complexity in instructions increases.

Ex : IN AL , 30H ; OUT 30H,AL

But in Memory mapped I/O scheme the same address is used for both I/O devices and memory

locations in the memory map. Simple instructions like MOV , LDR ,STR are used. The

advantage is simpler decoding circuitry and no special instructions are required.

Examples for I/O interfacing are , LED interfacing ,Stepper motor Interfacing ,LCD interfacing .

To implement the Input ports a simple octal bus driver/buffer like 74LS244 or 74LS245 are used.

Interfacing of I/O devices to 8086 Microprocessor : The interface diagram is shown below.

The 8288 bus controller produces the control signals for the I/O subsystem.The 8288 generates

the I/O read command output (IOR) and for I/O read cycle it generates I/O command outputs

IOW and AIOW . The 8288 also produces the control signals ALE, DT/R & and DEN .As

shown in the diagram the MN/MX is grounded which indicates that the processor is in maximum

mode. The complete AD—AD15 bus is used for input and output data transfers and M/IO’ signal

is made high to indicate that the device is an IO device. The various IO devices connected to the


interface circuit may be seven segment display or Stepper motor or any keyboard or display

device.The IO devices amy be connected in minimum mode also.In such case the MN/MX pin

must be made High (Vcc).In such a case status signal SSO pin is used instead of BHE signal.

---------------xxx------------------

interfacing of data converters & io devices

Documents

bus lines

output device

unidirectional buffer

tristate logic devices

bidirectional buffer

bidirectional buffer

interfacing device

tristate output