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Designing Chip-Level Nanophotonic Interconnection Networks Christopher Batten Computer Systems Laboratory Cornell University ASPLOS PC Meeting Mini-Symposium October 21, 2011

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Page 1: Interconnection Networks Designing Chip-Level NanophotonicOff-chip photonic link (50µm coupler pitch) 0.25 13-26 Off-chip electrical SERDES (50µm pitch) 5 0.2 On-chip/off-chip seamless

Designing Chip-Level NanophotonicInterconnection Networks

Christopher BattenComputer Systems Laboratory

Cornell University

ASPLOS PC Meeting Mini-SymposiumOctober 21, 2011

Page 2: Interconnection Networks Designing Chip-Level NanophotonicOff-chip photonic link (50µm coupler pitch) 0.25 13-26 Off-chip electrical SERDES (50µm pitch) 5 0.2 On-chip/off-chip seamless

Motivation Nanophotonic Devices Nanophotonic Networks

CMP Memory Bandwidth Challenge

Cornell CSL Christopher Batten 2 / 14

Page 3: Interconnection Networks Designing Chip-Level NanophotonicOff-chip photonic link (50µm coupler pitch) 0.25 13-26 Off-chip electrical SERDES (50µm pitch) 5 0.2 On-chip/off-chip seamless

Motivation Nanophotonic Devices Nanophotonic Networks

Goal for Talk

Illustrate the nanophotonic interconnectionnetwork design process and explain what research

in this area is trying to achieve

Cornell CSL Christopher Batten 3 / 14

Page 4: Interconnection Networks Designing Chip-Level NanophotonicOff-chip photonic link (50µm coupler pitch) 0.25 13-26 Off-chip electrical SERDES (50µm pitch) 5 0.2 On-chip/off-chip seamless

Motivation Nanophotonic Devices Nanophotonic Networks

Implementing a Nanophotonic Channel

• Light coupled into waveguide on chip A

• Transmitter off : Light extracted by ring modulator

• Transmitter on : Light passes by ring modulator

• Light continues to receiver on chip B

• Light extracted by receiver’s ring filterand guided to photodetector

Cornell CSL Christopher Batten 4 / 14

Page 5: Interconnection Networks Designing Chip-Level NanophotonicOff-chip photonic link (50µm coupler pitch) 0.25 13-26 Off-chip electrical SERDES (50µm pitch) 5 0.2 On-chip/off-chip seamless

Motivation Nanophotonic Devices Nanophotonic Networks

Implementing a Nanophotonic Channel

• Light coupled into waveguide on chip A

• Transmitter off : Light extracted by ring modulator

• Transmitter on : Light passes by ring modulator

• Light continues to receiver on chip B

• Light extracted by receiver’s ring filterand guided to photodetector

Cornell CSL Christopher Batten 4 / 14

Page 6: Interconnection Networks Designing Chip-Level NanophotonicOff-chip photonic link (50µm coupler pitch) 0.25 13-26 Off-chip electrical SERDES (50µm pitch) 5 0.2 On-chip/off-chip seamless

Motivation Nanophotonic Devices Nanophotonic Networks

Energy Efficiency and Bandwidth Density

BandwidthEnergy Density(pJ/b) (Gb/s/µm)

Global on-chip photonic link 0.25 160-320Global on-chip optimally repeated M9 wire in 32 nm 1 5

Off-chip photonic link (50 µm coupler pitch) 0.25 13-26Off-chip electrical SERDES (50 µm pitch) 5 0.2

On-chip/off-chip seamless photonic link 0.25

Cornell CSL Christopher Batten 5 / 14

Page 7: Interconnection Networks Designing Chip-Level NanophotonicOff-chip photonic link (50µm coupler pitch) 0.25 13-26 Off-chip electrical SERDES (50µm pitch) 5 0.2 On-chip/off-chip seamless

Motivation Nanophotonic Devices Nanophotonic Networks

Nanophotonic Device Integration Strategy

Cornell CSL Christopher Batten 6 / 14

Page 8: Interconnection Networks Designing Chip-Level NanophotonicOff-chip photonic link (50µm coupler pitch) 0.25 13-26 Off-chip electrical SERDES (50µm pitch) 5 0.2 On-chip/off-chip seamless

Motivation Nanophotonic Devices Nanophotonic Networks

Cornell CSL Christopher Batten 7 / 14

Page 9: Interconnection Networks Designing Chip-Level NanophotonicOff-chip photonic link (50µm coupler pitch) 0.25 13-26 Off-chip electrical SERDES (50µm pitch) 5 0.2 On-chip/off-chip seamless

Motivation Nanophotonic Devices Nanophotonic Networks

Designing Nanophotonic Interconnection Networks

I Architectural-Level Design. Network topology, routing algorithm. Analytical bounds on performance. Electrical baseline network

I Microarchitectural-Level Design. Choose electrical vs. nanophotonic

components. Flow control and arbitration

I Physical-Level Design. Map µarch design to physical substrate. Assign wavelengths to waveguides/fibers. Decide how to layout waveguides and

organize fibers

Cornell CSL Christopher Batten 8 / 14

Page 10: Interconnection Networks Designing Chip-Level NanophotonicOff-chip photonic link (50µm coupler pitch) 0.25 13-26 Off-chip electrical SERDES (50µm pitch) 5 0.2 On-chip/off-chip seamless

Motivation Nanophotonic Devices Nanophotonic Networks

Architectural-Level Design

Cornell CSL Christopher Batten 9 / 14

Page 11: Interconnection Networks Designing Chip-Level NanophotonicOff-chip photonic link (50µm coupler pitch) 0.25 13-26 Off-chip electrical SERDES (50µm pitch) 5 0.2 On-chip/off-chip seamless

Motivation Nanophotonic Devices Nanophotonic Networks

Microarchitectural-Level Design for Crossbar

Cornell CSL Christopher Batten 10 / 14

Page 12: Interconnection Networks Designing Chip-Level NanophotonicOff-chip photonic link (50µm coupler pitch) 0.25 13-26 Off-chip electrical SERDES (50µm pitch) 5 0.2 On-chip/off-chip seamless

Motivation Nanophotonic Devices Nanophotonic Networks

Microarchitectural-Level Design for Butterfly

Cornell CSL Christopher Batten 11 / 14

Page 13: Interconnection Networks Designing Chip-Level NanophotonicOff-chip photonic link (50µm coupler pitch) 0.25 13-26 Off-chip electrical SERDES (50µm pitch) 5 0.2 On-chip/off-chip seamless

Motivation Nanophotonic Devices Nanophotonic Networks

Physical Design for Butterfly

Cornell CSL Christopher Batten 12 / 14

Page 14: Interconnection Networks Designing Chip-Level NanophotonicOff-chip photonic link (50µm coupler pitch) 0.25 13-26 Off-chip electrical SERDES (50µm pitch) 5 0.2 On-chip/off-chip seamless

Motivation Nanophotonic Devices Nanophotonic Networks

Goals for Nanophotonic Network Research

Non-GoalPhotonic network A is 50% “better” than electrical network B

Goal #1Develop design patterns and design guidelines

that capture high-level design trade-offs andprovide context for device-level researchers

Goal #2Explore how this emerging and potentially disruptive technology

can radically change high-performance system design

Cornell CSL Christopher Batten 13 / 14

Page 15: Interconnection Networks Designing Chip-Level NanophotonicOff-chip photonic link (50µm coupler pitch) 0.25 13-26 Off-chip electrical SERDES (50µm pitch) 5 0.2 On-chip/off-chip seamless

Motivation Nanophotonic Devices Nanophotonic Networks

Past and Current Research

I Past Work. Nanophotonic Processor-to-DRAM Networks [HOTI’08,IEEE Micro’09]. Nanophotonic On-Chip Clos Network [NOCS’09]. Nanophotonic DRAM Memory Channels [ISCA’10]. Nanophotonic System-in-Package [WINDS’10]

I Current Work. Design patterns/guidelines for nanophotonic interconnection networks. More sophisticated models to bridge device-level to system-level gap. Leveraging new nanophotonic devices. Mitigating thermal sensitivity of silicon photonic devices. Simple prototype nanophotonic networks

Cornell CSL Christopher Batten 14 / 14

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