interconnect vr

7/30/2019 Interconnect VR

1/8

Interconnect-Centric SoC Design for Network-on-Chip

Personal

Project Manager: Ph.D. Li-Rong Zheng, KTH, Electrum 229, KistaProject Supervisor: Prof. Hannu Tenhunen, KTH, Electrum 229, KistaPh.D. Students: Dinesh Pamunuwa, Jian Liu, Meigen Shen, WimMichielsen

1: Introduction The system-on-chip (SoC) design paradigm and deep submicron

(DSM) technology bring two main challenges to the ASIC designcommunity. The first one is productivity to use millions of gates withinever shorter time-to-market, which is currently tackled with the designmethodology based on Intellectual Property Right (IPR) blocks. Thesecond challenge is coping with rapidly changed technologyparameters, where interconnect invites many signal and powerintegrity related problems. It is now clear that in ultra-deep submicronSoC design, interconnect will be a main design constraint anddominating effects in terms of system architecture, performance,robustness, power consumption, and cost. As an example, our studyrevealed that in a 0.07 m CMOS chip, unless the system cock rate isgreatly reduced otherwise, the maximum region that can besynchronized is about 6mm due to excessive interconnect delay andcrosstalk [1]. Thus, new models and templates for design architecturesare needed. One of such strongly emerging approaches is network-on-chip (NoC) based architectures and platforms. In a multiple-processorSoC or network-on-chip, global interconnects are reserved for globalcommunications. Consequently, the maximum synchronous regionwould be just 3 mm due to the interconnect limitation. Therefore, infuture SoC design, issues of interconnect constraints must beaccurately addressed in early system decisions and performanceanalysis in all abstraction levels and in different phases of the designrefinement process. Interconnects are no longer separate post-layoutand back-annotated issues, but are up-front system and architecturedesign issues. We need to describe the necessary physical propertiesand constraints in as attributes to interconnect library or interconnectIPRs. Only when these virtual wires are integrated in analyses,decisions made at high levels will be accurate; rework and iterationsbetween system design and physical design will be reduced.

In this project, we take interconnect as the main design object. Wetry to demonstrate the basic methods and techniques of how a system

1


2/8

architecture can be optimally defined by early addressing theinterconnect constraints. The problems we will study include:1. Issues of interconnect constraints and how they constrain the

system architectures and global communications (For example, themaximum synchronous region, maximum bandwidth of memory andglobal communications);

2. How to incorporate the effects of lower level decisions in higher-level system architecture decisions? (For example, the new designflow and method)

3. How to evaluate and select the best global communicationarchitecture under interconnect performance and wireabilityconstraints?

4. How to estimate the performance of the select system architectureparticularly the NoC? (For example, interconnect library andperformance estimator)

5. What are the appropriate communication structures at circuit andlogical level for NoC. In best cases these communication links canbe encapsulated as IPR-blocks (includes then both the dynamicinterconnect library concepts for wires, driver receiver circuitry, andbasic link protocol and media access control) in similar manner asprocessors or memories.

6. In addition, we will develop innovative techniques for mixed-signalisolations, signal and power distributions; integrate thesetechniques in our interconnect-centric design method andimplement them in innovative mixed-signal SoC architectures. The above listed problems are general to all DSM SoCs. With a

particular focus, we will study these issues on NoCs (Network-basedSoCs), with a close cooperation with another research group leaded byProf. A. Jantsch in applicants laboratory on project DesignMethodology of NoC. That project (we refer to as NoC projecthereafter) focuses on high level communication architecture andsynthesis issues, and this work focuses on physical level issues and is acomplementary one in the frame of NoC research at KTH. The methodsand techniques developed from this work will be directly used anddemonstrated in the NoC project, providing good opportunity tointerdisciplinary co-operation and enhancing mutually the quality andinternational recognition of the work performed.

2: Problem solutions and limitationsOur solution to the problems consists of three aspects: explore the

main constraints , perform a priori interconnect estimation , anddefine the design method and supporting tools and design flowconcepts .

2


3/8

For many years, we have studied the electrical properties of DSMinterconnects and developed some necessary models or algorithms forsignal integrity and power distribution design. In addition to adoptingmany existing models in open literatures, our study on interconnect-constraints on system architectures will be much based on our own

developed models and methods, giving us a unique competitiveadvantage. We focus particularly the global interconnects since globalwires are most critical to chip performance in DSM circuits.

In order to perform a priori interconnect estimation, our basicassumption is that in the future SoC design, reuse of IPRs will be verycommon. In a chip with billions of transistors, only a limited number of modules (each around 50K-200K gates) will be fully synthesized. Theremaining modules will be largely decided by IPR vendors. Based onthat, we can first generating a physical hierarchy with placement planand global interconnect plan, preceding a priori signal integrity, powerintegrity, and performance estimation. Information of area, powerconsumption, interfaces for each module is obtained either from IPRvendors or from early estimation algorithms. Concept of such a methodhas been introduced in our early papers [2-3].

Next, the wring requirements will be estimated based on Rents ruleor architecture specific comparable principles or semi-empirical rules.Currently, several algorithms exist for various circuitry types such asmicroprocessors, memories, CMOS gate-array, and logic chips.However, an SoC consists from many functional blocks, which includemicroprocessors, memories, logic, gate array, and maybe RF/analogfront-end. Besides, SoCs can have different architectures such as bus-

based SoCs or network oriented NoCs. Therefore, the existingalgorithm can not be used directly, new algorithms and tools must bedeveloped. This may be done by recursively applying the existingalgorithms for individual circuitry types and integrating them. Thus,proper studies of interconnectivity and Rents rule related principlesneed to be performed in close interaction with the other KTH NoCarchitecture project, where the architectural templates will bedeveloped and refined based on feedback from the work in this project.

For interconnect plan, two main subjects will be studied: (1) plan forperformance and (2) plan for noise immunity. We have developedseveral models for a priori crosstalk estimates and power supply noiseestimates for DSM circuits [2,4]. However, our previous methods needto be extended to asynchronous cases for global communications inNoCs. The performance estimator in our early paper [5] will bemodified and used.

As for the design method, we will use the dynamic interconnectlibrary (DIL) based method [3]. In this method, most of interconnectissues are externally linked to the state-of-the-art circuit design

3


4/8

method, and hence has the lowest impact of the existing methodology.As we mentioned in above, we will describe the physical properties andconstraints as interconnect IPRs. However, the conventional fixed- andprecharacterized library approach used for transistors will not work forinterconnects, because in SoCs, there will be millions of interconnect

nets and their characteristics are strongly layout-dependent. The DILwill facilitate this issue. This is because the DIL is a collection of hierarchical interconnect models and transceivers. By integrating someautomated algorithms and user constraints, it will allow us toautomatically select the best wire (virtual wires) for interconnectingvarious modules (with changeable wire width and spacing, optimalrepeater insertion, and best signaling schemes). Currently, apreliminary version of dynamic interconnect library has beendeveloped by the applicants and it was successfully applied for earlyestimates in a protocol processor IPR module [5]. In this work, we aimto extend this library particularly the efficient and automated

algorithms for interconnect synthesis and various signaling schemessuch as LVDS and single-end terminated signaling etc..Based on the a priori estimates and the new design method, we are

hence able to evaluate various communication architectures andsystem performance. Such a performance modeling environment andsystem simulator need to be developed and we have taken some initialsteps to this directions already [5]. We need to study differentcommunication schemes under the established interconnectconstraints and find appropriate circuit and architecture solution. Muchof this work can capitalize our earlier strong background in ATM andwireless link area established during 1990s.

As for the novel mixed-signal isolation techniques, our special focuswill be:(1)Low noise power distribution strategies with self-decoupling and

area array I/O distribution;(2)Optimal decoupling allocations and their early estimates; and(3)Trade-off analysis of quality factors and mixed-signal isolations for

RF/mixed signal integration.(4)Architectural strategies for reducing the power distribution

constraints (e.g. based on randomization feasible within GALS(globally asynchronous, locally synchronous concepts [10])

The above four issues will be integrated into our interconnect-centricdesign techniques. Besides, we need to mention that early powerdistribution analysis and decoupling allocation are essential foraccurate system plan. This is because in future DSM circuits powerdistribution will consume a large number of wiring resources as well asthe chip area.

On the communication link plan our focus will be on selecting theproper driver design schemes (transmitter/receiver), communication

4


5/8

protocol schemes and their performance analysis with NoC content,and local MAC (media access controller) structures and theirencapsulation as IPRs. Due to different performance requirements, afew such schemes need to be established. Based on NoC platformconcepts, packet switched topologies will be under main focus instead

of circuit switched (or bus) structures.Limitations:

We can only focus on a small portion of the interconnect-relateddesign problem. For example, our method is so far limited to hardwaredesign issues. Principally this may also be extended tohardware/software partitioning but that will need much additional work[6]. In addition, we only consider the physical hierarchy at global level.Local optimization for system structure and communication is out of this work. However, as stated in many recent papers that in futureDSM circuits, the local interconnect is not as bad as that because

length of these interconnects scales down when the module sizescales. The problems for global interconnects are dramaticallyincreasing as the number of modules integrated in an SoC increases.Packet oriented communication schemes are not well established atchip level, so some pioneering work will be required involving obviousrisks. The role of performance modeling will be emphasized due to this.

3: What is new in the presented approach?Interconnect-centric SoC design is an emerging area. To our

knowledge, most of previous activities of interconnect-centric designare focused on random logic circuits or microprocessors [7]. Many of the existing interconnect models (include some new developed onessuch as the wire distribution model by J. D. Meindl [8],GeorgTech.) arenot applicable to complex SoCs particularly the network-based SoCarchitecture. As for the deign method, a research group in UCLA(J.Cong) proposed a completely new flow for interconnect-centricdesign [9]. They are also making significant efforts in developing newalgorithms to support such a design flow. However, our DIL-basedmethod is innovative. In this method, there are least changes from thetodays circuit design flow. The interconnect IPRs externally link to the

existing design flow and hence, we believe this method will be at thelowest cost and the lowest risk.Besides, this work closely cooperates with projects on NoC

architectures and Design Methodology leaded by Prof. Axel Jantsch,KTH (as a supporting team of this project). Our physical-based models,methods, and algorithms will be directly used and examined in thatwork. The combination of these two projects will create manyinnovative researches and may bring us as a leading group in NoC

5


6/8

research. The performance estimation tools and concepts as well ascommunication link structures and performance will be very valuableissues for the other KTH NoC methodology project.

4: Why will this project succeed?

As outlined above, we have gained much knowledge in DSMinterconnect modeling and analysis in our previous studies as well asin our ongoing projects. From 1996-2001, we had 5~7 Ph.D. studentsworking in a reverent research area such as mixed-signal design,interconnect modeling and estimate, signal and power distribution, andclock distribution. We are also collaborating with UTU and TUT inFinland in the project COMPLAIN with special focus on SoCcommunication circuit design. Furthermore, we have an industrialpartner Mentor Graphics, who is cooperating with us in signal integritystudies and interconnect synthesis. We believe they will provide ususeful directives in our research. Besides, we will also get usefuldirectives from the NoC project and their partners (VTT, Ericsson Radio,Nokia, Saab Dynamic, Spirea). On international collaboration, we are apartner of EU 6 th Framework Innovative Research Project onInterconnect-centric SoC Design. We already have well-establishedcollaboration with other partners such as IMEC, University of Ghent,Philips, Infinion etc.

5: Impact if succeedWe try to address the interconnect issues in early system decisions

without big changes of the existing circuit design flow. If this issuccessful, it will be a lowest risk solution in coping with theinterconnect constraints and reduce the design iteration thus greatlyimprove SoC productivity and reduce design cost. In addition to itspotential applications in SoC design community and businessopportunities, we may also be a leading research group internationallyin interconnect-centric design and interconnect IPR development.

6: Measurable mid-term and final goalsafter 24 months

a. Develop a network-based wiring model for NoC;b. Complete an efficient power distribution algorithm with focus on

asynchronous circuits and a priori decoupling allocation;c. Complete an algorithm of repeater insertion with crosstalk and viaresistance constraints;

d. Studies on various on-chip signaling techniques in terms of bandwidth, wiring demand, power consumption, and robustness;

e. Comparative studies of various on-chip communicationarchitectures in terms of bandwidth, wiring demand, powerconsumption, and robustness; provide physical-level guidelines to

6


7/8

the NOC project in defining the communication protocol stack of NOCs.

f. Proposals for communication link architectures from interfacecircuits to MAC.

after 54 months

a. Implementation of the algorithms in the dynamic interconnectlibrary;

b. Manual demonstration of interconnect IPRs;c. Define and manual demonstrate the interconnect-centric design

method;d. Demonstrate application examples of the method in global

communication design of NOCs.

8: Metrics of success

a. International publications and patents (we expect roughly 5 peer-reviewed papers and 1 patent).b. Methods and tools for interconnect and communication link

performance analysis, where some of these will be used outside theresearch group;

c. Methods and algorithms will be used for system architecturedefinition and performance analysis in early design stages for SoCsand NOCs;

d. Exploitation of results and concepts in industrial designs towardsend of the project.

References:1) L. -R. Zheng , H. Tenhunen , Physical issues in Network-on-Chip,

presented as a tutorial lecture in the workshop of European Solid-StateCircuit Conference (ESSCIRC01) , Villach, Austria, Sept. 18-20, 2001.(http://www.ele.kth.se/~lrzheng/papers/ physicalissueNOCs_lirong.pdf )

2) L.-R. Zheng , H. Tenhunen , Design and analysis of power integrity indeep submicron system-on-chip circuits, Analog Integrated Circuits andSignal Processing , vol. 30. no.1, pp.15-30, 2002.(http://www.ele.kth.se/~lrzheng/papers/Norc_ALOG.pdf)

3) L. -R. Zheng , D. Pamunuwa , and H. Tenhunen , Accurate a priorisignal integrity estimation using a multilevel dynamic interconnect modelfor deep submicron VLSI design, In Proc. 2000 Europe Solid State Circuit Conference , pages 324-327, Stockholm Sweden, September 2000.Frontier Group, ISBN 2-86332-249-4.(http://www.ele.kth.se/~lrzheng/papers/ESSCIRC00_final.pdf)

4) L. -R. Zheng , H. Tenhunen , Fast modeling of core switching noise ondistributed LRC power grid in ULSI circuits, IEEE Transactions on

7
http://www.ele.kth.se/NOC)http://www.ele.kth.se/~lrzheng/papers/Norc_ALOG.pdf)http://www.ele.kth.se/~lrzheng/papers/ESSCIRC00_final.pdf)http://www.ele.kth.se/NOC)http://www.ele.kth.se/~lrzheng/papers/Norc_ALOG.pdf)http://www.ele.kth.se/~lrzheng/papers/ESSCIRC00_final.pdf)


8/8

Advanced Packaging , 24(3):245-254, 2001.(http://www.ele.kth.se/~lrzheng/papers/EPEP_IEEE_AP.pdf).

5) T. Nurmi, L. -R. Zheng , J. Isoaho, and H. Tenhunen , Early estimation of interconnect effects on the operation of system-on-chip platforms, InProc. European Conference on Circuit Theory and Design , pages 197-202,

Espoo, Finland, August 2001.(http://www.ele.kth.se/~lrzheng/papers/ecctd_cam.pdf)6) A. Postula , A. Hemani, and H. Tenhunen , Interconnect centered design

methodology for System-on-Chip, In Proc. of the 17th IEEE NORCHIPConference , pages 197-204, Oslo, Norway, Nov 1999.

7) D. Sylvester, K. Keutzer, System-level performance modeling withBACPAC Berkeley Advanced Chip Performance Calculator, Workshopon system-level interconnect Prediction , pp.109-114, Monterey, CA, April10-11, 1999.

8) J. A. Davis, J. D. Meindal, A stochastic wire length distribution for gaga-scale integration, IEEE Trans. Electronic Devices , vol.45, no.3, 1998.

9) J. Cong, An interconnect-centric design flow for nanometer technologies, IEEE Proceedings, vol.89, no.4, pp.505-528, April 2001.10) A. Hemani, T. Meincke, A. Postula , T.Olsson, P.Nilsson, J. berg,

P.Ellervee, and D. Lundqvist, Lowering power consumption in clock byusing globally asynchronous locally synchrounus design style, in Proc. of the 36th IEEE/ACM Design Automation Conference (36th DAC) , pages 873-878, New Orleans, LA, USA, Jun 1999.(http://www.ele.kth.se/ESD/doc/ar99/ahmed/dac99final.ps.gz )

8
http://www.ele.kth.se/~lrzheng/papers/EPEP_IEEE_AP.pdf).http://www.ele.kth.se/~lrzheng/papers/ecctd_cam.pdf)http://www.ele.kth.se/ESD/doc/ar99/ahmed/dac99final.ps.gzhttp://www.ele.kth.se/~lrzheng/papers/EPEP_IEEE_AP.pdf).http://www.ele.kth.se/~lrzheng/papers/ecctd_cam.pdf)http://www.ele.kth.se/ESD/doc/ar99/ahmed/dac99final.ps.gz

interconnect vr

Documents