interconnect - carleton universitytjs/4700/lec15/interconnectscaling...1 stanford university 1...

1

Stanford University Saraswat / EE311 / Interconnect Scaling1

Prof. Krishna Saraswat

Department of Electrical EngineeringStanford UniversityStanford, CA 94305

[email protected]

Interconnect


Outline

•Interconnect scaling issues

•Gate electrode

•Aluminum technology

•Copper technology

2


Why should we look at interconnects?

Basics and Background Interconnect Parameters: resistance, capacitance,inductance

Interconnect Metrics: Delay and Area Calculations

Scaling Related Issues: Delay

Problems

Solutions

Scaling Related Issues: Power

Current Interconnect Technology


Scaling of Minimum Feature sizeand Chip Area

Ref. A. Loke, PhD Thesis, Stanford Univ. 1999

101

102

103

104

1970 1980 1990 2000 2010

logic

memor y

Year

memory

Chip

Are

a (m

m2 )

1970 1980 1990 2000 2010

production

development

Year

0.01

0.1

1

10

Mim

imum

Geo

met

ry (µ

m)

3


Scaling of a chip and interconnections


Scaling of global interconnections

OldNew (scaled)

Scaled wires are:•Longer (chip area scaling)•Thinner (minimum dimension scaling)

4


60 80 100 120 140 160 18010-2

10-1

100

101

Technology Node (nm)

Del

ay T

ime

(ns) Longest Interconnect Delay

Typical Gate Delay

On-chip wires are getting slower

Increase in R, L and C



Basics and Background Interconnect Parameters: resistance, capacitance,inductance

Interconnect Metrics: Delay and Area Calculations




5


Types of Interconnects• Dimension based

• Local • Intermediate/semiglobal• Global

• Function based • Signaling• Clocking • Power/Gnd distribution

Global Local

Cross Sectional View:For Height, Width and Spacing

Top View: For Length


• Delay• Power dissipation• Bandwidth• Area• Joule heating• Data reliability (Noise)

• Cross talk

Depend on R and C and L !

Performance Metrics: Signaling Wires

• Reliability• Electromigration

6


Line Resistance and Capacitance

R = !L

WH

!

CIMD

= Kox"o

HL

LS

!

CILD

= Kox"o

WL

Xox

• What metrics does Resistance impact???? •With scaling of technology L increases, Xox, LS W and H decrease• As a result R, Cox and CI increase

AR=H/W


Space Width (!m) [=Line Width]

0.0 0.5 1.0 1.5 2.0 2.5 3.0

Ca

pa

cita

nc

e (fF

/mm

)

0

100

200

300

400

500

Line To Ground

Line To Line

Total

CAPACITANCE

Capacitance in Multilayer Structures

H

W

CILD

CIMDAR=H/W

M1

M3

M2

)ARIMDAR

ILD(l2IMDC

ILDCtotintC !

!+=+=

In general

CILDCIMD

Cintot

Cap

acita

nce

7


Capacitance: Impact on Interconnect Metrics

Higher Packing Density⇓

Decreased Space BetweenInterconnects

⇓Higher RC-Delay, power and

crosstalk

Capacitance Reduction is Important for Performance Enhancement

2

IMD

ILDtotint

IMDtalk

totint

2

totint

totint

AR1

1

C

CX

CfVCP

RC

!"#

$%&

+

='

'=

'

((

)

*

RC-Delay

Power

Crosstalk


What Capacitance to use for Delay?

• Nominal Cinttot=CIMD+CILD

• Worst Case Cinttot=2CIMD+CILD

• Best Case Cinttot=CILD

o oS

Depends on switching condition on adjacent wires

S

S

Not only total capacitance plays a role in delay, IMD plays a very import. Role

CIMD ~ 70% of Cinttot

8


Interconnect Parameters at High Frequencies • In general complicated: No dedicated return paths

•Resistance: R(f)– Two components: signal and return path– Frequency effects

– Current distribution in signal (Skin effect)– Return path choice, thus resistance

• Inductance: L(f)– Self: Area enclosed between signal & return path (larger area => larger L): Can effect delay– Mutual: Effects crosstalk (long range)

•Capacitance: C(f)– Relatively constant

How is current distribution in signal and its return path determined ??

s

Return path Current dist.

in signal wire


Current Distribution and Return Path

jwCG

jwLRZ

+

+=

• Impedance (Z) is minimized • At high frequency minimizes L• Return path closer

• At lower frequency minimizes R• Return path could be far away if it lowers return resistance

S

R

S RHigherFrequency

L ~ 0.3-0.7 nH/mmC ~ 0.15-0.25 pF/mm Z0= (L/C)1/2 ~ 35- 65Ω

9


What About Skin Effect for Resistance?

!

SkinDepth =1

"µ#f=2.1

ff in GHz, S.D in µm

• Copper

• Be careful when comparing skin depth to dimensions• Which dimension?: tall vs. wide

• Depends on the return path• Frequency of interest is not clock freq. But rise time associated freq.

• Example: f = 3GHz ⇒ skin depth = 1.2µm

1 µm

3 µm

1.2µm

Case 1: Important (from sides)Case 2: Not important(from vertical direction)


• Can we not model anything because of complexity of R and L?

• No, there is a lot we can predict without frequency dependencies Using Rdc and C

• Most interconnects are still not skin effect limited: Rdc ok

• L is important for inductive cross talk• Not so important for delay

• Delay and power important for most interconnects

• Rdc, we need to model more accurately

Summary: R, L and C Parameters

10


The Truth about Interconnect Delay: Don’t neglect the driver!

• Driver Delay

• Interconnect Delay– LC regime

– RC regime

( )Lwdiffdr ClCCZ ++

)lC(ZlCC

LCLl

v

lw0w

w

www ===

• Total Delay combination of three delays• Dominant component depends on

– wire length & cross-sectional dimensions– driver size: larger =>lower Zdr & higher Cdiff

• Delay RC only under certain conditions !!!

Zdr, Cdiff Rw, Cw, Lw,,l

l

CL Zdr : Driver resistanceZ0 : Characteristic impedance of wireν : Velocity

A. Deutch et. al., IEEE trans. Microwave theory and techniques, oct. 1997

)ClC)(lR5.0( Lww +


Interconnect Delay

LCRCDriver D

elay

Length

Del

ay

Zdr>Z0 (slope)

Local wires

Zdr(Cdiff+CL)

• Driver small, wire length short, cross section small => Zdr>Z0

• Inductance (LC) almost never important• Mostly driver delay dominates => want low Cw

Delay: Local wires

)ClCC(Z~Delay Lwdiffdr ++

11


• Delay has another component– number of round trips needed to ring up the line (Z0>Zdr desirable)

• Inductance only important for case 2a • Very long wires => RC delay conservative (diffuse RC transmission line model better)

Case 1 (Small driver)• Zdr> Z0 (same as local wire case)• Inductance not important

2wwLwdiffdr lCR5.0)ClCC(ZDelay +++!

Case 2a (Large driver)• Zdr < Z0 and l<lcrit (Rwl/2Z0 < 1)• Inductance important• Entire RLC model must be considered

Interconnect Delay

LCDriver Delay

Length

Del

ayglobal wires

Zdr > Z0 (slope)

RC

RC

Global wiresZdr < Z0

Length

Del

ay

LCDriver Delay

w

0

critR

Z2l !

Case 2b (Large driver)• Zdr < Z0 and l>lcrit (Rwl/2Z0 >1)• Inductance not important• Slow diffused RC signal

2ww lCR5.0Delay !

Delay: Semiglobal and Global Wires


w

0

w

w

w

crit

R

Z77.2

C

L

R

77.2l ==

Ideal Cu resistivity

ALDResistive Regime

Inductive Regime

* L=2 nH/mm

L=1 nH/mmL=0.2 nH/mm

0.18 0.15 0.12 0.1 0.07 0.05

Technology Node (µm)

0.035

• Global wires are becoming more RC in terms of delay in future

• However L is still very important in Cross talk (long range) and noise

• L also important in delay for wide global wires

J. A. Davis et. al. Proc. IEEE, March 2001

Kapur et. al. , IEEE Trans. Elec. Dev., April 2002

Delay: When is inductance important? (II)

12


Chip Size

• Device Size Limited• Regular compact structure• Needs fewer interconnect

levels

• Wire Pitch Limited• irregular structure• Needs more interconnect

levels• Performance impacted more

by interconnects

Μ1

Μ2

Μ3PMOS

NMOS

Memory: SRAM, DRAM Logic, e.g., µ-Processors


Wire-length distribution

1 10 100 1000

1E-4

1E-2

1E0

1E2

1E4

1E6

1E8

Interconnect Length, l (gate pitches)

2D

3D

Local GlobalSemiglobal

LSemi-global

LLocal

• Wire-length distribution (in terms of gate pitches) for a futuristic logiccircuit with 180 million gates.

• Metal tiers determined by LLoc and LSemi-global boundaries defined bydesign constraints, such as maximum allowable delay, current density, etc.

• More wires can be accommodated in the lower levels.• By placing wires in higher levels design constraints can be met but will

need more metal levels

global

semiglobal

local

13


Rent’s Rule

T = k N P

T = # of I/O terminalsN = # of gatesk = avg. I/O’s per gateP = Rent’s exponent

N gates

1

10

100

1000

1E+02 1E+04 1E+06

Number of Gates, N

Num

ber

of

I/O

pin

s, T

Rent's Rule fit

Intel Data

T=2.09

N^(0.36)T = 2.09 N0.36


Block A with NA gates

Block B

Block C

• Conservation of I/O’sTA + TB + TC = TA-to-B + TA-to-C + TB-to-C + TABC

• Values of T within a block or collection ofblocks are calculated using Rent’s rule,e.g.,

TA = k (NA) P

TABC = k (NA+ NB+ NC) P

• Recursive use of Rent’s rule gives wire-length distribution for the whole chip

TA-to-B = TA + TB -TAB

TB-to-C = TB+ TC -TBC

Determination of Wire-length Distribution

Ref: Davis & Meindl, IEEE TED, March 1998

14



Basics and Background

Scaling Related Issues: Delay Problems

Solutions




Future Problems (Delay)

• Local: Wires whose length shrinks• S1: AR maintained (3D shrink)• R up by α (worse) where α = scaling factor• C down by α (geometrical effect)• C down by low-k material• RC delay down as low-k• Delay going up compare to gate delay

• Semiglobal/Global: Length does not shrink• Much worse than local

All types of signal wires delaysare deteriorating wrt gate delaywith scaling even with newlow-k materials !

S2S1

S3

Simple Scaling ScenariosWire Cross sectionScaling Scenarios

Wire length Scaling

Future

Global Local

.

15


Scaling of Interconnect Cross Section Dimensions

GlobalSemi-globalLocal

Width

Height

2000 2004 2008 2012Year

1200

1000

800

600

400

200

0

Dim

ensi

ons

(nm

)

0.18 0.12 0.07 0.05Technology Node (µm)

0.035

HeightWidth

Global

Semiglobal

Local

ITRS ‘99 dimensions: local, semi-global, global wires


Solutions to Mitigate the Interconnect Problems

Technological Solutions Material Solutions: Lower resistivity materials and lower-dielectric constant

(Existing Paradigm)

Future Solutions: 3-D integration and Optical Interconnects

Circuit Solutions Repeaters (Existing Paradigm)

Future Solutions: Low-swing signaling and near speed of light electricalinterconnects

Architectural/Combination Solutions

16


Impact of Interconnect Resistivity

• Will superconductors really improve the circuit speed?• Is Cooling conventional conductors to 77°K sufficient?

Al


Interconnect and gate delay vs chip area and minimumfeature sizes for various interconnect materials

WSi 2WSi 2

Delay calculated for the longest interconnect on a chip L =chip area

2

17


Limits of 4 Commonly Used Materials forInterconnections

Ref. Gardner, et.al., IEEE Trans Electron Dev., March 1987.

Copper

Maximum length limited by τG = τI


1

2

3

4

5

6

7

8

9

10

11

12

13

14

Al & SiO2 (! = 4)

Cu & SiO2 (! = 4)

Al & low-! (! = 2)

Cu & lo w-! ( ! = 2)

0.092007

0.132004

0.182001

0.251998

0.351995

Tec hnology Generation

µmYear

Why Cu and Low-k Dielectrics?

Reduced resistivity and dielectric constant results in reduction in number ofmetal layers as more wires can by placed in lower levels of metal layers.

global

semiglobal

local

Source: Y.Nishi T.I.

18


Low Dielectric Constant (Low-k) MaterialsOxide DerivativesF-doped oxides (CVD) k = 3.3-3.9C-doped oxides (SOG, CVD) k = 2.8-3.5H-doped oxides (SOG) k = 2.5-3.3

OrganicsPolyimides (spin-on) k = 3.0-4.0Aromatic polymers (spin-on) k = 2.6-3.2Vapor-deposited parylene; parylene-F k ~ 2.7; k ~ 2.3F-doped amorphous carbon k = 2.3-2.8Teflon/PTFE (spin-on) k = 1.9-2.1

Highly Porous OxidesXerogels k = 1.8-2.5

Air k = 1


Repeaters As a SOLUTIONRepeater

R/n

C/n

! L =3.56 "Kox# o$

%2L2

! Ln

=3.56 "Kox# o$

%2L

n

& ' ( )

* + 2

! Ln

+ !G" # $ %

& ' n =

3.56 (Kox) o*

+2L2

n

"

# $

%

& ' + n!G

Propagation delay of a long interconnect line is

By breaking the long line into n smaller lines the delay of each line isreduced quadratically

The total wire delay is thus reduced significantly as τG reduces with scaling

τL/nτG

However, repeaters have Power and Area penalties

19


Repeaters: How Good Is It?

• Even with repeaters, 7.5X Clock at 35nm node 8X increasecompared to 180nm node

• By increasing the distance between the repeaters power canbe reduced at the expense of delay

0.18 0.15 0.12 0.1 0.07 0.05

Technology node (µm)

0.035

Wire

Del

ay (i

n nu

mbe

r of

clo

ck c

ycle

s)

Year

Non-re

peat

ed

optimal

25% Delay penalty

Delay

repeated



• ITRS wire dimensions: justified based on barely enough metal levels to fit the wires• Separation of memory and logic area because different wire length distributions• Rent’s rule based distribution for logic area

0.18 0.15 0.12 0.1 0.07 0.05Technology Node (µm)

Rep

eate

rs p

er L

onge

st G

loba

l Lin

e

Year

Number of Repeaters Required

A fraction of the chip area would be occupied by repeatersAdditional power will be consumed by repeaters


p = 0.6

p = 0.55Rent’s exponent of0.55 is reasonable in microprocessors

Num

ber o

f Rep

eate

rs

Year


20


Repeater Area Penalty

Significant area occupied by repeaters in future Via blockage non-negligible for wire-limited chips


p = 0.6

p = 0.55

Rent’s exponent


p = 0.6

p = 0.55

Rent’s exponent

Via blockage by repeaters on global wires Fractional chip area occupied by repeaters



Basics and Background



Power Dissipation

Power Removal (thermal Problem)

Power Distribution


21


Chip Power: Breakdown • Dynamic Power: CV2f• Leakage power: devices• Short circuit power during switching• Analog components (sense amps etc.):static power

Dynamic Power

Signalingclocking I/O

DevicesClockingInterconnects

Logic

SignalingInterconnects

memory

Latches Buffers Off-chipload

• Interconnect power• Due to Cint: dissipated in devices• Due to Rint: Joule heating (makes things worse)


Power breakdown at the 180nm node

Logic (15%)

Signaling Interconnects (46%)

Memory (4%)

Clock (36%)

4%4%

23%Semi-global lines

13%

2%

2%

15%

29%

9%

Local lines

Logic(Dynamicpower)

Latches

Distribution(Interconnects)

Repeaters

Memory (dynamic power)

Memory (leakage power)

Global lines

22


Power breakdown at the 50nm node

Logic (27%)

Signaling Interconnects (27%)

Memory (17%)

Clock (28%)

5%5%

Local lines

Logic(Dynamicpower)

Latches

Distribution (Interconnects)

Memory (dynamic power)Memory

(leakage power)

Global lines

Repeaters

Semi-global lines

23%

< 1%

17%

25%

2%

5%

12%

5%

Logic (leakage power)


µprocessor Power Projections

23


Total power dissipation on chip

• Power dissipation rising to exorbitant proportions !!!

• Need to come up with novel schemes to reduce power in each department


Thermal problem

3550 70 130 180100

0

1

2

3

4

0

0.2

0.4

0.6

0.8

1

1.2

Technology Node [nm]

Die

lect

ric C

onst

ant

Higher T ⇒ • higher R• lower reliability

Better circuit design techniques needed to reduce powerBetter cooling techniques needed

Ther

mal

Con

duct

ivity

[ W

/m

K ]

Substrate

Higher T

Lower T

I am Hot !

24


>100A will flow on these wires

The problems Caused by Increased Power

As T ⇑ R ⇑, RC delay ⇑10°C ⇑ , Speed ⇓ 5%

PERFORMANCE

RELIABILITY

10°C ⇑ , MTF ⇓ 50%

!

MTF =A

rmJnexp

Ea

kT

"

# $

%

& '

Mean time to failure

Electromigration induced hillocks and voids

Hillock VoidMetal

MetalDielectric


Impact of Vias on the ThermalCharacteristics of low-k Interconnects

• Vias have much higher thermal conductivity than the dielectricmaterials (ILD)

• Can be efficient thermal dissipation paths

S W2

Via

Mn

Mn-1

V

ia

Separa

tion

W1S W2

Via

Mn

Mn-1

V

ia

Separa

tion

W1S W2

Via

Mn

Mn-1

V

ia

Separa

tion

W1S W2

Via

Mn

Mn-1

V

ia

Separa

tion

W1

V

ia

Separa

tion

25


Commonly used case 1model overestimatesinterconnect temperature

Case 3 represents themost realistic worst casecondition0

50

100

150

200

0 1 2 3 4

case1

case2

case3

Tem

p. R

ise Δ

T [°

C]

Current Density, J [MA/cm2]

Case 1 Case 2 Case 3

Simulation of WireTemperature: Role of Vias


3D Thermal Analysis of InterconnectsTHERMAL-ELECTRICAL ANALOGY

Thermal ElectricalTemperature T [K] Voltage V [V]Heat q’ [J] Charge Q [C]Heat flux q [W] Current I [A]Thermal resistance RT [K/W] Electrical resistance R [V/A]Thermal capacitance CT [J/K] Electrical capacitance C [C/V]Heat diffusion RC transmission line

!

"2

T = RTCT

#T

#t

!

"2

V = RC#V

#t

Mn

ILDMn+1

Mn-1

IMD

Via

Tem

pera

ture

Ris

e Δ

T [°

C]

Location along metal wire [µm]

02468

1012141618

0 20 40 60 80 100

Polymer, ANSYSPolymer, HSPICESiO2, ANSYSSiO2, HSPICE

Chiang and Saraswat, VLSI Symp, June 2001

3-D THERMAL CIRCUIT

THERMAL ANALYSIS USING SPICE.

Via Via

kSiO2

kpolymer

kair

Via Separation [µm]

k ILD

, eff

[W

/mK

]

0.01

0.1

1

10

100

0 100 200 300 400 500

ILD: SiO2

polymer

air

EFFECT OF VIAS

26


• Temperature of global interconnects rise sharply for low-k ILDmaterials.

• Embedded low-k approach, e.g., air-gap shows excellent results

100

150

200

250

300

0.5 1.5 2.5 3.5

air

aerogel

polyimide

HSQ

FSG

air-gap

Current Density, J [M A/cm2]

Top

Met

al T

emp.

Tm

[°C

]65nmNode

Wire Temperature vs. Low-k ILD

Chiang, Shieh and Saraswat, VLSI Symp, June 2002


Embedded Low-k Dielectric ApproachWhy embed Low-k dielectriconly between metal lines?

•Capacitance is dominatedby CIMD

•Use a low-k dielectric as IMD

•Heat flows vertically

• Use a high thermalconductivity material ⇒ SiO2

VIA

VIA

METMET LOWk

METMET LOWk

SiO2(k~4.2)

SiO2(k~4.2)

SiO2(k~4.2)

Source: Y. Nishi

27


Impact of Joule Heating on RC Delay

• RC delay is strong function of current density because of JouleHeating

• Greater RC degradation for lower-k materials

20

40

60

80

100

120

140

0.5 1.5 2.5 3.5

FSGHSQair-gappolyimideaerogelair

Current Density, J [M A/cm2]

RC

[pse

c/m

m]

65nmNode

Chiang, Shieh and Saraswat, VLSI Symp, June 2002


a)both j and kILD scaleaccording to ITRS.

b) j scales with ITRS, but kILDstops scaling at 65nmnode.

c)j stops scaling at 65nmnode, while kILD continuesscaling.

d)both j and kILD stopsscaling at 65 nm node.Technology Node [nm]

Tem

pera

ture

Ris

e Δ

T [°

C]

130 90 65 45 220

5

10

15

20

25

30scenario (a)

scenario (b)

scenario (c)

scenario (d)

Temperature in Multilevel Metal Layers

• With the help of vias as efficient thermal paths, the wiretemperature can be significantly lower than that predicted fromoverly simplified 1-D thermal model.

• Therefore, the thermal problem associated with low-k insulatorsis not as bad as it appears.

• Beyond 45nm node closer packing of vias will alleviate thetemperature rise problem.

28


Global Signaling Wire: Repeater PowerMinimization With Delay Tradeoff

• Tolerable delay penalty depends on architecture

• Still 20W of power dissipation due to repeaters at 50nm node

• With about 20% more delay power dissipation by global wires with repeaters on them is now ~ 60+20=80W at 50nm node


Rep

eate

r Pow

er D

issi

patio

n (W

atts

)



Current Interconnect Technologies

Copper 6

Copper 1

TungstenLocal Interconnect

Copper 3

Copper 5

Copper 4

Copper 2

Current Al technology(Courtesy of Motorola)

Current Cu technology(Courtesy of IBM)

29


DC Resistance Modeling with Scaling:Technology Impact (I)

Diffusion barrier • Consumes progressively larger fractional area

• Barrier thickness (BT) doesn’t scale • Higher AR => larger barrier area

• Technology dictates • Minimum thickness: reliability constraints• Profile: deposition technology

Electron surface scattering• Reduced electron mobility with scaling• Depends on

• Ratio of λmfp to thickness• Interface quality: Roughness

• Technology dictates• Temperature• Copper/barrier interface quality (P)

Future

ALD IPVD C-PVD

Cu effective ρ increases in future


Problems in Scaling of Interconnections

Pure Metal Interconnect

Layered Interconnect

Surrounded Interconnect

Al

Al

Cu

ρav

Minimum Feature Size (λ)

• Resistivity increases asgrain size decreases

• Resistivity increases asmain conductor sizedecreases but not thesurrounding film size

AS λ DECREASESBarrier

Barrier

Cu

30


• Aspect ratio increase tradeoffs: Better delay and electromigration Worse power and cross talk

• In future increasing aspect ratio may not help

• Explains why AR dropped when Al to Cu switch

• Pay attention to different metrics simultaneously rather than just delay• Design window quite complex

Interplay Between Signaling Metrics (II)

Fixed length & width

Aspect Ratio (H/W)

Power α C tot

Cross talk

Resistance

Delay

Electromigration: current density

Arb

itrar

y U

nits


Electrical•Low resistivity of conductors•Low capacitance => low dielectric constant

– Low RC delay– Low power dissipation (CV2f loss)– Low cross talk

•Low contact resistanceProcessing

•Ability to contact shallow junctions•Ease of deposition of thin films of the material•Ability to withstand the chemicals and high temperatures required inthe fabrication process

•Ability to be thermally oxidized•Ability to be defined into fine patterns - dry etching

Reliability•Resistance to electromigration•Good adhesion to other layers - low physical stress•Stability of electrical contacts to Si and other layers•Good MOS properties

Requirements of the interconnection materials

31


Outline

•Interconnect scaling issues

•Silicide Gate technology

•Aluminum technology

•Copper technology

interconnect - carleton universitytjs/4700/lec15/interconnectscaling...1 stanford university 1...

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