interactions of double patterning technology with wafer...

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1 © 2006 Synopsys, Inc. (Name) Interactions of Double Patterning Technology with wafer processing, OPC and design flows Kevin Lucas, Chris Cork, Alex Miloslavsky, Gerry Luk-Pat, Levi Barnes, John Hapli, John Lewellen, Greg Rollins Synopsys Vincent Wiaux, Staf Verhaegen IMEC Leuven Belgium Predictable Success IMEC, Leuven, Belgium If it moves, chop it in half, then simulate it Kevin Lucas, Chris Cork, Alex Miloslavsky, Gerry Luk-Pat, Levi Barnes, John Hapli, John Lewellen, Greg Rollins Synopsys Vincent Wiaux, Staf Verhaegen IMEC, Leuven, Belgium Predictable Success IMEC, Leuven, Belgium

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Page 1: Interactions of Double Patterning Technology with wafer ...client.blueskybroadcast.com/SPIE/AL08/pdf/6924-02_Lucas.pdf · Interactions of Double Patterning Technology with wafer processing,

1© 2006 Synopsys, Inc. (Name)

Interactions of Double Patterning Technology with wafer processing,

OPC and design flows

Kevin Lucas, Chris Cork, Alex Miloslavsky, Gerry Luk-Pat, Levi Barnes, John Hapli, John Lewellen, Greg Rollins

Synopsys

Vincent Wiaux, Staf Verhaegen

IMEC Leuven Belgium

Predictable Success

IMEC, Leuven, Belgium

If it moves, chop it in half, then simulate it

Kevin Lucas, Chris Cork, Alex Miloslavsky, Gerry Luk-Pat, Levi Barnes, John Hapli, John Lewellen, Greg Rollins

Synopsys

Vincent Wiaux, Staf Verhaegen

IMEC, Leuven, Belgium

Predictable Success

IMEC, Leuven, Belgium

Page 2: Interactions of Double Patterning Technology with wafer ...client.blueskybroadcast.com/SPIE/AL08/pdf/6924-02_Lucas.pdf · Interactions of Double Patterning Technology with wafer processing,

2© 2006 Synopsys, Inc. (Name)

Double Patterning – additive1st trench imaging

Etch stop….

LowKBARCHM

Resist

Hard Mask etch

2nd trench imaging

Hard Mask etchResist/BARC strip

Hard Mask etch

© 2006 Synopsys, Inc. (3)

Predictable Success

transfer to dielectric

Hard Mask etchResist/BARC strip

See V. Wiaux 6924-08, next session

Outline

• DPT Lithography & Process Window• DPT Mask SynthesisDPT Mask Synthesis• DPT Physical Design• Conclusions

© 2006 Synopsys, Inc. (4)

Predictable Success

Page 3: Interactions of Double Patterning Technology with wafer ...client.blueskybroadcast.com/SPIE/AL08/pdf/6924-02_Lucas.pdf · Interactions of Double Patterning Technology with wafer processing,

3© 2006 Synopsys, Inc. (Name)

Lithography considerations @22nm• Need 30-35nm etched CD ~70nm min final pitch

Need highly controlled 140nm pitch single exposure lithoPW budget: 5% EL, 100nm DOF

• RET?No space for retargeting or AFsNeed litho sizing + etch downsize

• Patterning strategy:Poly: ~45nm litho CD (~32nm gen)

© 2006 Synopsys, Inc. (5)

Predictable Success

Cont: ~55nm litho CD (~32nm gen)M1: new resist or ~60nm litho CD

• All layers require 15nm+ etch shrinkStandard for Poly, new for Cont & M1

Min allowed space vs. # DPT conflicts

© 2006 Synopsys, Inc. (6)

Predictable Success

Upsizing reduces single exposure litho space.Creates more DPT interactions & conflicts.

0nm upsize 5nm upsize 10nm upsize 15nm upsize

Page 4: Interactions of Double Patterning Technology with wafer ...client.blueskybroadcast.com/SPIE/AL08/pdf/6924-02_Lucas.pdf · Interactions of Double Patterning Technology with wafer processing,

4© 2006 Synopsys, Inc. (Name)

DPT litho/etch topographyY

[um

]

0 0 1 0 2 0 3 0 4 0 5 0 6

-0.4

-0.3

-0.2

-0.1

0

1: n16_01_PolySi_depo.tdr 0

Y[u

m]

0 0 1 0 2 0 3 0 4 0 5 0 6

-0.4

-0.3

-0.2

-0.1

0

2: n16_02_HM_depo.tdr 0

Y[u

m]

0 0 1 0 2 0 3 0 4 0 5 0 6

-0.4

-0.3

-0.2

-0.1

0

3: n16_03_ARC_depo.tdr 0

Y[u

m]

0 0 1 0 2 0 3 0 4 0 5 0 6

-0.4

-0.3

-0.2

-0.1

0

4: n16_04_resist1.tdr 0

X [um]0 0.1 0.2 0.3 0.4 0.5 0.6

X [um]0 0.1 0.2 0.3 0.4 0.5 0.6

X [um]0 0.1 0.2 0.3 0.4 0.5 0.6

X [um]

Y[u

m]

0 0.1 0.2 0.3 0.4 0.5 0.6

-0.4

-0.3

-0.2

-0.1

0

5: n16_06_trim1.tdr 0

X [um]

Y[u

m]

0 0.1 0.2 0.3 0.4 0.5 0.6

-0.4

-0.3

-0.2

-0.1

0

6: n16_07_ARC1.tdr 0

X [um]

Y[u

m]

0 0.1 0.2 0.3 0.4 0.5 0.6

-0.4

-0.3

-0.2

-0.1

0

7: n16_08_HM.tdr 0

X [um]

Y[u

m]

0 0.1 0.2 0.3 0.4 0.5 0.6

-0.4

-0.3

-0.2

-0.1

0

8: n16_09_strip.tdr 0

m]

-0.4

-0.3

9: n16_10_lpcvd.tdr 0

m]

-0.4

-0.3

10: n16_11_reflow.tdr 0

m]

-0.4

-0.3

11: n16_12_resist2.tdr 0

m]

-0.4

-0.3

12: n16_13_trim2.tdr 0

X [um]0 0.1 0.2 0.3 0.4 0.5 0.6

© 2006 Synopsys, Inc. (7)

Predictable Success

X [um]

Y[u

m

0 0.1 0.2 0.3 0.4 0.5 0.6

-0.2

-0.1

0

X [um]

Y[u

m

0 0.1 0.2 0.3 0.4 0.5 0.6

-0.2

-0.1

0

X [um]

Y[u

m

0 0.1 0.2 0.3 0.4 0.5 0.6

-0.2

-0.1

0

X [um]

Y[u

m

0 0.1 0.2 0.3 0.4 0.5 0.6

-0.2

-0.1

0

X [um]

Y[u

m]

0 0.1 0.2 0.3 0.4 0.5 0.6

-0.4

-0.3

-0.2

-0.1

0

13: n16_14_ARC2.tdr 0

X [um]

Y[u

m]

0 0.1 0.2 0.3 0.4 0.5 0.6

-0.4

-0.3

-0.2

-0.1

0

14: n16_15_Poly.tdr 0

X [um]

Y[u

m]

0 0.1 0.2 0.3 0.4 0.5 0.6

-0.4

-0.3

-0.2

-0.1

0

15: n16_16.tdr 0

Planar vs. Non-planar results

© 2006 Synopsys, Inc. (8)

Predictable Success

Litho2 – no Etch1 patternCD bottom 55nm

Litho2 over Etch1 patternCD bottom 57nm+

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5© 2006 Synopsys, Inc. (Name)

DPT Mask Synthesis

© 2006 Synopsys, Inc. (9)

Predictable Success

DPT Decomposition/OPC/Verify• Functions:

decomposition (split & color), RET, OPC and error identification.

• High yieldg ySplit creates OPC/RET friendly layoutsOPC creates yield friendly wafer patterns

• through overlay, focus, & dose variationsVery high accuracy/predictive OPC modelsSymmetry, density uniformity

• Fast turnaround

© 2006 Synopsys, Inc. (10)

Predictable Success

• Fast turnaroundLimits complexity/iterations in decomposition algorithms

• Must successfully convert all DPT “compliant” designs

Page 6: Interactions of Double Patterning Technology with wafer ...client.blueskybroadcast.com/SPIE/AL08/pdf/6924-02_Lucas.pdf · Interactions of Double Patterning Technology with wafer processing,

6© 2006 Synopsys, Inc. (Name)

Logic contact split exampleGreen lines show

“network” of features to be decomposed

Red lines show coloring violations where redesign is necessary.

1D arrays, 2by2

© 2006 Synopsys, Inc. (11)

Predictable Success

1D arrays, 2by2 arrays, on grid contact are DPT friendly.

Smart Coloring for Violations

Line-end control critical

Overlap quality

Decomposition must ensure

© 2006 Synopsys, Inc. (12)

Predictable Success

Decomposition must ensure OPC can meet very tight accuracy tolerances- line-end control now critical

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7© 2006 Synopsys, Inc. (Name)

Yield & process window issues

Pinch, sharp corner, overlay sensitive …

© 2006 Synopsys, Inc. (13)

Predictable Success

Std. round corner current density22nm node Cu feature, max J ~1.2

© 2006 Synopsys, Inc. (14)

Predictable Success

Page 8: Interactions of Double Patterning Technology with wafer ...client.blueskybroadcast.com/SPIE/AL08/pdf/6924-02_Lucas.pdf · Interactions of Double Patterning Technology with wafer processing,

8© 2006 Synopsys, Inc. (Name)

DPT square corner current density22nm node Cu feature,

max J ~2.3

J is ~2X higher withJ is 2X higher with sharp corners.

Black’s electromigration Eq.: Mean time to failure (MTTF) can decrease by 3-4X!

© 2006 Synopsys, Inc. (15)

Predictable Success

y

Local stress at sharp corner could further accelerate failure.

DRC

Decomposition algorithm differencesBasic approach More complex algorithm

DRC violation

Small poorly printed polygon

© 2006 Synopsys, Inc. (16)

Predictable Success

Asymmetric with printing issuesHigh # of cuts, risky overlaps

Symmetric, fewer cuts, easier to OPC -> better yield

See C. Cork 6925-62, thurs. PM

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9© 2006 Synopsys, Inc. (Name)

Need for model based decomposition- Sometimes need model to predict and avoid errors

Looks fine after split but h S lit

MRC limits OPC at LE

has error on wafer

Looks

Split Option 1

DPT-aware OPC

© 2006 Synopsys, Inc. (17)

Predictable Success

bad after split but is good on wafer

Split Option 2

DPT physical design flow

© 2006 Synopsys, Inc. (18)

Predictable Success

Page 10: Interactions of Double Patterning Technology with wafer ...client.blueskybroadcast.com/SPIE/AL08/pdf/6924-02_Lucas.pdf · Interactions of Double Patterning Technology with wafer processing,

10© 2006 Synopsys, Inc. (Name)

Double Patterning in Design FlowDesign Task Goals

Std cell creation & characterization

Minimize cell widthMaximize timing/leakage performanceg g pNo design rule or DPT violations

Custom layout Minimize areaNo design rule or DPT violations

Place & route Maximize routabilityNo design rule or DPT violations

© 2006 Synopsys, Inc. (19)

Predictable Success

No design rule or DPT violations

Tapeout signoff (DRC) No design rule or DPT violations in final design

DPT standard cell generation flow

GDS Layout

Std ll t lStd cell tool GDS Import

TuneLayout

Std cell Setup

LayoutRules

ErrorReports

FixRule 1

FixRule 2

FixRule N

DPTDecomp

Tool …

External analysis

© 2006 Synopsys, Inc. (20)

Predictable Success

Corrected Layout

DesignRules

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11© 2006 Synopsys, Inc. (Name)

DPT Correction Flow Example: aoi22x1 with 2 METAL1 conflicts

Source GDS

GDS analyzed

for

2 Conflicts on METAL1 found

Pass 1Conflictscorrected

d ll

Corrected GDS1 New Conflict Corrected GDS

Pass 2Conflictscorrected

conflicts and cell optimized

and cell optimized

© 2006 Synopsys, Inc. (21)

Predictable Success

POLY & METAL1DPT AnalysisResults

DPT standard cell library migration• Took a traditional standard cell library and converted to a

DPT clean libraryMade reasonable min-space assumptions for DPT

• 70 unique standard cells• Compared cell area before and after conversion• Results:• Area shrunk ~1% after conversion (!?)• 2 possible reasons

© 2006 Synopsys, Inc. (22)

Predictable Success

A) DPT avoids halation rules min space OKB) Compaction engine improvements since library created

• Initial conclusion: Area increase is small inside Std cells

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12© 2006 Synopsys, Inc. (Name)

DPT hot spots in routed metals- typically metal2+ but also on metal1

Different circuit portions on

Si l dd l DPT h t S t b t ti ll

pMetal2 internally designed layout

© 2006 Synopsys, Inc. (23)

Predictable Success

Simpler odd-cycle DPT hot Spots can be automatically detected using rules. Most can be eliminated by slightly modifying the design rules.

This type of error accounts for ~70% of errors in routed metal.

Complex DPT routing hot spots

Those situations are too complicated for rules to detect.

Must be foundMust be found using DPT checks.

These are passed to auto-fix routine for local jumper or rip-up and reroute.

These represent

© 2006 Synopsys, Inc. (24)

Predictable Success

~30% of errors in layouts analyzed.

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13© 2006 Synopsys, Inc. (Name)

Example: jumper to avoid DPT conflict

Metal2 DPT conflict found & Metal3 landing pads &

© 2006 Synopsys, Inc. (25)

Predictable Success

Part of line causing odd cycle in Metal2 was removed using modified DFM auto-fix flow.

jumper section identified.g p

vias placed

Example: jumper to avoid DPT conflict -2

M t l2 DPT fli tN Vi d ti

© 2006 Synopsys, Inc. (26)

Predictable Success

Metal2 DPT conflict removed by jumper

New Vias and connection inserted in Metal4

This DPT conflict disappears but others remain to be fixed.

Page 14: Interactions of Double Patterning Technology with wafer ...client.blueskybroadcast.com/SPIE/AL08/pdf/6924-02_Lucas.pdf · Interactions of Double Patterning Technology with wafer processing,

14© 2006 Synopsys, Inc. (Name)

Summary and Conclusions

• Litho CD control requires significant upsizing of target litho patterns

Implications for resist etch & DPT friendly layoutImplications for resist, etch & DPT friendly layout

• DPT has new circuit failure modes to controlE.g., corner rounding, overlap & line-end position

• Complex algorithms improve area, effort & yieldE.g., symmetry, error reduction, model-based decomposition

• Need alignment of DPT methods in design & in mask

© 2006 Synopsys, Inc. (27)

Predictable Success

Need alignment of DPT methods in design & in mask synthesis

to avoid DPT issues being found only at mask data verification.

• Demonstrated automated DPT clean layout creation

Acknowledgements

• Ben Painter, Martin Drapeau, Brian Ward, Stephen Jang, Xiaopeng Xu: Synopsys p g p g y p y

• Eric Hendrickx: IMEC• Will Conley: Freescale

© 2006 Synopsys, Inc. (28)

Predictable Success

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15© 2006 Synopsys, Inc. (Name)

Interesting backup slides if time

© 2006 Synopsys, Inc. (29)

Predictable Success

3 color DPT?

© 2006 Synopsys, Inc. (30)

Predictable Success

C. Cork. PMJ 2008

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16© 2006 Synopsys, Inc. (Name)

Tone Inversion – Example SRAM

© 2006 Synopsys, Inc. (31)

Predictable Success

Positive Tone –Many Coloring Violations Negative Tone –No coloring violations

Remapping the layout problem can solve DPT errors

DPT friendly Std cell boundaries

© 2006 Synopsys, Inc. (32)

Predictable Success

Placed Std cells are DPT friendly if:- layers are gridded and single CD at boundary, OR- single color is < ½ min single expose space to boundary, OR- only left or right has multiple colors near boundary

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17© 2006 Synopsys, Inc. (Name)

DPT friendly Place & Route flow

For each ICC Switch Box

Std P&R layout

DPTPrevention

No

Local DPT-decomposition(skip if 1st time)

For each DPT Hot Spot

ICCDetail routeMetal fill

DPT ErrorRules

Mark for Reroute

Try to find a Jumper

ICC Switch

Break Odd cycle by removing part

of line

Yes

ICC Convergence Report

Rules

© 2006 Synopsys, Inc. (33)

Predictable Success

Full chip DPT-decomposition

Switch Box