inter-ic bus

HCS12 Technical Training Module 13 - IIC Slide 1

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Inter-IC Bus

(I C)2



Internal Bus

SCI1

256K FLASEEPROM

12K SRAM

ATD 1

HCS12 CPU

BKP INT MMI

CM BDM MEBI

4K BYTESEEPROM

SIM

msCAN3

msCAN2

msCAN1

SCI1

SPI 2or

PWMCH4-7

BDLCor

msCAN0

msCAN4or

IIC

SPI 1or

PWMCH 0-3

SPI 0

ATD 0

PLL PIT

ECT 8CHAN

PWM 8CHAN



IIC Features

• Compatible with I2C Bus standard

• Multi-master operation

• Software programmable for one of 256 different serial clock

frequencies

• Software selectable acknowledge bit

• Interrupt driven byte-by-byte data transfer

• Arbitration lost interrupt with automatic mode switching from

master to slave

• Calling address identification interrupt

• Start and stop signal generation/detection

• Repeated start signal generation

• Acknowledge bit generation/detection

• Bus busy detection

• Low power modes support

• Shared with msCAN 4



IIC Functional Block Diagram

Address Module IIC_Interrupt R_Data W_Data

SCL D_IN IN/OUT D_OUT



IIC Communication Protocol

START signal is defined as a high-to-low transition of SDA while SCL is high.A master may initiate communication by sending a START signal. This signal denotes the beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves out of their idle states.

Slave Address:An address byte followed by 1-bit R/W command to tell the Slave the desired direction of data transfer.

ACK Bit - Slave Transfer Acknowledge.

Stop:Master generates a Stop signal to free the bus.

Repeat Start:Repeat Start is a Start signal without generating a Stop signal to terminate communication.



IIC Registers

ADR[7:1] - Slave AddressAddress of selected IIC slave device

IBAD - IIC Address RegisterAddress Offset $0000

Bit 7 6 5 4 3 2 1 Bit 0

IBDR - IIC Data I/O Register

$0004

IIC Master initiates data transmission by writing data to this register.

IIC Master initiates data reception of next byte by reading this register.



IIC Registers

Bit 7 6 5 4 3 2 1 Bit 0

Address Offset $0001

IBC[2:0] SCL Tap SDA TapClocks Clocks

000 5 1 001 6 1 010 7 2 011 8 2 100 9 3 101 10 3 110 12 4 111 15 4

IBC[5:3] SCL2Tap Tap2Tap (Bin) (Clocks) (Clocks) 000 5 1 001 6 2 010 6 4 011 6 8 100 6 16 101 14 32 110 30 64 111 126 128

IBC[7:6] DIV 00 1 01 2 10 4 11 Reserved

I-Bus Tap and Prescale Values I-Bus Tap and Prescale ValuesDivision Factor

IBFR - IIC Frequency Divider Register

SCL Divider = DIV x {2 scl2tap + [(SCL_Tap -1 ) x tap2tap ] +2)}

SCL Hold = DIV x {scl2tap + [(SCL_Tap -1) x tap2tap] +3



I-Bus Transfer Control

Bit 7 6 5 4 3 2 1 Bit 0

Address Offset $0002

IBCR - IIC Control Register

IBEN — I-Bus EnableThis bit controls the software reset of the entire IIC Bus module.1 = The IIC Bus module is enabled. This bit must be set before any other IBCR bits have any effect.0 = The module is reset and disabled.

IBIE - I-Bus Interrupt Enable1 = IIC Interrupts Enabled

MS/SL - Master/Slave Mode Select A change from “0’ to “1” enables IIC as Master and causes a Start Signal generation. A change from “1’ to “0” changes IIC from Master to Slave & causes a Stop Signal generation.

Tx/Rx - Transmit/Receive Mode Select Selects direction of data transfer. The Master should set this bit during address transfer cycle.1 = Transmit Mode0 = Receive Mode

TXAK - Transmit Acknowledge Enable1 = No Acknowledge response is sent0 = Acknowledge signal will be sent on the 9th clock bit

RSTA - Repeat StartThe master generates a Repeat Star signal on the IIC bus by writing this bit with a logic”1”.

IBSWAI - I_Bus Interface Stop in Wait Mode1 = Will cause the IIC Bus to Halt when the CPU executes wait instruction.0 = IIC Bus continues to run normally in wait mode



I-Bus StatusBit 7 6 5 4 3 2 1 Bit 0

TCF - Data Transfer Bit1 = Transfer is complete. This bit is set on 9th clock of a byte transfer. 0 = Transfer in progress.

IAAS - Addressed as a SlaveThis bit is set when the calling address matches the I-Bus Address Register1 = Addressed as a slave and an interrupt is requested if enabled.0 = Not addressedTo clear this bit, a write to I-Bus Control Register.

IBB - I-Bus BusyThis bit is set when a Start signal is detected.It is cleared when I-Bus is idle.

IBAL - Arbitration LostThis bit is set for the following conditions:

1. SDA sampled as a low when the master drives a high during anaddress or data transmit cycle.2. SDA sampled as a low when the master drives a high during theacknowledge bit of a data receive cycle.3. A start cycle is attempted when the bus is busy.4. A repeated start cycle is requested in slave mode.5. A stop condition is detected when the master did not request it. (This bit must be cleared by software, by writing a “0” to it.)

SRW - Slave Read/WriteWhen the I-Bus is selected as a Slave,this bit indicates the R/W command bit of the calling address sent from the Master.1 = Slave transmit, Master reading from Slave.0 = Slave receive, Master writing to Slave.

IBIF - I-Bus InterruptI-Bus generates an interrupt request for the following events:1. Completion of one byte transfer.2. Reception of a matching calling address.3. When arbitration is lost. (To clear this bit, write a “0” to it in the interrupt service routine)

RXAK - Receive Acknowledge1 = No Acknowledge signal is detected on 9th bit clock. 0 = Acknowledge signal was detected on 9th bit clock.



Initialization

Initialization Sequence:

Reset will put the IIC Control Register to its default status. Before the interface can be used to transfer serial data, an initialization procedure must be carried out, as follows:

1. Update the Frequency Divider Register (IBFD) and select the required division ratio to obtain SCL frequency from system clock.

2. Update the IIC Address Register (IBAD) to define its slave address.

3. Set the IBEN bit of the IIC Control Register (IBCR) to enable the IIC system.

4. Modify the bits of the IIC Control Register (IBCR) to select Master/Slave mode, Transmit/Receive mode and interrupt enable or not.



Start Bit Generation Sequence

An example of a program which generates the START signal andtransmits the first byte of data (slave address) is shown below:

CHFLAG BRSET IBSR,#$20 ;WAIT FOR IBB FLAG TO CLEAR

TXSTART BSET IBCR,#$30 ;SET TRANSMIT AND MASTER MODE

;i.e. GENERATE START CONDITION

MOVEB CALLING,IBDR ;TRANSMIT THE CALLING ;ADDRESS, D0=R/W

IBFREE BRCLR #5,IBSR,#$20 ;WAIT FOR IBB FLAG TO SET

Stop Bit Generation Sequence

A data transfer ends with a STOP signal generated by the ‘master.’The following is an example showing how a stop condition is generated.

MASTX TST TXCNT ;TEST VALUE OF TRANSMITING COUNTER

BEQ END ;END IF NO MORE DATA

BRSET IBSR,#$01,END ;END IF NO ACK

MOVB DATABUF,IBDR ;TRANSMIT NEXT BYTE OF DATA

DEC TXCNT ;DECREASE THE TXCNT

BRA EMASTX ;EXIT

END BCLR IBCR,#$20 ;GENERATE A STOP CONDITION

EMASTX RTI ;RETURN FROM INTERRUPT

inter-ic bus

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