intel8086softwarehardwarearchitecturefull.ppt
DESCRIPTION
8086 description and guideTRANSCRIPT
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INTEL 8086Software & Hardware
Architecture
Suresh P. Nair [ME, (PhD)] MIEEEProfessor & HeadDepartment of Electronics and Communication EngineeringRoyal College of Engineering and TechnologyChiramanangad PO, Akkikkavu, Thrissur, Kerala, India
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MODULE 1 & 2
Complete idea about INTEL 8086 Microprocessor
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Topics to be covered
1. Software Architecture of the INTEL 8086.
2. Hardware Architecture of INTEL 8086.
3. 8086 Programming and program development.
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Software architecture of the INTEL 8086
Memory segmentation and addressing Block diagram of 8086 Address space & Data organization Data Types Registers Stack I/O space
RCET Microprocessor & Microcontroller 4
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Hardware Architecture of INTEL 8086
Pin Diagram and Pin Details
min/max mode
Coprocessor and Multiprocessor configuration
Hardware organization of address space
Control signals
I/O interfaces
RCET Microprocessor & Microcontroller 5
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8086 programming and program development.
Assembly Language Programming.
Instruction Set.
Assembler Directives.
Programming Exercises.
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Software Architecture of
INTEL 8086
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Software architecture of the INTEL 8086
Memory segmentation and addressing Block diagram of 8086 Address space & Data organization Data Types Registers Stack I/O space
RCET Microprocessor & Microcontroller 8
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Memory segmentation and addressing
• Von – Newman architecture & Harvard architecture
• Program Memory & Data Memory
• Need for Segmentation– To implement Harvard architecture– Easy to debug– Same Interfacing ICs can be used– To avoid overlap of stack with normal memory– Compatible with 8085
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Segmented Memory
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Memory Address Generation
• The BIU has a dedicated adder for determining physical memory addresses.
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Physical Address (20 Bits)
Adder
Segment Register (16 bits) 0 0 0 0
Offset Value (16 bits)
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Segment : Offset Address
• Logical Address is specified as segment:offset
• Physical address is obtained by shifting the segment address 4 bits to the left and adding the offset address.
• Thus the physical address of the logical address A4FB:4872 is:
A4FB0 + 4872
A9822
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Segments, Segment Registers & Offset Registers
• Segment Size = 64KB
• Maximum number of segments possible = 14
• Logical Address – 16 bits
• Physical Address – 20 bits
• 2 Logical Addresses for each Segments.
– Base Address (16 bits)
– Offset Address (16 bits)
• Segment registers are used to store the Base address of the segment.
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Segments, Segment Registers & Offset Registers
• 4 Segments in 8086– Code Segment (CS)
– Data Segment (DS)
– Stack Segment (SS)
– Extra Segment (ES)
RCET Microprocessor & Microcontroller 14
SEGMENT SEGMENT REGISTER OFFSET REGISTER
Code Segment CSR Instruction Pointer (IP)
Data Segment DSR Source Index (SI)
Extra Segment ESR Destination Index (DI)
Stack Segment SSR Stack Pointer (SP) / Base Pointer (BP)
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Block diagram of 8086
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Block diagram of 8086
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Pipelined architecture of the 8086 microprocessors
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Execution and bus interface units
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Software Model of the 8086 Microprocessors
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Address space & Data organization
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Memory address space
Storing a word in memory
What is the word in (b) in Hex?
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Aligned and misaligned data word
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Aligned and misaligned double words of data
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Storing double word in memory
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Data Types
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Unsigned word integer0 – 65,535
Unsigned byte integer0 - 255
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Data Types
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Signed integers
-128 - +127
-32,768 - +32,767
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Data Types
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Binary Coded Decimal (BCD)
Unpacked BCD
Packed BCD
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American Standard Code for Information Interchange (ASCII)
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Dedicated, Reserved, and General use Memory
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8086 Registers
RCET Microprocessor & Microcontroller 29
CS
SS
DS
ES
Segment
BP
Index
SP
SI
DI
AH
BH
CH
DH DL
CL
BL
AL
General Purpose
Status and Control
Flags
IP
AX
BX
CX
DX
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General Purpose Registers
• Normally used for storing temporary results • Each of the registers is 16 bits wide (AX, BX, CX, DX)• Can be accessed as either 16 or 8 bits AX, AH, AL
RCET Microprocessor & Microcontroller 30
AX - the AccumulatorBX - the Base RegisterCX - the Count RegisterDX - the Data Register
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General Purpose Registers• AX
– Accumulator Register – Preferred register to use in arithmetic, logic and data
transfer instructions because it generates the shortest Machine Language Code
– Must be used in multiplication and division operations
– Must also be used in I/O operations
• BX– Base Register– Also serves as an address register
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General Purpose Registers
• CX– Count register– Used as a loop counter– Used in shift and rotate operations
• DX– Data register– Used in multiplication and division– Also used in I/O operations
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Pointer and Index Registers
• All 16 bits wide, L/H bytes are not accessible
• Used as memory pointers– Example: MOV AH, [SI]
• Move the byte stored in memory location whose address is contained in register SI to register AH
• IP is not under direct control of the programmerRCET Microprocessor & Microcontroller 33
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Flag Register
RCET Microprocessor & Microcontroller 34
Carry
Parity
Auxiliary Carry
Zero
Overflow
Direction
Interrupt enable
Trap
Sign6 are status flags3 are control flag
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8086 Programmer’s Model
RCET Microprocessor & Microcontroller 35
ESCSSSDSIP
AHBHCHDH
ALBLCLDL
SPBPSIDI
FLAGS
AXBXCXDX
Extra SegmentCode SegmentStack SegmentData SegmentInstruction Pointer
AccumulatorBase RegisterCount RegisterData RegisterStack PointerBase PointerSource Index RegisterDestination Index Register
BIU registers
(20 bit adder)
EU registers
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The Stack• The stack is used for temporary storage of information
such as data or addresses.
• When a CALL is executed, the 8086 automatically PUSHes the current value of CS and IP onto the stack.
• Other registers can also be pushed
• Before return from the subroutine, POP instructions can be used to pop values back from the stack into the corresponding registers.
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The Stack
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Example for PUSH
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Example for POP
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The I/O address space
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Hardware Architecture of
INTEL 8086
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Hardware Architecture of INTEL 8086
Pin Diagram and Pin Details
min/max mode
Hardware organization of address space
Control signals
Coprocessor and Multiprocessor configuration
I/O interfaces
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INTEL 8086 - Pin Diagram
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INTEL 8086 - Pin Details
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Ground
Clock
Duty cycle: 33%
Power Supply
5V 10%
Reset
Registers, seg regs, flags
CS: FFFFH, IP: 0000H
If high for minimum 4
clks
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INTEL 8086 - Pin Details
RCET Microprocessor & Microcontroller 45
Address/Data Bus:
Contains address bits A15-A0 when ALE is 1 & data bits D15 –
D0 when ALE is 0.
Address Latch Enable:
When high, multiplexed
address/data bus contains address
information.
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INTEL 8086 - Pin Details
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INTERRUPT
Non - maskable interrupt
Interrupt request
Interrupt acknowledge
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INTEL 8086 - Pin Details
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Direct Memory Access
Hold acknowledge
Hold
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INTEL 8086 - Pin Details
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Address/Status Bus
Address bits A19 – A16 & Status bits S6 –
S3
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INTEL 8086 - Pin Details
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Bus High Enable/S7
Enables most significant data bits D15 – D8 during read or write operation.
S7: Always 1.
BHE#, A0:
0,0: Whole word (16-bits)
0,1: High byte to/from odd address
1,0: Low byte to/from even address
1,1: No selection
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INTEL 8086 - Pin Details
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Min/Max modeMinimum Mode:
+5V
Maximum Mode: 0V
Minimum Mode Pins
Maximum Mode Pins
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Microprocessor & Microcontroller
Minimum Mode- Pin Details
RCET 51
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Maximum Mode - Pin Details
RCET Microprocessor & Microcontroller 52
Status Signal
Inputs to 8288 to generate eliminated signals due to max
mode.
S2 S1 S0 000: INTA001: read I/O port010: write I/O port011: halt100: code access101: read memory110: write memory111: none -passive
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Maximum Mode - Pin Details
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DMA Request/Grant
Lock Output
Lock OutputUsed to lock peripherals off the system
Activated by using the LOCK: prefix on any instruction
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Maximum Mode - Pin Details
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Queue StatusUsed by numeric
coprocessor (8087)
QS1 QS000: Queue is idle
01: First byte of opcode
10: Queue is empty
11: Subsequent byte of opcode
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Minimum Mode 8086 System
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Minimum Mode 8086 System
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‘Read’ Cycle timing Diagram for Minimum Mode
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‘Write’ Cycle timing Diagram for Minimum Mode
RCET Microprocessor & Microcontroller 58
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Maximum Mode 8086 System
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Maximum Mode 8086 System
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Maximum Mode 8086 System • Here, either a numeric coprocessor of the type 8087 or another
processor is interfaced with 8086.
• The Memory, Address Bus, Data Buses are shared resources between the two processors.
• The control signals for Maximum mode of operation are generated by the Bus Controller chip 8788.
• The three status outputs S0*, S1*, S2* from the processor are input to 8788.
• The outputs of the bus controller are the Control Signals, namely DEN, DT/R*, IORC*, IOWTC*, MWTC*, MRDC*, ALE etc.
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Memory Read timing in Maximum Mode
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Memory Write timing in Maximum Mode
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Memory Banking
RCET Microprocessor & Microcontroller 64
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65
Interface 8086 to 6116 Static RAM
8086
A____BHE
ALE
A(10-0)D(7-0) __R/WOE*CS*
A(10-0)
__R/W
OE*CS*
D
D(7-0)
20
Latch
AddrDecoder
A(11-1)
21
A0, BHE*
A(19-12)
A(11-1)
__M/IO
___RD
___WR
Low byte
(Even Bank)
D(7-0)
D(15-8)
16
A0
RAMCS*
MEM*
BHE*
6116 (2K x8)
High byte
(Odd Bank)
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8086 Interrupts
RCET Microprocessor & Microcontroller 66
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8086 Interrupts Procedure
RCET Microprocessor & Microcontroller 67
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8086 External Interrupts
RCET Microprocessor & Microcontroller 68
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8086 Interrupt Vector Table
RCET Microprocessor & Microcontroller 69
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8086 Interrupt Vector Table
RCET Microprocessor & Microcontroller 70
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Total Memory and IVT
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8086 Control Signals1. ALE
2. BHE
3. M/IO
4. DT/R
5. RD
6. WR
7. DEN
RCET Microprocessor & Microcontroller 72
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Coprocessor and Multiprocessor configuration
• Multiprocessor Systems refer to the use of multiple processors that executes instructions simultaneously and communicate with each other using mail boxes and Semaphores.
• Maximum mode of 8086 is designed to implement 3 basic multiprocessor configurations:
1. Coprocessor (8087) 2. Closely coupled (8089) 3. Loosely coupled (Multibus)
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Coprocessor and Multiprocessor configuration
• Coprocessors and Closely coupled configurations are similar in that both the 8086 and the external processor shares the:
- Memory- I/O system- Bus & bus control logic- Clock generator
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Coprocessor / Closely Coupled Configuration
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TEST pin of 8086
• Used in conjunction with the WAIT instruction in multiprocessing environments.
• This is input from the 8087 coprocessor.
• During execution of a wait instruction, the CPU checks this signal.
• If it is low, execution of the signal will continue; if not, it will stop executing.
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Coprocessor Execution ExampleCoprocessor cannot take control of the bus, it does everything through the CPU
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Closely Coupled Execution Example
• Closely Coupled processor may take control of the bus independently.
• Two 8086’s cannot be closely coupled.
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Loosely Coupled Configuration• has shared system bus, system memory, and system
I/O.
• each processor has its own clock as well as its own memory (in addition to access to the system resources).
• Used for medium to large multiprocessor systems.
• Each module is capable of being the bus master.
• Any module could be a processor capable of being a bus master, a coprocessor configuration or a closely coupled configuration.
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Loosely Coupled Configuration• No direct connections between the modules.
• Each share the system bus and communicate through shared resources.
• Processor in their separate modules can simultaneously access their private subsystems through their local busses, and perform their local data references and instruction fetches independently. This results in improved degree of concurrent processing.
• Excellent for real time applications, as separate modules can be assigned specialized tasks
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Advantages of Multiprocessor Configuration
1. High system throughput can be achieved by having more than one CPU.
2. The system can be expanded in modular form. Each bus master module is an independent unit and normally resides on a separate PC board. One can be added or removed without affecting the others in the system.
3. A failure in one module normally does not affect the breakdown of the entire system and the faulty module can be easily detected and replaced
4. Each bus master has its own local bus to access dedicated memory or IO devices. So a greater degree of parallel processing can be achieved.
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WAIT State
• A wait state (Tw) is an extra clocking period, inserted between T2 and T3, to lengthen the bus cycle, allowing slower memory and I/O components to respond.
• The READY input is sampled at the end of T2, and again, if necessary in the middle of Tw. If READY is ‘0’ then a Tw is inserted.
RCET Microprocessor & Microcontroller 82
1 2 3 4
Clock
READY
Tw
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8086 System Memory Circuitry
1. Minimum Mode System Memory Circuitry
2. Maximum Mode System Memory Circuitry
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Minimum Mode System Memory Circuitry
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Maximum Mode System Memory Circuitry
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