intel® pentium® 4 processor-m and intel® 845e chipset platform design guide addendum for

Intel® Pentium® 4 Processor-M and Intel® 845E Chipset Platform Design GuideAddendum for Embedded Applications

April 2003

Order Number: 251319-002

2 Addendum for Embedded Applications

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Addendum for Embedded Applications 3

Contents

Contents1.0 Introduction....................................................................................................................................5

1.1 Content Overview .................................................................................................................51.2 Related Documents ..............................................................................................................61.3 Conventions and Terminology ..............................................................................................6

2.0 Intel® Pentium® 4 Processor-M for Applied Computing Transition Guidelines ......................7

2.1 Background...........................................................................................................................72.2 Enabling the Mobile Processor Transition ............................................................................82.3 Frequency Transition Sequence...........................................................................................92.4 External Logic .....................................................................................................................112.5 BIOS Enabling ....................................................................................................................14

2.5.1 Initiating the Transition Sequence in BIOS ............................................................142.5.2 Microcode Updates in BIOS ..................................................................................15

3.0 Voltage Regulator Design Guidelines .......................................................................................16

3.1 Scalable Platform Voltage Regulator Modules ...................................................................163.2 Scalable Platform Voltage Regulator Down........................................................................16

A High Frequency Transition Sample Schematic ........................................................................17

B Scalable Platform VRD Schematic .............................................................................................19

C Reference Design Schematics ...................................................................................................23

Figures

1 Mobile Processor Transition Block Diagram.................................................................................82 Transition Sequence Timing Diagram ..........................................................................................93 External Logic State Diagram.....................................................................................................114 External Logic Timing Diagram...................................................................................................115 External Logic Diagram ..............................................................................................................126 Required BIOS Modifications......................................................................................................14

Tables

1 Related Documentation ................................................................................................................62 Conventions and Terminology ......................................................................................................63 Frequency Transition Signal Overview .........................................................................................84 Timing Details .............................................................................................................................105 VRM Vendors .............................................................................................................................16


Contents

Revision History

Date Revision Description

April 2003 002 Add Scalable VRD Schematic.

June 2002 001 Initial release of this document.

Intel® Pentium® 4 Processor-M and Intel® 845E Chipset Platform Design Guide


1.0 Introduction

This document is an addendum to the Intel® Pentium® 4 Processor in 478-Pin Package and 845E Chipset Platform for DDR Design Guide. It is targeted for:

• Customers designing with the Intel® Pentium® 4 Processor-M for Applied Computing and Intel® 845E Chipset, and for

• Customers designing a scalable Intel 845E chipset platform, compatible with both the Intel Pentium 4 Processor for Applied Computing and the Intel Pentium 4 Processor-M for Applied Computing.

Designers should refer to the Intel® Pentium® 4 Processor in 478-Pin Package and Intel® 845E Chipset Platform Design Guide for the majority of their design. However, for any information pertinent to designing a scalable platform, or for combining the Intel Pentium 4 Processor-M with the Intel 845E chipset, designers should refer to this document. Design issues such as thermal considerations should be addressed using specific design guides or application notes for the processors or chipset, some of which are listed in Section 1.2, “Related Documents”.

These design guidelines have been developed to ensure maximum flexibility for board designers while reducing the risk of board related issues. The design information provided in this document falls into one of the two categories:

• Design Recommendations are items based on Intel’s simulations and lab experience to date and are strongly recommended, if not necessary, to meet timing and signal quality specifications.

• Design Considerations are suggestions for platform design that provide one way to meet the design recommendations. They are based on the reference platforms designed by Intel. They should be used as examples, but may not be applicable to particular designs.

Note: The guidelines recommended in this document are based on experience and preliminary simulation work performed at Intel while developing the Intel Pentium 4 processor, Pentium 4 Processor-M and 845E chipset based systems. This work is ongoing, and the recommendations and considerations are subject to change.

1.1 Content Overview

Section 2.0, “Intel® Pentium® 4 Processor-M for Applied Computing Transition Guidelines” contains design guidelines and BIOS guidelines for transitioning the Intel Pentium 4 Processor-M to maximum performance mode at reset.

Section 3.0, “Voltage Regulator Design Guidelines” contains design guidelines for designing in two separate voltage regulator modules (VRMs) or a single voltage regular-down (VRD) in a scalable platform.

Appendix A, “High Frequency Transition Sample Schematic” and Appendix C, “Reference Design Schematics” are references for board designers. While the schematics may cover a specific design, the core schematics will remain the same for most platforms. The schematic set provides a reference schematic for each platform component as well as common motherboard options. The schematics also include the mobile processor transition and voltage regulator design considerations contained herein. Additional flexibility is possible through other permutations of these options and components.



1.2 Related Documents

Reference the following documents for more information. All Intel issued documentation revision numbers are subject to change, and the latest revision should be used. Contact your Intel field representative for information on how to obtain Intel issued documentation.

Please refer to the Intel® Pentium® 4 Processor in 478-Pin Package and 845E Chipset Platform for DDR Design Guide for the most complete, up-to-date list of related documentation.

1.3 Conventions and Terminology

This section defines conventions and terminology that are used throughout this document.

Table 1. Related Documentation

Related Documents Order Number

Intel® Pentium® 4 Processor in 478-Pin Package and 845E Chipset Platform for DDR Design Guide 298652

Mobile Intel® Pentium® 4 Processor - M Datasheet 250686

Intel® Pentium® 4 Processor with 512-KB L2 Cache on 0.13 µ Process at 2 GHz, 2.20 GHz, 2.26 GHz, 2.40 GHz, and 2.53 GHz Datasheet 298643

Intel® 845E Chipset: Intel® 82845 Memory Controller Hub (MCH) for DDR Datasheet 290742

Intel® 82801DB I/O Controller Hub 4 (ICH4) Datasheet 290744

Mobile Intel® Pentium® 4 Processor-M Thermal Design Guide for Embedded Applications 273729

Intel® Pentium® 4 Processor for Embedded Applications Thermal Design Guide 273704

VRM 9.0 DC-DC Converter Design Guidelines 249205

Intel® Pentium® 4 Processor VR-Down Design Guidelines 249891

Table 2. Conventions and Terminology

Convention/Terminology Definition

Intel® Pentium® 4 Processor-M for Applied Computing; mobile processor

This part is identical to the Mobile Intel® Pentium® 4 Processor-M.

Intel® Pentium® 4 Processor for Applied Computing; desktop processor, or processor

This part is identical to the Intel® Pentium® 4 Processor.

Chipset Intel® 845E Chipset

Scalable

As in “scalable platform”, “scalable board”, etc. Used to describe a system that is designed to accommodate either the Intel Pentium 4 processor or the Intel Pentium 4 Processor-M.

MPM Maximum Performance Mode (enhanced Intel® SpeedStep® technology mode)

BOM Battery Optimized Mode (enhanced Intel SpeedStep technology mode)

VID Voltage Identification

VRD Voltage Regulator-Down

VRM Voltage Regulator Module



2.0 Intel® Pentium® 4 Processor-M for Applied Computing Transition Guidelines

This section contains design guidelines for transitioning the Intel® Pentium® 4 Processor-M for Applied Computing to maximum performance mode at reset.

2.1 Background

The Mobile Intel Pentium 4 Processor-M features enhanced Intel SpeedStep® technology, which allows the processor to switch between two core frequencies. The mobile processor operates in two modes, the high frequency Maximum Performance Mode (MPM) or the low frequency Battery Optimized Mode (BOM). By default, the mobile processor will boot to the lower frequency. Certain mobile chipsets, such as the mobile Intel® 845MZ or 845MP chipset, can control the transition between the two modes; however, the Intel® 845E chipset is not capable of controlling the transition. Therefore, when designing a system based on the Intel 845E chipset, additional logic is required to transition the mobile processor from BOM to MPM.

The design guidelines in this section should be used for Intel Pentium 4 Processor-M / Intel 845E chipset based platforms, as well as for scalable platforms. The BIOS guidelines provided in Section 2.5, “BIOS Enabling” specify provisions for detecting the presence of either a desktop processor or mobile processor, and only initiating transition sequence when a mobile processor is present.

Note: The Embedded Intel Architecture Group, which supports the combination of the Intel Pentium 4 Processor-M for Applied Computing and Intel 845E Chipset, does not provide full support for enhanced Intel SpeedStep technology. The only supported aspect of this feature is the transition from battery optimized mode to maximum performance mode at reset. Designers are encouraged to follow the guidelines in this document to ensure proper product support.



2.2 Enabling the Mobile Processor Transition

Figure 1 depicts a block diagram for enabling the transition of the mobile processor from BOM to MPM. The additional logic, external to the processor and chipset, required to accomplish this transition is depicted as the shaded block labeled External Logic.

Table 3 explains the various signals involved with the mobile processor transition. Additional details on these signals and the transition sequence follow in later sections.

Figure 1. Mobile Processor Transition Block Diagram

Intel ® 82845E MCH

Intel ® 82801DB ICH4

Intel ® Pentium ®

4 Processor - M

External Logic

BIOS

CLK Gen

STPCLK# SLP#

DPSLP# RI# SUSCLK

SLP#

RESET = +3.3V

Processor System Bus Hub Interface

DPSLP# BCLK

GHI# (tied low)

Table 3. Frequency Transition Signal Overview (Sheet 1 of 2)

Signal Component(s)/Pin(s) Definition/Usage

GHI# CPU (pin A6)

At the transition, GHI# is sampled to determine the mode of the processor. GHI# high = Battery Optimized Mode; GHI# low = Maximum Performance Mode. GHI# must be tied low to correctly transition to MPM. (On the desktop processor, pin A6 is called TESTHI11.)

STPCLK#CPU (pin Y4)

ICH4 (ball V23)After the BIOS initiates the process, the ICH4 asserts this signal. As a result, the CPU enters Stop Grant state.

SLP# / CPUSLP#

CPU (SLP#, pin AB26)

ICH4 (CPUSLP#, ball U21)

External logic input

After the CPU is in Stop Grant state, the ICH4 asserts SLP#. As a result, the CPU enters Sleep state. The external logic intercepts this signal as a trigger to continue the transition sequence.

DPSLP#CPU (AD25)

External logic output

After the CPU is in Sleep state, the external logic asserts DPSLP#. As a result, the CPU enters Deep Sleep state. After a specified length of time, the external logic de-asserts DPSLP# and the CPU re-enters Sleep state. (On the desktop processor, pin AD25 is called TESTHI12.)



2.3 Frequency Transition Sequence

Figure 2 depicts the timing diagram for the mobile processor frequency transition sequence from BOM to MPM.

The steps in the mobile processor frequency transition sequence are as follows:

1. From Normal to Stop Grant (in-sync with BCLK) – The BIOS enables S1 sleep state. The ICH4 asserts STPCLK#, which causes the processor to initiate a special bus cycle, Stop Grant Acknowledge. 20 BCLKs after the response phase of Stop Grant Acknowledge, the processor enters Stop Grant state.

2. From Stop Grant to Sleep (in-sync with BCLK) – The ICH4 asserts SLP#, which places the processor in Sleep state. SLP# is also an input to the external transition logic, and the assertion

RI#ICH4 (ball Y1)

External logic output

The external logic asserts RI# (ring indicator) to wake the ICH4. From that point, the ICH4 controls the return of the system to Normal state.

SUSCLKICH4 (ball AA4)

External logic inputThis is the 32.7 KHz clock used to synchronize the external logic.

BCLKCPU (pins AF22, AF23)

Clock generatorThe differential BCLK (bus clock) determines the system bus frequency.

Table 3. Frequency Transition Signal Overview (Sheet 2 of 2)

Signal Component(s)/Pin(s) Definition/Usage

Figure 2. Transition Sequence Timing Diagram

CPU VCC

BCLK/BCLK#

SUSCLK

STPCLK#

CPU bus

SLP#

DPSLP#

GHI#

RI#T2

T3

T1

NormalStopGrant Sleep

DeepSleep

StopGrantSleep Normal

T4

stpgnt

T5

T6

OFF

Battery Optimized Mode Maximum Performance Mode

Clocks running

Clocks running



of SLP# triggers the transition logic to begin its execution. Note that the external logic is synchronized with SUSCLK.

3. From Sleep to Deep Sleep and back to Sleep (in-sync with SUSCLK) – The external logic asserts DPSLP# after T2. After T3, the external logic deasserts DPSLP#. The system enters Sleep state after T4. Because GHI# is tied low, the mobile processor will transition to MPM and the high frequency.

4. From Sleep to Stop Grant (in-sync with SUSCLK, BCLK) – The external logic asserts RI# (ring indicator) to the ICH4, which will take over from here for the wake portion of the sequence. The external logic deasserts RI# in the next SUSCLK cycle. The ICH4 deasserts SLP#, and after T5, the system enters Stop Grant state.

5. From Stop Grant to Normal (in-sync with BCLK) – The ICH4 deasserts STPCLK#, and the system enters Normal state.

Table 4 provides timing details for the timings noted in Figure 2.

Note: To avoid compromising signal integrity, the DPSLP# input to the CPU must not sink more than 4mA. In the schematic in Appendix A, “High Frequency Transition Sample Schematic”, the values of resistors R4 and R6 must be selected to properly translate the voltage of this signal, while meeting this sink requirement.

Table 4. Timing Details

T# Description Min Max Unit

T1 Input signals stable to SLP# assertion requirement 10 BCLKs

T2 SLP# to DPSLP# assertion 10 BCLKs

T3 DPSLP# hold time 1 BCLKs

T4

Deep Sleep PLL lock latency, time required to enter Sleep state after DPSLP# has been deasserted. External logic can assert RI# anytime after this.

0 30 us

T5

Input signal hold time from SLP# deassertion, time required to enter Stop Grant state after SLP has been deasserted

10 BCLKs

T6 STPCLK# hold time from SLP# deassertion 10 BCLKs



2.4 External Logic

System designers must select hardware to fulfill the requirements of the external logic, as stated above. The external logic must accommodate three inputs (SLP#, RESET, SUSCLK) and two outputs (DPSLP#, RI#). Designers may select a PLD, FPGA, or other logic device of their choice and use the state diagram in Figure 3, the simulation timing diagram in Figure 4, and logic diagram and equations shown in Figure 5.

Figure 3. External Logic State Diagram

Figure 4. External Logic Timing Diagram

State 1000

State 2001

State 3011

State 4111

State 5110

State 6100

State 7010

State 8101

CPUSLP

DPSLP, RI

CLKCLK

DPSLP, RI

DPSLP, RI

DPSLP, RI

CLK

DPSLP, RI

CPUSLP

CLK

DPSLP, RI



In addition, designers may utilize the following VHDL code to program their external logic device:

library ieee;use ieee.std_logic_1164.all;entity speed_transition is port(

clk, rst: in std_logic;cpuslp: in std_logic;

dslp: out std_logic;ri: out std_logic

);end speed_transition;

architecture speed of speed_transition is

signal state: std_logic_vector(2 downto 0);-- State assignment is such that the logic is reducedconstant state1: std_logic_vector(2 downto 0) := "000";constant state2: std_logic_vector(2 downto 0) := "001";constant state3: std_logic_vector(2 downto 0) := "011";constant state4: std_logic_vector(2 downto 0) := "111";constant state5: std_logic_vector(2 downto 0) := "110";constant state6: std_logic_vector(2 downto 0) := "100";constant state7: std_logic_vector(2 downto 0) := "010";constant state8: std_logic_vector(2 downto 0) := "101";

Figure 5. External Logic Diagram

RI = Qa_ + Qb + Qc

DPSLP = Qa + Qb_ + Qc_

Dc = Qa_ * Qc + Qa_ * Qb_ * CPUSLP_

Db = Qa_ * Qc + Qb * Qc

1D1CLRN1CLK2PRN2D2CLRN2CLK

1PRN

2QN2Q

1QN1Q

7474

D FLIP-FLOPS

1D1CLRN1CLK2PRN2D2CLRN2CLK

1PRN

2QN2Q

1QN1Q

7474

D FLIP-FLOPS

VCC

CLK

CPUSLP

RESET

GND

7404

74087408

7408

7408

7408

7408

7408

7408

7408

7432

7432

7432

74327432

7432

7432

7432

RI

DPSLP

Qb_

QaQa_

Qb

Qb_QaQa

Qa_Qb

Da

Qc_Qb_Db

QbQa_

QcQcQc_

Qc_Qc

Dc

Da = Qa * Qb + Qb * Qc + Qa * Qc_ * CPUSLP_

INPUT

INPUT

INPUT

OUTPUT

OUTPUT



begin-- If reset is low the state machine will be stable and in state1process (clk, rst)

beginif rst=’0’ then

state <= state1;elsif (clk’event and clk=’1’) then

case state iswhen state1 =>

if cpuslp = ’0’ thenstate <= state2;

end if;dslp <= ’1’;ri <= ’1’;

when state2 =>state <= state3;

when state3 =>state <= state4;dslp <= ’0’;

when state4 =>state <= state5;dslp <= ’1’;

when state5 =>state <= state6;ri <= ’0’;

when state6 =>if cpuslp = ’1’ then

state <= state1;else

state <= state6;end if;

when others =>state <= state1;

end case;end if;

end process;

end speed;



2.5 BIOS Enabling

2.5.1 Initiating the Transition Sequence in BIOS

BIOS designers must follow the design guidelines referenced in the Intel® Pentium® 4 Processor in 478-Pin Package and 845E Chipset Platform for DDR Design Guide. However, additional BIOS modifications are required to initiate the transition sequence. Figure 6 depicts a flow chart of the required BIOS modifications.

The “Intel® SpeedStep® Support?” step above controls whether or not the transition sequence actually takes place. If a desktop processor is present in the socket (as in the case of a scalable platform), the BIOS first checks the processor for enhanced Intel SpeedStep technology support. If enabled (as in a mobile processor), the transition sequence continues; if disabled (as in a desktop processor), the transition sequence does not execute.

Figure 6. Required BIOS Modifications

A9872-02

BIOSSequence

Go toS1 Sleep

EXIT

Clear Ring Indicator(Wake-Up Event)Status Register

Intel®SpeedStep®

Support ?

Yes

No

Setup S1 State

Enable Ring Indicator(Wake-Up Event)

Enable SLP in S1 Stateof Power Management

Registers

Set ACPI Base Addressand

Enable ACPI I/O Region



The BIOS must run the equivalent of the following psuedo-code during POST, immediately following the initialization of the ICH4:

// Initiate an Intel(R) SpeedStep(R) technology sequence.// This sequence is used to trigger the external logic on board.// The external logic is triggered by CPUSLP# assertion.// The external logic asserts the Wake event (Ring Indicator) to wake system.

IF ( SpeedStep-Supported ){

Ring Indicator Status, GPE0_STS[8] = ClearRing Indicator Event, GPE0_EN[8] = EnableMask InterruptsCPUSLP# signal assert in S1 Sleep, GEN_PMCON_1 [5] = EnableSleep Type, PM1_CNT [12:10] = Desktop S1 State (001h)Sleep, PM1_CNT [13] = Enable

}

To obtain details on the register utilized to check whether Intel SpeedStep technology is supported, please contact your Intel field representative.

Note: The system must not contain an external bus master that could possibly interrupt the above sequence. If so, the BIOS must disable that external bus master.

2.5.2 Microcode Updates in BIOS

The Intel® Pentium® 4 processor and Intel® Pentium® 4 Processor-M contain different microcode. If the BIOS contains code to update the processor microcode, the BIOS must be modified to first detect which processor is present in the socket, and then load the appropriate microcode.



3.0 Voltage Regulator Design Guidelines

Because scalable platforms do not require advanced power management support, the primary differences between mobile and desktop requirements are the loadline specification and VID table translation. As such, for a scalable platform, Intel recommends one of the two following voltage regulator solutions:

• Design the board to accommodate two voltage regulator modules (VRMs), or

• Design the board with a scalable voltage regulator-down (VRD) on the board.

3.1 Scalable Platform Voltage Regulator Modules

For this solution, one connector should be designed onto the board to support either a desktop or mobile VRM. Refer to the VRM 9.0 DC-DC Converter Design Guidelines for specifications and design guidelines for the VRM connector. Intel has enabled third party vendors to manufacture the two VRMs. The vendors are listed in Table 5.

Caution: The proper VRM must be plugged into the connector before powering on the board. If the processor and VRM do not match, the VRM will deliver an incorrect voltage level, which may cause damage to the board and components.

3.2 Scalable Platform Voltage Regulator Down

A reference design for a VRD for a scalable platform is included in Appendix B, “Scalable Platform VRD Schematic”.

Table 5. VRM Vendors

Mobile VRM Vendor Desktop VRM Vendor

Powercube, A Natel Company

9340 Owensmouth Ave

Chatsworth, California 91311

USA

Contact: Mr. Shree Ramadas

Tel: (818) 734-6500

Toll-free: (800) 866-3590

FAX: (818) 734-6540

Toll-free FAX: (800) 866-3589

Email: [email protected]

www.powercube.com

Powercube Part Number: VRMP-91-12-40

Sales representatives are located in Japan, China, India, Taiwan, Korea, UK, France, Germany, Norway, Sweden, Finland, Denmark, Austria, Italy, and Israel.

Celestica

4607 S.E. International Way

Milwaukie, Oregon 97222

USA

Tel: 971-206-2800

FAX: 503-786-5011

Email: [email protected]

www.celestica.com

Celestica Part Number: 073-20816-01

Sales representatives are located in North America, Japan, Taiwan, and Malaysia.

NOTE: These vendors are listed by Intel Corporation as a convenience to Intel’s general customer base. Intel does not make any representations or warranties whatsoever regarding quality, reliability, functionality, or compatibility of these devices. This list and/or these devices may be subject to change without notice.



Appendix A High Frequency Transition Sample Schematic

This appendix includes a schematic diagram for one example implementation of the Intel® Pentium® 4 Processor-M transition requirements.

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

To CPU pin AD2

5.

It has a pull-up resis

tor

to +3.3V_STB

Y

Note:

THIS DRAWING CONTA

INS

INFORMATION WHICH

HAS

NOT BEEN VALIDATED FOR

MANUFACTURING AS AN

END

USER PRODUCT. INTEL IS

NOT RESPONSIBLE FOR

THE

MISUSE OF TH

ISINFORMATION.

PLD

Spar

e Pa

rts

FOR

LM393

PLD

DECO

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(3.3

V Si

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(3.3

V Si

gnal

/ 32KHz)(5V

Signal)

(3.3

V Si

gnal)

(1.5

V Si

gnal)

(3.3

V Si

gnal)

This signal has to be low to make the tr

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Note:

Rise

Tim

e ~ 20 ns

Max

Curr

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from

ICH4

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DS

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Vcc GND

R1

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LM39

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U2A

LM39

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R2 3K

C40.

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SU

SC

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DP

SLP

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V

H_S

LP

ICH

4_R

I_P

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I



Appendix B Scalable Platform VRD Schematic

This appendix includes a reference schematic for a voltage regulator-down (VRD), compatible with both the Intel® Pentium® 4 processor and the Intel® Pentium® 4 Processor-M.

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

290K

Hz

per

Pha

se

Optional type-3 compensation

components, not needed for most cases

Load-line switching circuit: When

Desktop_operation control signal is High,

the VR will operate to the load line.

The equivalent resistor of R_mobile in

parallel with R_desktop determines Desktop

operation mode load line.

VR enable circuit is for

reference only. Please refer

to reference design

schematics.

2). Use Dpak FETs IRLR3714 for upper

switch Q11,Q12,Q21,Q22,Q31,Q32

1). Use Dual-FETs for each switch for

better efficiency and thermal

performance in a no-fan enviorement.

Mosfet selection:

VIN

is th

e 12

V in

put f

rom

AT

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ect t

hem

to V

inin

the

layo

ut.

3). Use Dpak FETs IRFR3711 for lower

switch Q13,Q14,Q23,Q24,Q33,Q34

12V

is th

e fil

tere

d in

put v

olta

ge f

or

pow

erst

age.

Current sensing and Droop setting:

1). Select current sensing resistor R11,

R12, R13 based on desktop 70A ouput

current, 5.2mohm Rds,on @ 25C and 65C

temperature rise.

2). In mobile operation mode, the

selection of droop resistor R_mobile is

based on 80mV voltage drop at 40A Maximum

load.

3). In desktop operation mode, the

selection of parallel droop resistor

R_desktop is based on 105mV voltage drop

at 70A output.

Application Notes:

The paramaters are for initial test

purposes only. Refining the values of

compensation network components and

droop resistors are needed in order to

ensure the actual board meets the spec.

No-load voltage offset:

1). No-load offset is not needed for Mobile

operation mode.

2). No-load offset for desktop operation

mode is -25mV. This offset is done by

connection FB pin of HIP6301V to 5V through

a 324kohm resistor.

VID

vo

ltage

fo

r In

tel (

R)

Pen

tium

(R)

4 P

roce

sso

r an

d In

tel

Pen

tium

4 P

roce

sso

r-M

:

1). E

ven

tho

ugh

the

VID

vo

ltage

s fo

r bo

th D

eskt

op

and

Mo

bile

ope

ratio

n m

ode

can

be

the

sam

e, th

e V

ID c

ode

s an

d th

e lo

adlin

es a

re d

iffer

ent.

2). T

o e

nsur

e th

at th

e sa

me

circ

uit c

an b

e us

ed f

or

both

pro

cess

ors

, a p

roce

sso

r id

entif

icat

ion

circ

uit

and

a V

ID c

ode

co

nver

tion

logi

c is

nee

ded.

Thi

s re

gula

tor

onl

y us

es th

ede

skto

p V

ID m

ap to

set

out

put v

olta

ge.

The

refo

re,

whe

n us

ing

the

mo

bile

pro

cess

or,

glu

e lo

gic

will

be

need

ed to

map

the

mo

bile

VID

s to

the

desk

top

VID

s.

THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED

FOR MANUFACTURING AS AN END USER PRODUCT. INTEL IS NOT

RESPONSIBLE FOR THE MISUSE OF THIS INFORMATION.

APPENDIX B

Inte

l (R

) Pen

tium

(R) 4

Pro

cess

or a

nd In

tel P

entiu

m 4

Pro

cess

or-M

Sca

lable

VR

D1.

5

PW

M C

ontr

ol a

nd P

ower

Sta

ge

B

12

Mon

day,

Apr

il 21

, 200

3

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

VID

2

VR

_Ena

ble

VID

3

VID

0

V_C

OR

E+

2

VID

4

VID

1

Des

ktop

_ope

ratio

n

2

V_C

OR

E

+5V

VIN

+12

V

+12

V

+12

V

+5V

+5V

+5V

Q12

1

34

U1

HIP

6601

1 58

7 6 32

4

UG

AT

E

LGA

TE

PH

AS

E

PV

CC

VC

C

PW

MB

OO

T

GN

D

L230

0nH

12

R11

1.62

K1

2

C23

4.7n

F

1 2

L130

0nH

12

C21

4.7n

F

1 2

R25

2.2o

hm

C12

0.33

uF

12

R21

2.2o

hm

U2

HIP

6601

1 58

7 6 32

4

UG

AT

E

LGA

TE

PH

AS

E

PV

CC

VC

C

PW

MB

OO

T

GN

D

TP

-1 1

C3

680p

F

12

Q11

1

34

R0

100K

R_m

obile

3.16

k1

2

Q34

1

34

C15

4.7u

F

1 2

C1

1.2n

F

12

C7 2.

2uF

1 2

C16

0.33

uF

12

C6 2.

2uF

1 2

C2

56pF

C13

4.7u

F

1 2

Q2 PN

P B

CE

C14

0.33

uF

12

C8 2.

2uF

1 2

R_d

eskt

op_o

ffset

324k

12

R_d

eskt

op6.

19k

12

Q24

1

34

R10

10k

C25

4.7n

F

1 2

U5 H

IP63

01V

20 1 2 3 4 5

15 14 11 1816 13 12 177610 9

19 8

VC

C

VID

4V

ID3

VID

2V

ID1

VID

0

PW

M1

PW

M2

PW

M3

PW

M4

ISE

N1

ISE

N2

ISE

N3

ISE

N4

FB

CO

MP

VS

EN

GN

D

PG

OO

D

FS

/DIS

Q32

1

34

Q14

1

34

TP

-3 1

R13

1.62

K1

2

Q33

1

34

Q7

BS

S13

8

3

1

2

Q21

1

34

Q13

1

34

Q7 BS

S13

8

3

1

2

Q22

1

34

Rdr

iver

-12.

2ohm

R3

750o

hm1

2

TP

-2

1

Q3

2N37

72

R23

2.2o

hm

R1

4.75

K1

2

C11

4.7u

F

1 2

C0

1uF

L330

0nH

12

U3

HIP

6601

1 58

7 6 32

4

UG

AT

E

LGA

TE

PH

AS

E

PV

CC

VC

C

PW

MB

OO

T

GN

D

Q23

1

34

R12

1.65

K1

2

Q31

1

34

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

40 each 10uF X7R 1206 caps

9 each 560uF OSCON caps

1). In Mobile operation mode, it may be necessary to reduce the number of output caps

to reduce cost. However, it is important to have the space for 9 output bulk caps so

that the same board can be used for both Mobile and Desktop applications.

Notes for output capacitor selection:

2). The number of ceramic caps can also be reduced based on actual test results. It

is prefered to use small 805 package 10uF caps if available.

J3

OFF* = Desktop Operation

ON = Mobile Operation

The Desktop_Operation

signal can also be used to

control the VID translation

circuitry.

Desktop/Mobile Selection jumper

Inte

l (R

) Pen

tium

(R) 4

Pro

cess

or a

nd In

tel P

entiu

m 4

Pro

cess

or-M

Sca

lable

VR

D1.

5

OU

TP

UT

CA

PA

CIT

OR

S a

nd IN

PU

T F

ILTE

R

B

22

Mon

day,

Apr

il 21

, 200

3

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

V_C

OR

E+

1

V_C

OR

E-

Des

ktop

_ope

ratio

n1

V_C

OR

E

V_C

OR

E

V_C

OR

E

V_C

OR

E

+12

V

VIN

+5V

C11

010

uF

1 2

C12

010

uF

1 2

C13

210

uF

1 2

+C

164

560u

F

1 2

C13

110

uF

1 2

+C

161

560u

F

1 2

J2 LUG

1

C10

210

uF

1 2

C12

110

uF

1 2

+C

167

560u

F

1 2

+C

3627

0uF

1 2

C13

010

uF

1 2

C10

510

uF

1 2

C11

710

uF

1 2

+C

168

560u

F1 2

C12

810

uF

1 2

C11

510

uF

1 2

R4

5k

J3

Hea

der1

X2

1 2

C10

310

uF

1 2

C10

910

uF

1 2

C12

910

uF

1 2

C11

610

uF

1 2

+C

163

560u

F

1 2

C13

310

uF

1 2

C14

010

uF

1 2

C10

410

uF1 2

C11

310

uF

1 2

L51.

2uH

12

C11

110

uF

1 2

C13

610

uF

1 2

+C

3427

0uF

1 2

C13

510

uF

1 2

+C

162

560u

F

1 2

C12

310

uF

1 2

C13

410

uF

1 2

C10

110

uF

1 2

+C

165

560u

F

1 2

+C

166

560u

F

1 2

J1 LUG

1

C13

710

uF

1 2

C12

610

uF1 2

C11

210

uF

1 2

C12

410

uF

1 2C

107

10uF

1 2

C12

510

uF

1 2

C13

910

uF

1 2

C11

410

uF

1 2

C10

810

uF

1 2

C13

810

uF

1 2

C10

610

uF

1 2

C11

910

uF

1 2

+C

169

560u

F

1 2

C12

210

uF

1 2

+C

3527

0uF

1 2

C12

710

uF

1 2

C11

810

uF

1 2



This page intentionally left blank.



Appendix C Reference Design Schematics

This appendix includes a complete set of board schematics for a scalable Intel® 845E chipset platform, which supports both the Intel® Pentium® 4 processor and Intel® Pentium® 4 Processor-M.

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Schematic Page

#

COVER SHEET

1

Revision X2

Last Change : 2002-09-26

2 3 4 5

BLOCK-POWER

BLOCK DIAGRAM

6 7 8

CPU-P4 BUS

CPU-P4 POWER

910

MCH-SYSBUS & CLOCK

MCH-AGP & DDR

MCH-POWER

11

12

13

14

DDR-DIMM 0

ICH4-SYSBUS & PCI

SIO0-LPC47M107

15

16

19

17

18

LAN-10/100/1000 BUS

20

21

23

22

24

25

26

27

28

AC97-AD1885

VGA-COUGAR-01

CLK-ICS950201

CONN-PCI

CONN-COM1/COM2/LPT

USB0-USB1-LAN0

DDR-POWER

POWER

Prefix

Netobject

H_

P4 HOSTBUS SIGNAL

CLOCK SIGNAL

CK_

ICH4-LPC & IDE & USB

ICH4-POWER

GLUE LOGIC

SIO1-LPC47N227

CONN-COM3/COM4/KBC

VGA-COUGAR-02

VGA-COUGAR-03

CONN-01 IDE-FLOPPY

29

30

31

SYSTEM CONTROL

M_

MEMORY BUS SIGNAL

V_

POWER

G_

AGP BUS SIGNAL

CPU-ITP

DDR-DIMM 1

32

USB2-USB5

33

LAN-10/100/1000 CONN

A_

CRITICAL ANALOG TRACES

MECH-ROUTE

NOTES

34

35

F_

FLOPPY DISK SIGNAL

L_

LPC BUS SIGNAL

P_

PCI BUS SIGNAL

AC_

AC97 SIGNAL

KB_

KEYBOARD SIGNAL

LP_

LPT1284 SIGNAL

MS_

MOUSE SIGNAL

ZV_

ZV VIDEO PORT SIGNAL

AUD_

ANALOG AUDIO SIGNAL

GND_

GND SIGNAL DERIVED

I2C_

I2C BUS SIGNAL

IDE_

IDE SIGNAL

INT_

INTERRUPT SIGNAL

LANn_

LAN CONTROLLER n SIGNAL

SPn_

SERIAL PORT n SIGNAL

USB_

USB PORT SIGNAL

APIC_

APIC SIGNAL

General Note:

All Parts marked 'XXX1' will not be assembled in V1.

All Parts marked 'XXX2' will not be assembled in V2.

EEn_

SERIAL EEPROM LANn

EN_

ENABLE FOR POWER SOURCES

FWH_

FIRMWARE HUB SIGNAL

GND

GND POWER

MIDI_

MIDI SIGNAL

Changes from X1 to X2

1 2All BAT54A (0-0031-1261) changed to BAT54 (0-0031-1104) due to wrong polarity

R712 changed from 10k to 15k to adjust voltage

3PU R756 and R757 added @ U38.15 (PG_VDDR) and U38.16 (PG_V1V5)

4Net on pins U3.54 and U3.55 separated (BSEL[0..1]) due to naming error

PU R758 added at CN34.7 (SYS_RESET#)

5 6 7 8 910

PU R759 added at U39.4 (VIDPWRGD)

C717 changed from 4u7 to 1u

R607 not populated

11

12

13

R571 and R572 not populated (FWH Test Pins)

R585 and R586 not populated (for LVDS 18 Bit)

14

15

16

R760 and C741 added to U7.50 to generate a V_3V3SB input delay for resume reset

R501 and R494 not populated due to PCI config of LAN 82540

U36 FWH symbol changed due to wrong pinout (Pin 23, 24 and 25)

R496 changed to 4k7 and set to GND (PD M66EN)

R525 and R499 is now populated

R530 not populated due to wrong V_2V5LAN voltage

17

18

19

U20.G4 is now 51R Pulldown to GND

U20.H4 is now 33R Pullup to V_3V3LAN

20

21

22

23

AC97 Fixup (AC_SDIN0 -> Changed to AC_SDIN2 on ICH4)

Swap ICH4 Pin N20 and P21 (H_HISTB+ / H_HISTB-) due to wrong info in yellow cover

LAN 82540 Fixup (R519 populated with 0R, R517 changed to 2K49 and R513 changed to 330R)

R615 changed to 4K32 due to Cougar Bug

24

HW Rev changed to 2 at Glue Logic

25

26

R373 is now populated with 10M

CN12.4 must be isolated cause of shortcut of AUD_MIC_BIAS to GND

27

PU R761-R765 added to VID[0:4]

PU R766 added to U23.15, PD R767 added to U23.14 (Panellink strapping options)

28

29

30

HD-LED-power connected to V_5V0 instead of V_5V0SB

PD R768 added to PS_ON

PU R769 added to U3.28 (PGOOD408#)

31

32

33

PD R770, R771, R772 added to power enables (default off, if CPLD not configured)

PD R773-R776 added to serial port shut down pins

Splitted SMI# and PME# signals of SIO0 and SIO1 on ICH4-GPIOs

34

Removed R383, R384, R385

35

Added D25 to avoid crossvoltages from VGA Monitor

36

Added D26 to avoid crossvoltages LPT Port

37

Alternative population of L7 to L12 with resistors (0R)

PME# Signal of Cougar (PinB7) is set to V_3V3 via 0R

38

39

U29 (LP3965EMP) can be replaced by an 0R_1206 to power 3V3 on Cougar

40

Possibility to PullDown Pin D8(MD24) on Cougar to enable SDRAM

41

CN41 (JUMPER 3x1) added to connect to MPCI Pins (TIP and RING)

42

V_5V0 input at V_DDR supply is now controlled by XILINX CPLD (Pin 25)

43

Delay of PWRGOOD# (LAN 82540EM Pin A9) to enable correct EEPROM detection

THIS SCHEMATIC IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER,

INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR

PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF PROPOSAL, SPECIFICATION

OR SAMPLE.

No license, express or implied, by estoppel or otherwise, to any

intellectual property rights is granted herein. Intel disclaims all

liability, including liability for infringement of any proprietary rights,

relating to use of information in this specification. Intel does not

warrant or represent that such use will not infringe such rights.

THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR

MANUFACTURING AS AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE

MISUSE OF THIS INFORMATION.

* Other names and brands may be claimed as the property of others.

Intel (R) 845E Interactive

Client Reference Design

APPENDIX C

B44

4B-W

2.00

CO

VE

R S

HE

ETInte

l (R

) 84

5E In

tera

ctiv

e C

lient

Ref

eren

ce D

esig

n

C1

35M

onda

y, A

pril

21, 2

003

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

eS

heet

of

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

BG

A38

516

MB

int.

mem

.

Glu

e Lo

gic

pla

nar

5V P

CI-S

lot

Inte

l (R

)82

801D

B IC

H4

I/O p

anel

max

. 2

GB

pla

nar

Pg

. 8

Hu

b In

terf

ace

66M

Hz

x4,

8b (

266

MB

/s)

SE

RIA

L3

SM

B

Inte

l(R

) P

enti

um

(R) 4

Pro

cess

or

or

Inte

l(R)

Pen

tiu

m(R

) 4

Pro

cess

or-M

I/O p

anel

Pg

. 26

, 27

, 28

FW

H

Pg

. 12

PA

RA

LL

EL

Inte

l (R

) 82

845E

LPC

47N

227

Inte

l (R

) 82

851

LAN

Con

trol

ler

(op

tion

ali8

2551

/i825

59)

I/O p

anel

PC

I, 33

MH

z, 3

2b (

132

MB

/s)

SE

RIA

L2

FIR

LPC

47M

107

pla

nar

Inte

l (R

) 82

562E

T/E

M

Pg

. 24

, 25

I/O p

anel

8 M

bit

Inte

l (R

)82

802A

CF

irmw

are

Hub

PLC

C32

DDR-DIMM

LV

DS

ATA66/100

pla

nar

Pg

. 13

CD

-RO

M

Pg

. 19

1280

x102

4 @

18B

it

RJ4

5

FC

PG

A47

8

PH

OT

O D

IOD

E

pla

nar

LA

N

Pg

. 25

US

B2.

0

BG

A59

3

Pg

. 31

AC

'97

AD

1885

Pg

. 27

FA

N

AG

P 1

.5V

, 66

MH

z x4

, 32

b (

1.1

GB

/s)

PH

Y

Pg

. 20

HE

AD

PH

ON

E

pla

nar

Pg

. 33

LIN

E-O

UT

DV

I/VG

A

I/O p

anel

IDE

1

SM

I* S

M73

1

CP

U V

RM

MO

US

E

LM87

Pg

. 33

Pg

. 30IT

P

Pg

. 31

, 32

FD

D

SY

SM

ON

I/O p

anel

Pg

. 9,

10,

11

IDE

0

DV

I-I

SE

RIA

L0

US

B

SIO

Pg

. 23

ICS

9502

01C

K 4

08B

I/O p

anel

FS

B 1

33M

Hz

x4,

64b

(4.

3 G

B/s

)

Pg

. 6,

7

Blo

ck D

iagr

am

pla

nar

Pg

. 29

Pg

. 34

3 *

pla

nar

Pg

. 15

, 16

, 17

I/O p

anel

LPC

3.3

V,

33M

Hz

DD

R S

DR

AM

2.5

V,

266M

Hz,

64b

(2.

1 G

B/s

)

Pg

. 35

SIO

BG

A42

1

MIC

RO

- P

ostc

ode

dec

odin

g-

Sp

eed

step

log

ic-

Pow

eru

p s

equ

enci

ng

SE

RIA

L1

Clo

ckin

g

min

iPC

I-Slo

t

LIN

E-I

N

pla

nar

I/O p

anel

Pg

. 18

AC

'97

I/O p

anel

DD

R V

R

TV-O

UT

RJ4

5

K/B

Xili

nx *

Coo

lrunn

er

Pg

. 29

2 *

I/O p

anel

2 *

I/O p

anel

, po

wer

ed2

* p

lan

ar

Pg

. 14

Pg

. 27

Pg

. 27

Pg

. 31

Pg

. 30

Pg

. 30

Pg

. 21

Pg

. 21

Pg

. 21

Pg

. 22

Pg

. 22

Pg

. 22

Pg

. 22

Pg

. 20

Pla

tfor

m L

AN

Con

nect

Com

pone

nt

MC

H

B44

4B-W

2.00

BLO

CK

-DIA

GR

AM

Inte

l (R

) 84

5E In

tera

ctiv

e C

lient

Ref

eren

ce D

esig

n

C2

35M

onda

y, A

pril

21, 2

003

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

eS

heet

of

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

VC

C_C

LK

VC

C_1

V8

VC

C_1

V5S

US

3V3

VC

C_3

V3S

US

SLP

_S3#

CL

K

B

VC

C_3

V3S

MIC

5284

B

ICH

4

VC

C_1

V2V

ID

SLP

_S4#

A

LTC

1117

VC

C_1

V5S

VC

CP

A

CP

U

ISL6

225

ISL6

225

ISL6

225

AT

X P

OW

ER

VC

C_T

ER

M

VR

M M

OD

UL

E

VC

C_5

V0S

US

VT

T

12V

VC

C_R

EF

SLP

_S3#

VC

C_5

V0S

VC

C_1

V8S

VC

C_1

V5

LTC

1117

ATX

12V

VC

C_D

DR

V_3

V3A

GP

MC

H

DIM

M

12V

SM

731*

LTC

1117

5V

VC

C_D

DR

5VS

B

B44

4B-W

2.00

BLO

CK

-PO

WE

R

Inte

l (R

) 84

5E In

tera

ctiv

e C

lient

Ref

eren

ce D

esig

n

C3

35M

onda

y, A

pril

21, 2

003

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

eS

heet

of

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

BIOS IN

Firmware-Hub

PCB

FWH

B44

4B-W

2.00

ME

CH

-RO

UT

EInte

l (R

) 84

5E In

tera

ctiv

e C

lient

Ref

eren

ce D

esig

n

C4

35M

onda

y, A

pril

21, 2

003

Titl

e

Siz

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ocum

ent N

umbe

rR

ev

Dat

eS

heet

of

V_C

OR

E

V_C

OR

EV

_CO

RE

V_C

OR

EV

_CO

RE

V_C

OR

E

V_C

OR

EV

_CO

RE

V_C

OR

EV

_CO

RE

V_C

OR

E

V_C

OR

EV

_CO

RE

V_C

OR

EV

_CO

RE

V_C

OR

E

V_C

OR

EV

_CO

RE

V_C

OR

E

GN

DG

ND

GN

DG

ND

M12

HS

_MC

H_I

NT

ER

FA

CE

XXX1

XXX2

M24

SM

02/R

D

TP

2

M17

HS

_MC

H_P

OR

ON

XXX1

XXX2

M25

SM

02/R

D

M1

P4_

RE

TE

NT

1

2

3

4

MR

KF

1M

AR

KF

PIT

M16

HS

_MC

H_C

LIP

XXX1

XXX2

DK

5D

K20

4060

BR

D1

B44

4B

DK

16D

K20

4060

TP

3

DK

9D

K20

4060

M E C H

M32

JMP

_2m

m54

DK

17D

K20

4060

M26

SM

02/R

D

TP

4

B2

BO

HR

4.0

Mx

DK

15D

K20

4060

M15

HS

_MC

H_L

EV

ER

XXX1

XXX2

B7

BO

HR

4.0

Mx

M E C H

M31

BA

T_C

R20

32

B3

BO

HR

4.0

Mx

DK

14D

K20

4060

DK

1D

K20

4060

M10

8280

2AC

M30

MA

CA

DR

ES

SXX

X1XX

X2

DK

2D

K20

4060

DK

12D

K20

4060

DK

18D

K20

4060

B9

BO

HR

4.0

Mx

DK

6D

K20

4060

M11

HS

_MC

H_P

IN_F

INXX

X1XX

X2

B5

BO

HR

4.0

Mx

M29

MA

CA

DR

ES

S

MA

RK

E2

MA

RK

ET

OP

DK

13D

K20

4060

M2

BG

A59

3A/C

OO

L

12345678

B4

BO

HR

4.0

Mx

DK

10D

K20

4060

DK

3D

K20

4060

MA

RK

E3

MA

RK

ET

OP

TP

1

DK

11D

K20

4060

B1

BO

HR

4.0

Mx

B8

BO

HR

4.0

Mx

DK

7D

K20

4060

M7

B44

4100

0.01

MA

RK

E1

MA

RK

ET

OP

M23

SM

02/R

D

DK

8D

K20

4060

DK

4D

K20

4060

V_C

OR

E6.

.8,1

1,17

,33,

35

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

DEV

IDSEL

DEVICE

IRQ

REQ/GNT

V_-12V0

V_-5V0

V_5V0

V_5V0SB

V_12V0

V_12V0VRM

V_12V0VRMF

INPUT

VOLTAGES

V_FAN1

V_FAN1S

V_FAN1SF

V_FAN2

V_FAN2S

V_FAN2SF

V_12VAUD

V_AUDOUT

V_5VAUD

V_12USB2

V_12USB2F

V_12USB2S

V_12USB3

V_12USB3F

V_12USB3S

DERIVED VOLTAGES -->

V_1V5SB

V_3V3SB

V_3V3AGP

V_1V5

V_DDR

V_DDRVTT

V_DDRREF

V_CORE

V_USB0

V_USB1

V_USB2

V_USB3

V_USB4

V_USB5

V_USB0X

V_USB1X

V_USB2X

V_USB3X

V_USB4X

V_USB5X

V_1V5A1

V_PIDE

V_SIDE

V_5V0CF

V_VCC1

V_AVCC1

V_PVCC1

V_VREF_SII

V_5DVI

V_5DVIF

V_BLI

V_DBL

V_DL_CL

V_DL_CLF

V_IOLAN

V_1V5LAN

V_2V5LAN

V_3V3LAN

V_3V3LAN0

V_AMP

V_AMPIN

V_AMPINX

V_AMPOUT

V_KB

V_KBF

V_FIR

V_IR

V_GAME

V_GAMEF

V_ICHPLL

V_2V5_LVD

V_2V5_LVD1

V_LVDD1

V_LVDD2

V_2V0_2V5

V_VDD1

V_2V5_VDD

V_VDD2

V_VDD3

V_AVDD

V_FPVDD

V_TVDD

V_VPVDD

V_HVDD

V_RTCBIAS

V_5V0REF

V_1V2VID

V_RTC

V_3V3SB

V_1V8

V_3V3

V_CLK

V_BAT

V_VCCA

V_VCCIOPLL

V_1V5A2

V_PLLVDD

V_2V5_LVD2

V_CVDD

00

01

02

03

04

05

06

07

08

09

10

11

12

13

14

15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26

AD27

AD28

AD29

AD30

AD31

SM731 AGP

LAN10/100/1000T

INTERNAL LAN

MINI PCI SLOT

STD PCI SLOT

RISER SLOT1

RISER SLOT2

RISER SLOT3

A G N/A

E-F

A-B-C-D

B-C-D-A

C-D-A-B

D-A-B-C

AGP

4

N/A

3

0

0

1

2

PCI/AGP DEVICES

OTHERS

V_DDR, V_DDRREF

S3 (SUS. TO RAM)

POWER PLANE

POWER STATES

S0 (FULL ON)

S5 (SOFT OFF)

ON IN STATE

V_*SB, V_KB, V_*LAN, V_USB*

I2C DEVICES

CLOCK GENERATOR

SO-DIMM0

SO-DIMM1

ICH4 SLAVE

LAN CONTROLLER

LM87 HW MONITOR

DEVICE

ADDRESS

1101001x

1010000x

1010001x

1000100x

N/A

0101110x

BUS

SM BUS

SM BUS

SM BUS

SM LINK

SM LINK

SM BUS

SIGNAL NAME

ICH4 GPIOs

SUPER I/O 0

SUPER I/O 1

SUPER I/O 0

SUPER I/O 1

CPLD

LAN0 KINNERETH

MINI PCI

CPLD

PRIMARY IDE

SECONDARY IDE

POWERED USB

POWERED USB

FIRMWARE HUB

FIRMWARE HUB

PCI RISER

PCI RISER

AUDIO AMPLIFIER

PCI RISER

PCI SLOT

PCI SLOT

SIO0_SMI#

SIO1_SMI#

SIO0_PME#

SIO1_PME#

XC_GPIO2

LAN0_ENA

MPCI_ACT#

XC_GPIO1

IDE_PPDIAG#

IDE_SPDIAG#

USB_PWR2ENA#

USB_PWR3ENA#

FWH_WP#

FWH_TBL#

RISER_ID1

RISER_ID2

AMP_SHDN

NOGO

P_PRSNT1#

P_PRSNT2#

GPIO

DEVICE

GPI6

GPI7

GPI8

GPI12

GPI13

GPIO25

GPIO27

GPIO28

GPIO32

GPIO33

GPIO34

GPIO35

GPIO36

GPIO37

GPIO38

GPIO39

GPIO40

GPIO41

GPIO42

GPIO43

B44

4B-W

2.00

NO

TE

S

Inte

l (R

) 84

5E In

tera

ctiv

e C

lient

Ref

eren

ce D

esig

n

C5

35M

onda

y, A

pril

21, 2

003

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

eS

heet

of

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

B44

4B-W

2.00

CP

U B

US

Inte

l (R

) 84

5E In

tera

ctiv

e C

lient

Ref

eren

ce D

esig

n

C6

35M

onda

y, A

pril

21, 2

003

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

eS

heet

of

H_I

GN

NE

X#

H_A

20M

X#

H_B

NR

#H

_BP

RI#

H_H

IT#

H_I

NT

RX

H_D

RD

Y#

H_D

BS

Y#

H_H

ITM

#

H_A

DS

#

PR

OC

HO

T#

H_S

MIX

#

H_L

OC

K#

H_N

MIX

H_T

RD

Y#

H_D

EF

ER

#

H_R

S#[

0..2

]

H_C

PU

RS

T#

H_I

NIT

#

H_D

[0..6

3]

H_D

0

H_D

ST

BN

#[0.

.3]

H_D

BI#

0

H_D

ST

BN

#0

H_D

BI#

[0..3

]

H_R

S#1

H_R

S#2

H_R

S#0

PW

RG

OO

D

CP

US

LPY

#S

TP

CLK

Y#

H_D

1H

_D2

H_D

3H

_D4

H_D

5H

_D6

H_D

7H

_D8

H_D

9H

_D10

H_D

11H

_D12

H_D

13H

_D14

H_D

15H

_D16

H_D

17H

_D18

H_D

19H

_D20

H_D

21H

_D22

H_D

23H

_D24

H_D

25H

_D26

H_D

27H

_D28

H_D

29H

_D30

H_D

31H

_D32

H_D

33H

_D34

H_D

35H

_D36

H_D

37H

_D38

H_D

39H

_D40

H_D

41H

_D42

H_D

43H

_D44

H_D

45H

_D46

H_D

47H

_D48

H_D

49H

_D50

H_D

51H

_D52

H_D

53H

_D54

H_D

55H

_D56

H_D

57H

_D58

H_D

59H

_D60

H_D

61H

_D62

H_D

63

H_D

ST

BP

#0

H_D

ST

BP

#[0.

.3]

H_B

R0#

H_D

BI#

1H

_DB

I#2

H_D

BI#

3

H_D

ST

BN

#1H

_DS

TB

N#2

H_D

ST

BN

#3

H_D

ST

BP

#1H

_DS

TB

P#2

H_D

ST

BP

#3

H_F

ER

R#

CK

_CP

U+

CK

_CP

U-

IER

R#

SK

TO

CC

#

THERMDC

THERMDA

SP

AR

EP

IN

SP

AR

EP

IN

SP

AR

EP

IN

SP

AR

EP

INS

PA

RE

PIN

SP

AR

EP

INS

PA

RE

PIN

SP

AR

EP

IN

SP

AR

EP

INS

PA

RE

PIN

SP

AR

EP

IN

H_A

#28

H_A

#10

H_A

#4

H_A

#18

H_A

#11

H_A

#29

H_A

#22

H_A

#9

H_A

#3

H_R

EQ

#2

H_A

#17

H_A

#27

H_A

DS

TB

#[0.

.1]

H_A

#[3.

.31]

H_A

#20

H_A

#7

H_A

#21

H_A

#31

H_A

#15

H_A

#8

H_A

#26

H_A

#16

H_R

EQ

#[0.

.4]

H_A

DS

TB

#1

H_A

#6

H_A

#30

H_A

#14

H_R

EQ

#1

H_A

#25

H_R

EQ

#0

H_A

#19

H_R

EQ

#4

H_A

#5

H_A

#12

H_A

#13

H_A

#23

H_R

EQ

#3

H_A

DS

TB

#0

H_A

#24

SP

AR

EP

INS

PA

RE

PIN

SP

AR

EP

INS

PA

RE

PIN

V_C

OR

E

V_C

OR

E

V_C

OR

EV

_CO

RE

V_C

OR

E

GN

D

V_3

V3

V_3

V3

R14

4k7A

R11

62R

A

R3 62RA

R9

62R

A

R13

62R

A

R8

62R

A

R12

62R

A

R7

62R

A

R10

62R

A

R6

62R

A

U1A

SW

478/

S1

E21

G25

P26

V21

J26

K25

K26

L25

H5

H2

E22

K22

R22

W22

F21

J23

P23

W23

AD

6A

D5

AF

26

J1K5J4J3H3

G1L5R5

AC

1V

5

AA

3A

C3

V6

H6

D2

G2

G4

F3

E3

E2

F1

G5

F4

AB

2 J6 C6

B6

B2

B5

AB

23 Y4

AB

26 D1

E5

W5

AB

25

AF

22A

F23

B3

C4

A2

C3

B21

B22

A23

A25

C21

D22

B24

C23

C24

B25

G22

H21

C26

D23

J21

D25

H22

E24

G23

F23

F24

E25

F26

D26

L21

G26

H24

M21

L22

J24

K23

H25

M23

N22

P21

M24

N23

M26

N26

N25

R21

P24

R25

R24

T26

T25

T22

T23

U26

U24

U23

V25

U21

V22

V24

W26

Y26

W25

Y23

Y24

Y21

AA

25A

A22

AA

24

K2

K4L6K1L3M6L2M3

M4

N1

M1

N2

N4

N5

T1

R2

P3

P4

R3

T2

U1

P6

U3

T4

V2

R6

W1

T5

U4

V3

W2

Y1

AB

1

DB

I0#

DB

I1#

DB

I2#

DB

I3#

DP

0#D

P1#

DP

2#D

P3#

DB

SY

#D

RD

Y#

DS

TB

N0#

DS

TB

N1#

DS

TB

N2#

DS

TB

N3#

DS

TB

P0#

DS

TB

P1#

DS

TB

P2#

DS

TB

P3#

BS

EL0

BS

EL1

SK

TO

CC

#

RE

Q0#

RE

Q1#

RE

Q2#

RE

Q3#

RE

Q4#

AD

S#

AD

ST

B0#

AD

ST

B1#

AP

0#A

P1#

BIN

IT#

IER

R#

MC

ER

R#

BR

0#

BP

RI#

BN

R#

LOC

K#

HIT

#H

ITM

#D

EF

ER

#

RS

0#R

S1#

RS

2#

RS

P#

TR

DY

#

A20

M#

FE

RR

#

IGN

NE

#S

MI#

PW

RG

OO

D

ST

PC

LK#

CP

US

LP#

LIN

T0

LIN

T1

INIT

#

RE

SE

T#

BC

LK0

BC

LK1

THERMDA

THERMDC

THERMTRIP#

PR

OC

HO

T#

D0#

D1#

D2#

D3#

D4#

D5#

D6#

D7#

D8#

D9#

D10

#D

11#

D12

#D

13#

D14

#D

15#

D16

#D

17#

D18

#D

19#

D20

#D

21#

D22

#D

23#

D24

#D

25#

D26

#D

27#

D28

#D

29#

D30

#D

31#

D32

#D

33#

D34

#D

35#

D36

#D

37#

D38

#D

39#

D40

#D

41#

D42

#D

43#

D44

#D

45#

D46

#D

47#

D48

#D

49#

D50

#D

51#

D52

#D

53#

D54

#D

55#

D56

#D

57#

D58

#D

59#

D60

#D

61#

D62

#D

63#

A3#

A4#

A5#

A6#

A7#

A8#

A9#

A10

#A

11#

A12

#A

13#

A14

#A

15#

A16

#A

17#

A18

#A

19#

A20

#A

21#

A22

#A

23#

A24

#A

25#

A26

#A

27#

A28

#A

29#

A30

#A

31#

A32

#A

33#

A34

#A

35#

R2 301RA

R4 51RA

R5 62RA

R17

62R

A

H_B

PR

I#9 H

_DE

FE

R#

9

CK

_CP

U+

12C

K_C

PU

-12

H_C

PU

RS

T#

8,9

H_I

NIT

#15H

_RS

#[0.

.2]

9

H_T

RD

Y#

9

H_A

20M

#15

H_I

GN

NE

#15

H_S

MI#

15 PW

RG

OO

D15

ST

PC

LK#

15C

PU

SLP

#15

,18

H_N

MI

15H

_IN

TR

15

SK

TO

CC

#18

BS

EL0

10,1

2

TH

ER

MT

RIP

#16

H_F

ER

R#

15H

_DR

DY

#9

H_D

BS

Y#

9

H_D

[0..6

3]9

H_D

BI#

[0..3

]9

H_D

ST

BP

#[0.

.3]

9

H_D

ST

BN

#[0.

.3]

9

H_A

#[3.

.31]

9 H_R

EQ

#[0.

.4]

9 H_A

DS

TB

#[0.

.1]

9

H_A

DS

#9

H_B

R0#

9

H_B

NR

#9

H_L

OC

K#

9

H_H

IT#

9H

_HIT

M#

9

TH

ER

MD

C33

TH

ER

MD

A33

V_C

OR

E4,

7,8,

11,1

7,33

,35

GN

D4,

7,8,

10..3

5SP

AR

EP

IN7,

9,11

,15,

16,2

4..2

7

V_3

V3

8,12

,15.

.17,

19,2

0,23

,26.

.29,

33,3

5

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

9x Oscon 560uF

ESR max = 9.28mR each

ESL max = 6.4nH each

Iripple = 4.080 each

ESL max = 5nH each

ESR max = 12mR each

ESL typ = 1.15nH each


3x Al Electrolytic 3300uF

Place : Northside of CPU


14x 1206 ker



Place : Inside CPU Socket

ESL max = 6.4nH each

10x 1206 ker


ESL typ = 1.15nH each

Place : Southside of CPU

14x 1206 ker

Place : Between 1206 ker

6x 0603 ker

to eliminate

133MHz x N

Freqs

B44

4B-W

2.00

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R41

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4

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C53 10u/CA

C52 10u/CA

R38

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C36 10u/CA

R32

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C44 10u/CA

C21 10u/CA

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2

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C67

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R23 51RA

C45 10u/CA

R24

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C66

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478/

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P2

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P22

P25

R1

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R23

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AA

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6A

B8

AB

10A

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B20

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21A

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C5

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7A

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11A

C13

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C17

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19A

C22

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4A

D8

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10A

D12

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14A

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D21

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9A

E11

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17A

E19

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22A

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F8

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A11

A13

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A17

A19

A21

A24

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4B

8B

10B

12B

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16B

18B

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26 C2

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26 J2 J5 J22

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25 N3

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VS

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VS

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53V

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S_1

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S_1

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VS

S_1

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VS

S_1

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VS

S_1

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VS

S_1

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VS

S_1

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VS

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VS

S_0

VS

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VS

S_2

VS

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VS

S_4

VS

S_5

VS

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VS

S_7

VS

S_8

VS

S_9

VS

S_1

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VS

S_2

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VS

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VS

S_2

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VS

S_2

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VS

S_2

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VS

S_3

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VS

S_3

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VS

S_3

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VS

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VS

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VS

S_4

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VS

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VS

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VS

S_4

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VS

S_4

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VS

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VS

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VS

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VS

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VS

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VS

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VS

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VS

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VS

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VS

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VS

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VS

S_7

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VS

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VS

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VS

S_7

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VS

S_8

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VS

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VS

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VS

S_8

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_87

VS

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VS

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0

C33 10u/CA

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1

3300

u/E

A

C25 10u/CA

U1B

SW

478/

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A8

A10

A12

A14

A16

A18

A20

B7

B9

B11

B13

B15

B17

B19

C8

C10

C12

C14

C16

C18

C20

D7

D9

D11

D13

D15

D17

D19

E8

E10

E12

E14

E16

E18

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F9

F11

F13

F15

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4

VC

C_0

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C_5

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C_6

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C_7

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C_9

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C_3

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C_4

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C_5

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C_5

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C_5

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DB

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BP

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M1#

BP

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C17 10u/CA

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C27

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R36

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C54 10u/CA

C60

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R31

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C49 10u/CA

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Inte

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Ref

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R736 51RA

C738 100nA

C739 100nA

R733 51RA

R52 27RA

R48 54R9A

R75

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R53 680RA

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BU

S &

CLO

CK

Inte

l (R

) 84

5E In

tera

ctiv

e C

lient

Ref

eren

ce D

esig

n

C9

35M

onda

y, A

pril

21, 2

003

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

eS

heet

of

H_A

#3

H_A

#[3.

.31]

H_A

DS

TB

#[0.

.1]

H_D

[0..6

3]

H_A

DS

#

H_H

ITM

#

H_T

RD

Y#

H_D

RD

Y#

H_H

IT#

H_D

EF

ER

#H

_LO

CK

#

H_D

BS

Y#

H_B

R0#

H_B

NR

#

H_R

S#0

H_B

PR

I#

H_C

PU

RS

T#

H_D

BI#

[0..3

]

H_R

S#[

0..2

]

H_A

DS

TB

#0

H_D

2H

_D3

H_D

4H

_D5

H_D

6H

_D7

H_D

8H

_D9

H_D

10H

_D11

H_D

12H

_D13

H_D

14H

_D15

H_D

16H

_D17

H_D

18H

_D19

H_D

20H

_D21

H_D

22H

_D23

H_D

24H

_D25

H_D

26H

_D27

H_D

28H

_D29

H_D

30H

_D31

H_D

32H

_D33

H_D

34H

_D35

H_D

36H

_D37

H_D

38H

_D39

H_D

40H

_D41

H_D

42H

_D43

H_D

44H

_D45

H_D

46H

_D47

H_D

48H

_D49

H_D

50H

_D51

H_D

52H

_D53

H_D

54H

_D55

H_D

56H

_D57

H_D

58H

_D59

H_D

60H

_D61

H_D

62H

_D63

H_D

0H

_D1

H_D

BI#

0

H_A

#4H

_A#5

H_A

#6H

_A#7

H_A

#8H

_A#9

H_A

#10

H_A

#11

H_A

#12

H_A

#13

H_A

#14

H_A

#15

H_A

#16

H_A

#17

H_A

#18

H_A

#19

H_A

#20

H_A

#21

H_A

#22

H_A

#23

H_A

#24

H_A

#25

H_A

#26

H_A

#28

H_A

#29

H_A

#30

H_A

#31

H_R

S#1

H_R

S#2

H_D

BI#

1H

_DB

I#2

H_D

BI#

3

H_R

EQ

#4

H_R

EQ

#2H

_RE

Q#1

H_R

EQ

#[0.

.4]

H_R

EQ

#0

H_R

EQ

#3

H_A

#27

H_A

DS

TB

#1

H_H

I[0..1

0]

H_HISTB-H_HISTB+

H_D

ST

BN

#0

H_D

ST

BP

#[0.

.3]

H_D

ST

BN

#[0.

.3]

H_D

ST

BP

#0H

_DS

TB

P#1

H_D

ST

BP

#2H

_DS

TB

P#3

H_D

ST

BN

#1H

_DS

TB

N#2

H_D

ST

BN

#3

H_HI5H_HI6H_HI7H_HI8H_HI9H_HI10

CK

_MC

H66

P_R

ST

0#

CK

_MC

H+

CK

_MC

H-

SP

AR

EP

IN

SP

AR

EP

IN

CK_SCK+1CK_SCK+5

CK

_SC

K+[

0..5

]

CK_SCK+3

CK_SCK-4

CK_SCK+4

CK

_SC

K-[

0..5

]

CK_SCK+0CK_SCK+2

CK_SCK-3CK_SCK-5CK_SCK-1CK_SCK-0CK_SCK-2

H_HI0H_HI1H_HI2H_HI3H_HI4

GN

D

U2A

Inte

l (R

) 82

845E

MC

H

L7 M6

G2

N5

H4 L2 J3 M5 J2 K3 L5 L3 M3

M4

K4

N3

N7

N2

P3

P5

R6

P4

R2

P7

R3

U3

T3

T5

T4

AE

16A

D17

AH

17A

E15

AF

16A

C17

AH

15A

G17

AG

16A

G15

AE

14A

G14

AF

14A

C14

AH

13A

G13

AF

12A

E13

AG

12A

H11

AG

10A

G11

AF

10A

E12

AC

10A

G9

AD

9A

E10

AC

9A

E9

AC

12A

C11

AH

5A

F8

AG

6A

G7

AG

8A

F4

AH

3A

H7

AE

5A

G3

AF

3A

H2

AF

6A

E8

AG

2A

G5

AE

2A

C8

AC

3A

C6

AC

7A

D7

AB

7A

E3

AA

6A

A3

AC

5A

B4

AB

3A

A5

AB

5A

A2

V3

W3

Y7

Y4

V5

Y3

Y5

W5

V4

U6

T7

R7

U5

U2

U7

W2

W7

W6

V7

AE

17

AD

5A

G4

AH

9A

D15 R

5N

6

AD

3A

E7

AD

11A

C16

AD

4A

E6

AE

11A

C15

K8J8

P22

E14J24G6G15E24H5

F15G25G7G14G24F5

J27

H26

P25P24N27P23M26M25L28L27M27N28M24

N25N24

HA

#31

HA

#30

HA

#29

HA

#28

HA

#27

HA

#26

HA

#25

HA

#24

HA

#23

HA

#22

HA

#21

HA

#20

HA

#19

HA

#18

HA

#17

HA

#16

HA

#15

HA

#14

HA

#13

HA

#12

HA

#11

HA

#10

HA

#9H

A#8

HA

#7H

A#6

HA

#5H

A#4

HA

#3

HD

#63

HD

#62

HD

#61

HD

#60

HD

#59

HD

#58

HD

#57

HD

#56

HD

#55

HD

#54

HD

#53

HD

#52

HD

#51

HD

#50

HD

#49

HD

#48

HD

#47

HD

#46

HD

#45

HD

#44

HD

#43

HD

#42

HD

#41

HD

#40

HD

#39

HD

#38

HD

#37

HD

#36

HD

#35

HD

#34

HD

#33

HD

#32

HD

#31

HD

#30

HD

#29

HD

#28

HD

#27

HD

#26

HD

#25

HD

#24

HD

#23

HD

#22

HD

#21

HD

#20

HD

#19

HD

#18

HD

#17

HD

#16

HD

#15

HD

#14

HD

#13

HD

#12

HD

#11

HD

#10

HD

#9H

D#8

HD

#7H

D#6

HD

#5H

D#4

HD

#3H

D#2

HD

#1H

D#0

AD

S#

BN

R#

BP

RI#

DE

FE

R#

DB

SY

#

HIT

M#

HIT

#

HLO

CK

#

DR

DY

#

HR

EQ

#0H

RE

Q#1

HR

EQ

#2H

RE

Q#3

HR

EQ

#4

HT

RD

Y#

RS

#0R

S#1

RS

#2

BR

0#

CP

UR

ST

#

DB

I#0

DB

I#1

DB

I#2

DB

I#3

HA

DS

TB

0#H

AD

ST

B1#

HD

ST

BP

#0H

DS

TB

P#1

HD

ST

BP

#2H

DS

TB

P#3

HD

ST

BN

#0H

DS

TB

N#1

HD

ST

BN

#2H

DS

TB

N#3

BC

LK-

BC

LK+

66IN

SCK0+SCK1+SCK2+SCK3+SCK4+SCK5+

SCK0-SCK1-SCK2-SCK3-SCK4-SCK5-

RS

TIN

#

TE

ST

IN#

HI_0HI_1HI_2HI_3HI_4HI_5HI_6HI_7HI_8HI_9

HI_10

HI_STB+HI_STB-

CK

_MC

H+

12C

K_M

CH

-12

CK

_MC

H66

12

P_R

ST

0#15

,18,

33

CK

_SC

K-[

0..5

]13

,14

H_D

EF

ER

#6

H_B

PR

I#6H

_RS

#[0.

.2]

6

H_T

RD

Y#

6

H_D

[0..6

3]6

H_H

I[0..1

0]15

H_H

IST

B+

15H

_HIS

TB

-15

H_D

ST

BP

#[0.

.3]

6

H_D

ST

BN

#[0.

.3]

6

H_A

#[3.

.31]

6 H_R

EQ

#[0.

.4]

6

H_A

DS

#6

H_H

ITM

#6

H_H

IT#

6

H_B

R0#

6

H_B

NR

#6

H_D

BS

Y#

6

H_L

OC

K#

6

H_D

RD

Y#

6H_D

BI#

[0..3

]6 H

_AD

ST

B#[

0..1

]6

GN

D4,

7,8,

10..3

5SP

AR

EP

IN6,

7,11

,15,

16,2

4..2

7

CK

_SC

K+[

0..5

]13

,14

H_C

PU

RS

T#

6,8

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

SET=ENABLE

DDR MODE

B44

4B-W

2.00

MC

H-A

GP

& D

DR

Inte

l (R

) 84

5E In

tera

ctiv

e C

lient

Ref

eren

ce D

esig

n

C10

35M

onda

y, A

pril

21, 2

003

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

eS

heet

of

M_S

CB

5

M_S

CB

2

M_S

MA

9

M_S

MA

5

M_S

MA

3M

_SM

A4

M_S

MA

2

M_S

CB

1

M_S

MA

1

M_S

CB

4

M_S

MA

10

M_S

CB

3

M_S

MA

11

M_S

CB

7

M_S

MA

12

M_S

MA

0

M_S

CB

[0..7

]

M_S

MA

8

M_S

MA

6M

_SM

A7

M_S

CB

0

M_S

CB

6

M_S

MA

[0..1

2]

M_S

CK

E[0

..3]

G_S

T[0

..2]

G_S

BA

7

M_S

MA

X0

M_S

CK

E1

M_S

CK

E2

G_S

BA

4

M_S

CK

E0

G_C

/BE

#0

M_S

CB

X0

G_C

/BE

#[0.

.3]

G_S

BA

0

G_S

BA

3

G_S

BA

6

M_S

CK

E3

M_S

CS

#2

M_S

CS

#[0.

.3]

M_D

X0

M_S

CS

#1

G_S

BA

[0..7

]

G_S

BA

2

G_S

BA

5

M_S

CS

#3

G_S

T2

G_S

BA

1

M_S

CS

#0

G_W

BF

#

G_S

T1X

G_S

T1

BS

ELX

0G

_ST

0

GR

CO

MP

G_C

/BE

#1G

_C/B

E#2

G_C

/BE

#3

M_D

X1M

_DX2

M_D

X3M

_DX4

M_D

X5M

_DX6

M_D

X7M

_DX8

M_D

X9M

_DX1

0M

_DX1

1M

_DX1

2M

_DX1

3M

_DX1

4M

_DX1

5M

_DX1

6M

_DX1

7M

_DX1

8M

_DX1

9M

_DX2

0M

_DX2

1M

_DX2

2M

_DX2

3M

_DX2

4M

_DX2

5M

_DX2

6M

_DX2

7M

_DX2

8M

_DX2

9M

_DX3

0M

_DX3

1M

_DX3

2

M_D

X34

M_D

X35

M_D

X36

M_D

X37

M_D

X38

M_D

X39

M_D

X40

M_D

X42

M_D

X43

M_D

X44

M_D

X45

M_D

X46

M_D

X48

M_D

X49

M_D

X50

M_D

X51

M_D

X52

M_D

X53

M_D

X54

M_D

X55

M_D

X56

M_D

X57

M_D

X58

M_D

X59

M_D

X60

M_D

X61

M_D

X62

M_D

X63

M_S

CB

X2M

_SC

BX3

M_S

CB

X4M

_SC

BX5

M_S

CB

X6M

_SC

BX7

M_S

MA

X1M

_SM

AX2

M_S

MA

X3M

_SM

AX4

M_S

MA

X5M

_SM

AX6

M_S

MA

X7M

_SM

AX8

M_S

MA

X9M

_SM

AX1

0M

_SM

AX1

1M

_SM

AX1

2

M_S

DQ

SX1

M_S

DQ

SX2

M_S

DQ

SX3

M_S

DQ

SX4

M_S

DQ

SX5

M_S

DQ

SX6

M_S

DQ

SX7

M_S

DQ

SX8

G_A

D[0

..31]

G_A

D22

G_A

D24

G_A

D0

G_A

D21

G_A

D2

G_A

D29

G_A

D14

G_A

D19

G_A

D27

G_A

D26

G_A

D18

G_A

D31

G_A

D3

G_A

D16

G_A

D8

G_A

D23

G_A

D12

G_A

D9

G_A

D28

G_A

D5

G_A

D11

G_A

D13

G_A

D4

G_A

D6

G_A

D10

G_A

D17

G_A

D15

G_A

D1

G_A

D7

G_A

D25

G_A

D30

G_A

D20

M_D

X47

M_D

[0..6

3]

M_D

X41

M_D

0

M_D

X33

M_S

CB

X1

M_S

DQ

S6

M_S

DQ

S1

M_S

DQ

S5

M_S

DQ

S0

M_S

DQ

S4

M_S

DQ

S8

M_S

DQ

SX0

M_S

DQ

S3

M_S

DQ

S[0

..8]

M_S

DQ

S7

M_S

DQ

S2

M_D

1M

_D2

M_D

3M

_D4

M_D

5M

_D6

M_D

7M

_D8

M_D

9M

_D10

M_D

11M

_D12

M_D

13M

_D14

M_D

15M

_D16

M_D

17M

_D18

M_D

19M

_D20

M_D

21M

_D22

M_D

23M

_D24

M_D

25M

_D26

M_D

27M

_D28

M_D

29M

_D30

M_D

31M

_D32

M_D

33M

_D34

M_D

35M

_D36

M_D

37M

_D38

M_D

39M

_D40

M_D

41M

_D42

M_D

43M

_D44

M_D

45M

_D46

M_D

47M

_D48

M_D

49M

_D50

M_D

51M

_D52

M_D

53M

_D54

M_D

55M

_D56

M_D

57M

_D58

M_D

59M

_D60

M_D

61M

_D62

M_D

63

M_S

BS

X1M

_SB

SX0

M_S

RA

SX#

M_S

CA

SX#

M_S

WE

X#

RC

VE

N#

GN

DG

ND

GN

D

GN

D

GN

D

GN

D

V_1

V5

V_1

V5

V_1

V5 GN

D

RN

2C33

RX4

56

RN

13B

33R

X43

4

RN

16D

33R

X47

8

RN

10B

33R

X43

4

RN

20A

33R

X41

2

RN

8B33

RX4

34

RN

5B33

RX4

34

R14

033

RA

RN

15C

33R

X45

6

RN

17D

33R

X47

8

RN

3A33

RX4

12

RN

13D

33R

X47

8

R14

60R

A

RN

10C

33R

X45

6

RN

19D

33R

X47

8

R14

40R

A

R74

233

RA

RN

8A33

RX4

12

RN

5C33

RX4

56

RN

15B

33R

X43

4

RN

17A

33R

X41

2

R74

50R

A

RN

3C33

RX4

56

RN

13A

33R

X41

2

R13

90R

A

R74

80R

A

R74

033

RA

RN

10D

33R

X47

8

RN

20C

33R

X45

6

R74

70R

A

RN

8C33

RX4

56

RN

5A33

RX4

12

R12

733

RA

R12

11K

5A

R14

733

RA

RN

18B

33R

X43

4

Q1

BC

847/

B

3

1

2

U2B

Inte

l (R

) 82

845E

MC

H

E9

F7

F9

E7

G28

F27

C28

E28

H25

G27

F25

B28

E27

C27

B25

C25

B27

D27

D26

E25

D24

E23

C22

E21

C24

B23

D22

B21

C21

D20

C19

D18

C20

E19

C18

E17

E13

C12

B11

C10

B13

C13

C11

D10

E10

C9

D8

E8

E11

B9

B7

C7

C6

D6

D4

B3

E6

B5

C4

E5

C3

D3

F4

F3

B2

C2

E2

G5

H3

G3

AF

22

AG

26A

F24

AG

25

AE

23A

E22

R24

R23

AC

27A

C28

AF

27A

F26

AD

25

Y24

W27

W24

W23

W28

AG

24A

H25

AD

24A

C22

AC

24A

C25

AB

24A

A25

AA

24A

B23

Y23

AB

26A

A27

AB

27A

B25

AA

28Y

26Y

27V

24U

25U

24T

24U

23T

23V

27V

26U

28U

27T

27T

26R

25T

25R

28R

27

V25

V23

Y25

AA

23

W25

D14

C15

C17

B17

C14

B15

D16

C16

AE

25A

E24

AE

27A

E28

AG

27A

G28

AH

27A

H28

G22

E20

F13

F21

G20

G21

F19

E18

G19

G18

E16

F17

E12

E15

E3

C5

C8

D12

B19

C23

C26

F26

F23

H23

E22

G23

G13

G12

F11

G8

G11

SC

S#0

SC

S#1

SC

S#2

SC

S#3

SD

Q0

SD

Q1

SD

Q2

SD

Q3

SD

Q4

SD

Q5

SD

Q6

SD

Q7

SD

Q8

SD

Q9

SD

Q10

SD

Q11

SD

Q12

SD

Q13

SD

Q14

SD

Q15

SD

Q16

SD

Q17

SD

Q18

SD

Q19

SD

Q20

SD

Q21

SD

Q22

SD

Q23

SD

Q24

SD

Q25

SD

Q26

SD

Q27

SD

Q28

SD

Q29

SD

Q30

SD

Q31

SD

Q32

SD

Q33

SD

Q34

SD

Q35

SD

Q36

SD

Q37

SD

Q38

SD

Q39

SD

Q40

SD

Q41

SD

Q42

SD

Q43

SD

Q44

SD

Q45

SD

Q46

SD

Q47

SD

Q48

SD

Q49

SD

Q50

SD

Q51

SD

Q52

SD

Q53

SD

Q54

SD

Q55

SD

Q56

SD

Q57

SD

Q58

SD

Q59

SD

Q60

SD

Q61

SD

Q62

SD

Q63

RC

VE

NO

UT

#

RC

VE

NIN

#

PIP

E#

ST

2S

T1

ST

0

WB

F#

RB

F#

AD

_ST

B0+

AD

_ST

B0-

AD

_ST

B1+

AD

_ST

B1-

SB

_ST

B+

SB

_ST

B-

GR

CO

MP

GF

RA

ME

#G

IRD

Y#

GT

RD

Y#

GS

TO

P#

GD

EV

SE

L#

GR

EQ

#G

GN

T#

G_A

D31

G_A

D30

G_A

D29

G_A

D28

G_A

D27

G_A

D26

G_A

D25

G_A

D24

G_A

D23

G_A

D22

G_A

D21

G_A

D20

G_A

D19

G_A

D18

G_A

D17

G_A

D16

G_A

D15

G_A

D14

G_A

D13

G_A

D12

G_A

D11

G_A

D10

G_A

D9

G_A

D8

G_A

D7

G_A

D6

G_A

D5

G_A

D4

G_A

D3

G_A

D2

G_A

D1

G_A

D0

G_C

/BE

0#G

_C/B

E1#

G_C

/BE

2#G

_C/B

E3#

GP

AR

SC

B7

SC

B6

SC

B5

SC

B4

SC

B3

SC

B2

SC

B1

SC

B0

SB

A7

SB

A6

SB

A5

SB

A4

SB

A3

SB

A2

SB

A1

SB

A0

SM

A12

SM

A11

SM

A10

SM

A9

SM

A8

SM

A7

SM

A6

SM

A5

SM

A4

SM

A3

SM

A2

SM

A1

SM

A0

SD

QS

8S

DQ

S7

SD

QS

6S

DQ

S5

SD

QS

4S

DQ

S3

SD

QS

2S

DQ

S1

SD

QS

0

SC

KE

3S

CK

E2

SC

KE

1S

CK

E0

SB

S1

SB

S0

SR

AS

#S

CA

S#

SW

E#

R74

60R

A

RN

7C33

RX4

56

RN

3B33

RX4

34

RN

14D

33R

X47

8

R12

32K

AXX

X1XX

X2

R74

90R

A

RN

10A

33R

X41

2

R15

00R

A

RN

19C

33R

X45

6

R74

433

RA

RN

12B

33R

X43

4

RN

8D33

RX4

78

RN

5D33

RX4

78

R74

333

RA

RN

18D

33R

X47

8

R10

61K

A

R73

80R

A

R12

42K

A

R14

30R

A

RN

7D33

RX4

78

RN

3D33

RX4

78

R16

040

R2A

RN

14A

33R

X41

2

R13

733

RA

RN

20D

33R

X47

8

RN

1B33

RX4

34

RN

12D

33R

X47

8

RN

9D33

RX4

78

R128 6K8A

RN

18C

33R

X45

6

R73

70R

A

RN

7A33

RX4

12

RN

4C33

RX4

56

RN

14B

33R

X43

4

R13

80R

A

R14

90R

A

RN

19A

33R

X41

2R

117

1K5A

RN

2D33

RX4

78

RN

12A

33R

X41

2

RN

16C

33R

X45

6

RN

9B33

RX4

34

RN

18A

33R

X41

2

RN

1D33

RX4

78

RN

7B33

RX4

34

RN

4D33

RX4

78

RN

14C

33R

X45

6

RN

2A33

RX4

12

RN

12C

33R

X45

6

R14

10R

A

RN

16B

33R

X43

4

RN

9A33

RX4

12

R14

50R

A

RN

19B

33R

X43

4

RN

1A33

RX4

12

RN

4A33

RX4

12

RN

15A

33R

X41

2

RN

17C

33R

X45

6

R11

11K

A

RN

2B33

RX4

34

RN

13C

33R

X45

6

RN

16A

33R

X41

2

RN

9C33

RX4

56

RN

1C33

RX4

56

R14

80R

A

R14

20R

A

RN

20B

33R

X43

4

R73

90R

A

R74

133

RA

RN

4B33

RX4

34

RN

15D

33R

X47

8

RN

17B

33R

X43

4

BS

EL0

6,12

G_S

BA

[0..7

]26

G_R

EQ

#26

G_R

BF

#26

G_P

IPE

#26

G_S

BS

TB

+26

G_S

BS

TB

-26

M_S

CS

#[0.

.3]

13,1

4

M_S

MA

[0..1

2]13

,14

M_S

CK

E[0

..3]

13,1

4

M_S

WE

#13

,14

M_S

CA

S#

13,1

4M

_SR

AS

#13

,14

M_S

BS

013

,14

M_S

BS

113

,14

G_S

T[0

..2]

26

G_G

NT

#26

M_D

[0..6

3]13

,14

M_S

CB

[0..7

]13

,14

M_S

DQ

S[0

..8]

13,1

4

G_A

D[0

..31]

26

G_C

/BE

#[0.

.3]

26

G_D

EV

SE

L#26

G_S

TO

P#

26G

_TR

DY

#26

G_I

RD

Y#

26G

_FR

AM

E#

26

G_P

AR

26 G_A

DS

TB

1+26

G_A

DS

TB

1-26

G_A

DS

TB

0-26

G_A

DS

TB

0+26

V_1

V5

11,1

7,28

,33,

34

GN

D4,

7,8,

11..3

5

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Between

MCH and

DIMM

All VCCSM Balls of MCH

1206 / X5R

1206 / X7R

1206 / X7R

0603 / X7R

1206 / X7R

0603 / X7R

0603 / X7R

WIRED

B44

4B-W

2.00

MC

H-P

OW

ER

Inte

l (R

) 84

5E In

tera

ctiv

e C

lient

Ref

eren

ce D

esig

n

C11

35M

onda

y, A

pril

21, 2

003

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

eS

heet

of

HR

CO

MP

1H

RC

OM

P0

HS

WN

G

V_1

V5A

2

GN

D_A

MC

H

HV

RE

F_M

CH

SP

AR

EP

IN

SP

AR

EP

IN

SPAREPINSPAREPIN

HLR

CO

MP

SM

RC

OM

P

V_1

V5A

1

V_D

DR

V_D

DR

REF

V_C

OR

E

V_D

DR

REF

V_D

DR

GN

DG

ND

GN

D

GN

D

GN

D

GN

DG

ND

GN

DG

ND

GN

D

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

D

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

D

V_1

V5

V_1

V5

V_1

V5

V_1

V5

V_1

V5

V_1

V5

V_1

V8

V_1

V8

V_1

V8

V_1

V8

V_C

OR

E

V_C

OR

E

V_D

DR

VTT

V_D

DR

VTT

V_C

OR

E

GN

D

C70

100n

A

R16

624

R9A

+

C92 100u/TA

R16

240

R2A

C88

10nA

+C

72

33u/

TA

R16

730

R1A

C80 100nA

R16

310

0RA

C109 10u/CA

C114 100nA

R16

149

R9A

C79 100nA

C86 100nA

R16

524

R9A

C97 100nA

C115 100nA

L34u

H7/

SB

C96 100nAC84 100nA

R16

430

1RA

C113 100nA

C85 100nA

C99 100nA

C90

100n

A

+

C77 100u/BP

C112 10u/CA

C89

10nA

C83 100nA

R16

815

0RA

C98 100nA

+

C75

33u/

TA

C102 100n

U2C

Inte

l (R

) 82

845E

MC

H

Y8

R8

M7

AB

17A

B11

J21 J9

P26

AA

21

P27

AC

13A

C2

AD

13A

A7

J28

AG29

AC29

W29

R29

AE26

AA26

U26

AJ25

AF23

AD23

AA22

W22

U22

R22

AD21

AB21

P17

U16

R16

N16

T15

P15

U14

R14

N14

P13

L25L29

N26N23M22

A5

A9

A13

A17

A21

A25

C1

C29

D7

D11

D15

D19

D23

D25

F6

F10

F14

F18

F22

G1

G4

G29

H8

H10

H12

H14

H16

H18

H20

H22

H24

J5 J7 K6

K22

K24

K26

L23

T13

U13

T17

U17

AJ2

3A

G23

AJ2

1A

G21

AF

20A

E21

AD

20A

B20

AJ1

9A

G19

AE

19A

C19

AF

18A

D18

AB

18A

A9

AB

8U

8M

8

A15

A11A

7A

3

A19

A23

A27 D

5D

9D

13D

17D

21 E1

E4

E26

E29 F

8F

12F

16F

20F

24G

26 H9

H11

H13

H15

H17

H19

H21 J1 J4 J6 J2

2J2

6J2

9K

5K

7K

27 L1 L4 L6 L8 L22

L24

L26

M23 N

1N

4N

8N

13N

15N

17N

22N

29 P6

P8

P14P16R1R4R13R15R17R26T6T8T14T16T22U1U4U15U29V6V8V22

W1W4W8W26Y6Y22

AA

1A

A4

AA

8A

A29

AB

6A

B9

AB

10A

B12

AB

13A

B14

AB

15A

B16

AB

19A

B22

AC

1A

C4

AC

18A

C20

AC

21A

C23

AC

26A

D6

AD

8A

D10

AD

12A

D14

AD

16A

D19

AD

22A

E1

AE

4A

E18

AE

20A

E29

AF

5A

F7

AF

9A

F11

AF

13A

F15

AF

17A

F19

AF

21A

F25

AJ3

AJ5

AJ7

AJ9

AG

1A

G18

AG

20A

G22

AH

19A

H21

AH

23

AJ1

1A

J13

AJ1

5

AJ1

7A

J27

AD26AD27

H7H6G17G16G10G9J25J23K23K25H27

HV

RE

F5

HV

RE

F4

HV

RE

F3

HV

RE

F2

HV

RE

F1

SD

RE

F2

SD

RE

F1

HI_

RE

F

AG

PR

EF

HLR

CO

MP

HR

CO

MP

1H

RC

OM

P0

HS

WN

G1

HS

WN

G0

SM

RC

OM

P

VCC1_5

VCC1_5

VCC1_5

VCC1_5

VCC1_5

VCC1_5

VCC1_5

VCC1_5

VCC1_5

VCC1_5

VCC1_5

VCC1_5

VCC1_5

VCC1_5

VCC1_5

VCC1_5

VCC1_5

VCC1_5

VCC1_5

VCC1_5

VCC1_5

VCC1_5

VCC1_5

VCC1_5

VCC1_5

VCC1_5

VCC1_8VCC1_8

VCC1_8VCC1_8VCC1_8

VC

CS

MV

CC

SM

VC

CS

MV

CC

SM

VC

CS

MV

CC

SM

VC

CS

MV

CC

SM

VC

CS

MV

CC

SM

VC

CS

MV

CC

SM

VC

CS

MV

CC

SM

VC

CS

MV

CC

SM

VC

CS

MV

CC

SM

VC

CS

MV

CC

SM

VC

CS

MV

CC

SM

VC

CS

MV

CC

SM

VC

CS

MV

CC

SM

VC

CS

MV

CC

SM

VC

CS

MV

CC

SM

VC

CS

MV

CC

SM

VC

CS

MV

CC

SM

VC

CS

MV

CC

SM

VC

CS

MV

CC

SM

VC

C1_

5

VS

S

VC

C1_

5

VS

S

VT

TV

TT

VT

TV

TT

VT

TV

TT

VT

TV

TT

VT

TV

TT

VT

TV

TT

VT

TV

TT

VT

TV

TT

VT

TV

TT

VT

T

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND

GNDGNDGNDGNDGNDGND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GND

GN

DG

ND

GN

D

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

D

GN

DG

ND

GN

D

GN

DG

ND

NC1NC2

RSVD11RSVD10RSVD9RSVD8RSVD7RSVD6RSVD5RSVD4RSVD3RSVD2RSVD1

C69

100n

A

C103 100n

C101 100nA

C94 10u/CA

C104 100n

C95 10u/CA

L44u

H7/

SB

C105 100n

+

C93 100u/TA

+

C78 100u/BP

C106 100n

C110 10u/CA

C100 100nA

C91

100n

A

HI_

RE

F15

V_1

V5

10,1

7,28

,33,

34

GN

D4,

7,8,

10,1

2..3

5

V_1

V8

15,1

7,33

,35V

_CO

RE

4,6.

.8,1

7,33

,35

V_D

DR

VT

T14

,34

V_D

DR

RE

F13

,14,

34V

_DD

R13

,14,

33,3

4

AG

P_R

EF

28

SP

AR

EP

IN6,

7,9,

15,1

6,24

..27

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

B44

4B-W

2.00

CLK

ICS

9502

01Inte

l (R

) 84

5E In

tera

ctiv

e C

lient

Ref

eren

ce D

esig

n

C12

35M

onda

y, A

pril

21, 2

003

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

eS

heet

of

IRE

F_C

K

CK

_RE

S0

CK

_RE

S1

CK

_RE

S2

A_CLKX2CK

_RE

SX0

CK

_RE

SX1

CK

_CP

UX+

CK

_SLO

T3X

CK

_RE

SX2

CK

_IC

H48

X

CK

_MC

HX+

CK

_MC

H66

X

CK

_MC

HX-

MU

LTIS

EL

CK

_IT

PX+

CK

_MP

CIX

CK

_CP

LDX

CK

_AG

P66

X

CK

_SLO

T2X

CK

_CP

UX-

CK

_SLO

T1X

CK

_14M

X

CK

_FW

HX

CK

_IC

H66

X

FS

0

CK

_LA

NX

A_CLKX1C

K_L

PC

1X

CK

_IT

PX-

BS

EL2

CK

_LP

C0X

CK

_IC

H33

X

V_C

LK

V_C

LK

V_C

LK

V_C

LK

V_3

V3

GN

D

V_3

V3

V_3

V3

V_3

V3

V_3

V3

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

D

V_C

LKA

GN

DG

ND

GN

D

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

D

V_3

V3

V_3

V3

GN

D

GN

D

GN

DG

ND

GN

DG

ND

GN

DG

ND

V_3

V3

R7691KA

R17

933

RA

C12

4

10nA

R17

533

RA

R56 49R9A

C11

8

100n

A

R17

733

RA

C141 10pA

C11

6

10u/

CA

FB

1B

LM21

B60

1S

R17

327

RA

C133 10pA

R1841KA

R18

033

RA

R19

933

RA

U3

ICS

9502

01G

T

181419 2632 374650 4 9 15 20 2731 36 41 47 23

4329 30253453 28425638 3933 35 21 22 23 24 5 6 7 10 11 12 13 16 17 1852 51 49 48 45 44

545540

VD

DA

RE

F

VD

DP

CI1

VD

DP

CI2

VD

D3V

66

VD

DA

VD

D3V

66

VD

DA

48

VD

DC

PU

VD

DC

PU

GN

DG

ND

GN

DG

ND

GN

DA

GN

DG

ND

GN

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B60

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C130 10pA

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533

RA

R17

027

RA

C11

9

100n

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R1831KA

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533

RA

R17

427

RA

R17

227

RA

C135 10pA

C128 10pA

R19

333

RA

R19

01K

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R16

927

RA

C136 10pA

C134 10pA

R19

233

RA

R18

733

RA

C132 10pA

C11

7

100n

A

R19

733

RA

R20

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C137 10pA

C127 10pA

C12

3

10nA

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R19

133

RA

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5

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R17

127

RA

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1

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933

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R19

633

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0

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R15 49R9A

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833

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433

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BS

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CK

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9

CK

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K_I

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CK

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9

CK

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26

CK

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K_I

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6616

CK

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16

CK

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16,1

9,20

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CK

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CK

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120

CK

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CK

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CK

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CK

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29

CK

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5

V_C

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7,8,

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1,13

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7,19

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23,2

6..2

9,33

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SM

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5

5 5

4 4

3 3

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Ref

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2]

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CA

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M_S

CB

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M_S

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CK

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K+1

CK

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K+2

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0..5

]

CK

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K-0

CK

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K-1

CK

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K-2

CK

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K-[

0..5

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M_D

56

M_D

44

M_D

5

M_D

21

M_D

[0..6

3]

M_D

39

M_D

60

M_D

11

M_D

31

M_D

17

M_D

50

M_D

43

M_D

45

M_D

38

M_D

54

M_D

59

M_D

24

M_D

36

M_D

18

M_D

16

M_D

35

M_D

29

M_D

27M

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M_D

51M

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M_D

1

M_D

34

M_D

42

M_D

28

M_D

49

M_D

22

M_S

CB

[0..7

]

M_S

DQ

S0

M_S

DQ

S1

M_S

DQ

S2

M_S

DQ

S3

M_S

DQ

S4

M_S

DQ

S5

M_S

DQ

S6

M_S

DQ

S7

M_S

DQ

S8

M_S

DQ

S[0

..8]

M_S

CK

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M_S

CK

E[0

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M_S

CS

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M_S

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.3]

M_S

MA

1M

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A2

M_S

MA

3M

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A4

M_S

MA

5M

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A6

M_S

MA

7M

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A8

M_S

MA

9M

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A10

M_S

MA

11M

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A12

M_D

0

M_D

2M

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M_D

4

M_D

6M

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M_D

8M

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M_D

10

M_D

12M

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M_D

14M

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M_D

19M

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M_D

23

M_D

25

M_D

30

M_D

32M

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M_D

37

M_D

40M

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M_D

46M

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M_D

48

M_D

53

M_D

55

M_D

57M

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M_D

61M

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M_D

63

M_S

CB

0M

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B1

M_S

CB

2M

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B3

M_S

CB

4

V_D

DR

V_D

DR

REF

V_D

DR

V_D

DR

REF

GN

D

GN

D

GN

D

GN

D

GN

D

V_D

DR

C14

6

100n

A

CN

2

SW

184/

D1

48 43 41 130 37 32 125 29 122 27 141

2 4 6 8 94 95 98 99 12 13 19 20 105

106

109

110

23 24 28 31 114

117

121

123

33 35 39 40 126

127

131

133

53 55 57 60 146

147

150

151

61 64 68 69 153

155

161

162

72 73 79 80 165

166

170

171

83 84 87 88 174

175

178

179

44 45 49 51 134

135

142

144

63118

115

103 59 52 65 154

15223054627796104112128136143156164172180

738467085108120148168

113

157

15871163 97 107

119

129

149

159

169

177

140 21 111 16 17137

138 7576

90

5 14 25 36 56 67 78 86 47 91 92 181

182

183

18482 19 10 101

102

173

167

3111826344250586674818993100116124132139145152160176

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

D31

D32

D33

D34

D35

D36

D37

D38

D39

D40

D41

D42

D43

D44

D45

D46

D47

D48

D49

D50

D51

D52

D53

D54

D55

D56

D57

D58

D59

D60

D61

D62

D63

CB

0C

B1

CB

2C

B3

CB

4C

B5

CB

6C

B7

WE

#

A11

A12

A13

BA

0B

A1

CA

S#

RA

S#

VDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQ

VDDVDDVDDVDDVDDVDDVDDVDDVDD

BA

2

CS

0#C

S1#

CS

2#/N

CC

S3#

/NC

DQ

M0

DQ

M1

DQ

M2

DQ

M3

DQ

M4

DQ

M5

DQ

M6

DQ

M7

DQ

M8

CK

E0

CK

E1

CK

0/D

NU

CK

0#/D

NU

CK

1

CK

1#C

K2#

/DN

U

CK

2/D

NU

WP

DQ

S0

DQ

S1

DQ

S2

DQ

S3

DQ

S4

DQ

S5

DQ

S6

DQ

S7

DQ

S8

SD

AS

CL

SA

0S

A1

SA

2

VD

DS

PD

VD

DID

VR

EF

NC

1N

C/R

ES

ET

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C2

NC

3N

C4

NC

/FE

TE

N

GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND

M_S

WE

#10

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M_S

CA

S#

10,1

4M

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AS

#10

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M_S

BS

010

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M_S

BS

110

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CK

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K+[

0..5

]9,

14

CK

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K-[

0..5

]9,

14

M_S

CK

E[0

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10,1

4

M_S

CS

#[0.

.3]

10,1

4

M_S

MA

[0..1

2]10

,14

M_D

[0..6

3]10

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M_S

CB

[0..7

]10

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M_S

DQ

S[0

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10,1

4

SM

BIS

OD

12,1

4,15

GN

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7,8,

10..1

2,14

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R11

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33,3

4V_D

DR

RE

F11

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34

SM

BIS

OC

12,1

4,15

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

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DIM

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At Corner of DIMMS

B44

4B-W

2.00

DD

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1

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Ref

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of

M_D

31

M_D

46

M_D

0

M_D

38

M_D

36

M_D

26

M_D

6

M_D

1

M_D

58

M_D

43

M_D

2

M_D

56

M_D

50

M_D

24

M_D

28

M_D

39

M_D

11

M_D

48

M_D

24

M_D

15

M_D

10

M_D

53

M_D

60

M_D

19

M_D

34

M_D

8

M_D

19

M_D

3

M_D

30M

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M_D

45

M_D

37

M_D

35

M_D

5

M_D

57

M_D

55

M_D

42

M_D

1

M_D

43

M_D

54

M_D

38

M_D

47

M_D

23

M_D

25

M_D

14

M_D

9

M_D

18

M_D

5

M_D

52

M_D

49

M_D

33

M_D

27

M_D

29

M_D

18

M_D

44

M_D

59

M_D

34

M_D

41M

_D42

M_D

46

M_D

53

M_D

61

M_D

63M

_D63

M_D

22

M_D

13

M_D

8

M_D

4

M_D

56

M_D

51

M_D

48

M_D

32

M_D

26

M_D

37

M_D

28

M_D

17

M_D

14

M_D

22

M_D

58

M_D

17

M_D

33

M_D

40M

_D41

M_D

45

M_D

4

M_D

52

M_D

62

M_D

60

M_D

62

M_D

21

M_D

12

M_D

7

M_D

10

M_D

7

M_D

50

M_D

25

M_D

31

M_D

55

M_D

27

M_D

36

M_D

13

M_D

16

M_D

21

M_D

47

M_D

32

M_D

23

M_D

40M

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M_D

44

M_D

3

M_D

51

M_D

2

M_D

59

M_D

61

M_D

57

M_D

20

M_D

6

M_D

15

M_D

[0..6

3]

M_D

49

M_D

30

M_D

11

M_D

54

M_D

16

M_D

35

M_D

12

M_D

9

M_D

0

M_D

20

M_S

CA

S#

M_S

WE

#

M_S

RA

S#

CK

_SC

K-[

0..5

]

CK

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K-3

CK

_SC

K+[

0..5

]

CK

_SC

K+3

CK

_SC

K+4

CK

_SC

K+5

CK

_SC

K-4

CK

_SC

K-5

M_S

BS

0M

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S1

M_S

CS

#0

M_S

WE

#M

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AS

#

M_S

CK

E0

M_S

RA

S#

M_S

MA

0

M_S

DQ

S3

M_S

DQ

S1

M_S

DQ

S6

M_S

DQ

S0

M_S

DQ

S8

M_S

DQ

S7

M_S

DQ

S2

M_S

DQ

S[0

..8]

M_S

DQ

S5

M_S

DQ

S4

M_S

DQ

S0

M_S

DQ

S1

M_S

DQ

S2

M_S

DQ

S3

M_S

DQ

S4

M_S

DQ

S5

M_S

DQ

S6

M_S

DQ

S7

M_S

DQ

S8

M_S

CK

E[0

..3]

M_S

CK

E2

M_S

CK

E3

M_S

CK

E1

M_S

CK

E2

M_S

CK

E3

M_S

CS

#1M

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S#2

M_S

MA

9

M_S

MA

6

M_S

MA

0

M_S

MA

12

M_S

MA

[0..1

2]

M_S

MA

1

M_S

MA

4

M_S

MA

2

M_S

MA

11

M_S

MA

7M

_SM

A8

M_S

MA

5

M_S

MA

10

M_S

MA

3

M_S

MA

1M

_SM

A2

M_S

MA

3M

_SM

A4

M_S

MA

5M

_SM

A6

M_S

MA

7M

_SM

A8

M_S

MA

9M

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A10

M_S

MA

11M

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A12

M_S

CS

#[0.

.3]

M_S

BS

1

M_S

CS

#2

M_S

BS

0

M_S

CS

#3

M_S

CS

#3

M_S

CB

[0..7

]

M_S

CB

0

M_S

CB

6

M_S

CB

4

M_S

CB

1M

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B2

M_S

CB

3

M_S

CB

7

M_S

CB

5M

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B4

M_S

CB

0

M_S

CB

7M

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B6

M_S

CB

2M

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B1

M_S

CB

5

M_S

CB

3

V_D

DR

V_D

DR

REF

V_D

DR

V_D

DR

REF

V_D

DR

V_D

DR

GN

D

GN

D

GN

D

GN

D

GN

D

GN

DG

ND

GN

D

GN

D

GN

D

GN

D

V_D

DR

VTT

V_D

DR

VTT

V_D

DR

V_D

DR

V_D

DR

VTT

V_D

DR

VTT

V_D

DR

VTT

V_D

DR

VTT

V_D

DR

VTT

V_D

DR

VTT

RN

21B

47R

X43

4

RN

11C

47R

X45

6

CN

3

SW

184/

D1

48 43 41 130 37 32 125 29 122 27 141

2 4 6 8 94 95 98 99 12 13 19 20 105

106

109

110

23 24 28 31 114

117

121

123

33 35 39 40 126

127

131

133

53 55 57 60 146

147

150

151

61 64 68 69 153

155

161

162

72 73 79 80 165

166

170

171

83 84 87 88 174

175

178

179

44 45 49 51 134

135

142

144

63118

115

103 59 52 65 154

15223054627796104112128136143156164172180

738467085108120148168

113

157

15871163 97 107

119

129

149

159

169

177

140 21 111 16 17137

138 7576

90

5 14 25 36 56 67 78 86 47 91 92 181

182

183

18482 19 10 101

102

173

167

3111826344250586674818993100116124132139145152160176

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

D31

D32

D33

D34

D35

D36

D37

D38

D39

D40

D41

D42

D43

D44

D45

D46

D47

D48

D49

D50

D51

D52

D53

D54

D55

D56

D57

D58

D59

D60

D61

D62

D63

CB

0C

B1

CB

2C

B3

CB

4C

B5

CB

6C

B7

WE

#

A11

A12

A13

BA

0B

A1

CA

S#

RA

S#

VDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQVDDQ

VDDVDDVDDVDDVDDVDDVDDVDDVDD

BA

2

CS

0#C

S1#

CS

2#/N

CC

S3#

/NC

DQ

M0

DQ

M1

DQ

M2

DQ

M3

DQ

M4

DQ

M5

DQ

M6

DQ

M7

DQ

M8

CK

E0

CK

E1

CK

0/D

NU

CK

0#/D

NU

CK

1

CK

1#C

K2#

/DN

U

CK

2/D

NU

WP

DQ

S0

DQ

S1

DQ

S2

DQ

S3

DQ

S4

DQ

S5

DQ

S6

DQ

S7

DQ

S8

SD

AS

CL

SA

0S

A1

SA

2

VD

DS

PD

VD

DID

VR

EF

NC

1N

C/R

ES

ET

#N

C2

NC

3N

C4

NC

/FE

TE

N

GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND

RN

24C

47R

X45

6

C159 100nA

C193 100nA

C213 100nA

C218 100nA

RN

45B

47R

X43

4

RN

37C

47R

X45

6

RN

27C

47R

X45

6

R75

156

RA

RN

31B

47R

X43

4

RN

22D

47R

X47

8

C175 100nA

RN

32C

56R

X45

6

RN

40D

47R

X47

8

+

C167 220u/PB

C154 100nA

R75

056

RA

RN

34C

47R

X45

6

C164 100nA

RN

35B

56R

X43

4

RN

26B

47R

X43

4

C191 100nA

C174 100nA

RN

21A

47R

X41

2

RN

11A

47R

X41

2

RN

24A

47R

X41

2

C161 100nA

RN

41B

56R

X43

4

C207 100nA

C194 100nA

C220 100nA

RN

45C

47R

X45

6

RN

26C

47R

X45

6

RN

22A

47R

X41

2

RN

35D

56R

X47

8R

N29

B47

RX4

34

C221 100nA

C190 100nA

C163 100nA

C170 10u/CA

RN

11D

47R

X47

8

RN

6D47

RX4

78

RN

33C

47R

X45

6

RN

24B

47R

X43

4

C160 100nA

RN

41A

56R

X41

2

C205 100nA

R75

256

RA

RN

45D

47R

X47

8

RN

36A

47R

X41

2

RN

28D

47R

X47

8

RN

21C

47R

X45

6

RN

22B

47R

X43

4

RN

35A

56R

X41

2

C214 100nA

RN

38A

47R

X41

2

RN

27B

47R

X43

4

C200 100nA

C165 100nA

RN

11B

47R

X43

4

RN

6B47

RX4

34

C206 100nA

RN

24D

47R

X47

8

RN

33B

47R

X43

4

C162 100nAC183 100nA

RN

26D

47R

X47

8

R23

847

RA

+

C148 100u/TA

C210 100nA

C171 10u/CA

C199 100nA

RN

39C

47R

X45

6

RN

27D

47R

X47

8

RN

22C

47R

X45

6

RN

44D

47R

X47

8

RN

35C

56R

X45

6

RN

41C

56R

X45

6

RN

37A

47R

X41

2

RN

28C

47R

X45

6

C179 100nA

C166 100nA

RN

6A47

RX4

12

C197 100nA

+

C150 100u/TA

C226 100nA

RN

33D

47R

X47

8

RN

25C

47R

X45

6

RN

42B

56R

X43

4

RN

30C

47R

X45

6

RN

38D

47R

X47

8

C182 100nA

C169 10u/CA

C211 100nA

RN

30D

47R

X47

8

C178 100nA

RN

39A

47R

X41

2

C217 100nA

C204 100nA

RN

23B

47R

X43

4

C151 100nA

C156 100nA

C192 100nA

RN

43D

47R

X47

8

RN

21D

47R

X47

8

RN

44B

47R

X43

4

RN

28A

47R

X41

2

RN

37B

47R

X43

4

+

C147 100u/TA

C177 100nA

C185 100nA

RN

6C47

RX4

56

RN

33A

47R

X41

2

RN

25D

47R

X47

8

RN

37D

47R

X47

8

RN

42D

56R

X47

8

RN

29C

47R

X45

6

C198 100nA

C224 100nA

RN

30A

47R

X41

2

RN

39B

47R

X43

4

C187 100nA

C203 100nA

C209 100nA

RN

23A

47R

X41

2

C155 100nA

C222 100nA

RN

43B

47R

X43

4

RN

44C

47R

X45

6

RN

36D

47R

X47

8

RN

28B

47R

X43

4

C195 100nA

C188 100nA

RN

31D

47R

X47

8

RN

32B

56R

X43

4

RN

40C

47R

X45

6

C181 100nA

C152 100nA C173 100nA

RN

34D

47R

X47

8

RN

25B

47R

X43

4

C216 100nA

RN

42A

56R

X41

2

RN

36C

47R

X45

6

RN

29D

47R

X47

8

C225 100nA

RN

39D

47R

X47

8

C208 100nA

C189 100nA

RN

23C

47R

X45

6

C158 100nA

RN

43C

47R

X45

6

C21

2

100n

A

RN

44A

47R

X41

2

RN

27A

47R

X41

2

C201 100nA

RN

31C

47R

X45

6

RN

32D

56R

X47

8

RN

40A

47R

X41

2

C215 100nA

RN

34A

47R

X41

2

RN

25A

47R

X41

2

RN

42C

56R

X45

6

RN

30B

47R

X43

4

C180 100nA

C219 100nA

RN

38C

47R

X45

6

C184 100nA

C196 100nA

C153 100nA

C223 100nA

RN

23D

47R

X47

8

C157 100nA

RN

43A

47R

X41

2

RN

41D

56R

X47

8

RN

45A

47R

X41

2

RN

38B

47R

X43

4

RN

29A

47R

X41

2

C172 100nA

+

C149 100u/TA

RN

31A

47R

X41

2

RN

32A

56R

X41

2

RN

40B

47R

X43

4

C202 100nA

RN

34B

47R

X43

4

C176 100nA

RN

36B

47R

X43

4

RN

26A

47R

X41

2

C186 100nA

M_S

RA

S#

10,1

3

M_S

WE

#10

,13

M_S

CA

S#

10,1

3

CK

_SC

K+[

0..5

]9,

13

CK

_SC

K-[

0..5

]9,

13

M_S

BS

010

,13

M_S

BS

110

,13

M_S

CK

E[0

..3]

10,1

3

M_S

CS

#[0.

.3]

10,1

3

M_S

MA

[0..1

2]10

,13

M_D

[0..6

3]10

,13

M_S

CB

[0..7

]10

,13

M_S

DQ

S[0

..8]

10,1

3

GN

D4,

7,8,

10..1

3,15

..35

V_D

DR

RE

F11

,13,

34V

_DD

R11

,13,

33,3

4V_D

DR

VT

T11

,34

SM

BIS

OD

12,1

3,15

SM

BIS

OC

12,1

3,15

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Level Shifter for

Firmware Hub

INIT#

Hub interface

reference voltages

populate for "top block swap" A

B

B44

4B-W

2.00

ICH

4-S

YS

BU

S &

PC

I

Inte

l (R

) 84

5E In

tera

ctiv

e C

lient

Ref

eren

ce D

esig

n

C15

35M

onda

y, A

pril

21, 2

003

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

eS

heet

of

INT

_PIR

QH

#

PC

IRS

T#

H_I

NIT

#

INT

_PIR

QC

#

INITB#

INT

_PIR

QE

#

INIT

B

INT

_IR

Q14

INT

_PIR

QD

#

INT

_PIR

QB

#

INT

_PIR

QG

#

INT

_IR

Q15

INT

_PIR

QA

#

INT

_PIR

QF

#

SE

RIR

Q

H_H

I10

INT

_PIR

QB

#

P_A

D30

H_H

I6

H_H

I1

INT

_PIR

QE

#

INT

_PIR

QA

#

H_F

ER

R#

H_H

I7

H_H

I5

LAN

_XT

XD2

P_A

D12

P_A

D9

CK

_IC

HLA

NX

P_A

D25

P_A

D24

AP

ICD

1

PW

RG

OO

D

H_I

NIT

#

P_C

BE

#3

P_A

D0

LAN

_XT

XD1

EE

0_C

SE

E0_

CK

KB

_RS

T#

P_A

D26

P_A

D4

H_H

I4

INT

_PIR

QC

#

H_I

GN

NE

#

SM

BA

LER

T#

P_A

D16

LAN

_RS

CX

INT

_IR

Q14

H_H

IST

B-

P_A

D27

H_H

I2

LAN

_XT

XD0

H_H

IST

B+

P_C

BE

#1

P_A

D6

LAN

_XR

XD0

CP

US

LP#

P_A

D29

P_A

D21

P_A

D7

INT

_PIR

QH

#

P_A

D20

P_A

D15

P_A

D14

P_A

D10

P_A

D2

H_H

I8

H_I

NT

R

P_A

D31

INT

_PIR

QG

#IN

T_P

IRQ

F#

ST

PC

LK#

P_C

BE

#2

P_A

D28

P_A

D11

P_A

D1

SM

BD

AT

A

LAN

_XR

XD2

LAN

_XR

XD1

SE

RIR

Q

INT

_IR

Q15

INT

_PIR

QD

#

H_N

MI

INT

RU

DE

R#

PC

IRS

TX#

P_A

D17

P_A

D3

AP

ICD

0

A20

GA

TE

P_C

BE

#0

P_A

D23

P_A

D18

H_H

I3

AP

ICC

LK

HI_

CO

MP

H_S

MI#

P_A

D13

P_A

D5

H_H

I9

H_H

I0

H_A

20M

#

P_A

D22

P_A

D19

P_A

D8

XRS

T_S

LOT

S#

P_R

ST

X0#

P_R

ST

X1#

IDE

_RS

TX#

EE

0_D

O

SM

BIS

OD

SM

BIS

OC

EE

0_8#

_16

SP

AR

EP

IN

SP

AR

EP

IN

XC_L

AN

0RS

T#

SP

AR

EP

IN

EE

0_D

I

P_R

EQ

A#

P_R

EQ

#1

P_S

TO

P#

P_P

ME

#

P_F

RA

ME

#

P_P

ER

R#

P_R

EQ

#0

P_S

ER

R#

P_R

EQ

#3

P_L

OC

K#

P_D

EV

SE

L#

P_T

RD

Y#

P_R

EQ

#4

P_I

RD

Y#

P_R

EQ

#2

LM87

INT

#

SM

BD

AT

AS

MB

CLK

SM

BC

LK

SP

AR

EP

IN

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

D

GN

D

V_1

2V0

V_1

2V0

V_1

2V0

V_1

V8

V_1

V8

V_3

V3

V_3

V3

V_3

V3

V_3

V3S

B

V_3

V3S

B

V_3

V3S

B

V_3

V3S

B

V_3

V3S

B

V_3

V3S

B

V_3

V3S

B

V_3

V3S

B

V_3

V3S

BV

_3V

3SB

V_R

TC

V_R

TC

GN

D

V_3

V3

V_3

V3

V_3

V3S

B

V_3

V3

V_3

V3

R33

18K

2A

D S

G

2N70

02/B

Q2

R32

28K

2A

R32

710

KA

R36

8

33R

A

Q4

BC

847/

B

3

1

2

R32

88K

2A

C23

1

100n

A

R35

522

RA

R34

88K

2A

R32

98K

2A

R34

58K

2A

R34

28K

2A

R31

715

0RA

R36

1

10K

A

R35

622

RA

R31

915

0RA

C22

7

100n

A

C23

5

10pA

XXX1

XXX2

R35

18K

2A

R34

68K

2A

R35

38K

2A

D S

G

2N70

02/B

Q3

R33

98K

2A

C23

2

10pA

XXX1

XXX2

R31310KA

R31

840

R2A

R33

58K

2A

R35

822

RA

R33

28K

2A

R36

50R

A

R33

88K

2A

R34

710

KA

XXX1

XXX2

R36

9

33R

A

R32

48K

2A

U5

AT

93LC

46-2

V7

1 2 3 4

8 57 6

CS

CK

DI

DO

VC

C

GN

D

NC

16/8

#

R34

18K

2A

R33

38K

2A

R36

4

33R

A

R32

510

KA

C22

9

100n

A

Hub

link

I/F

CPU I/

F

SM

I/F

PC

I I/F

INT

I/F

EEPRO

M

LAN

I/F

U4A

ICH

4

H5 J3 H3

K1

G5 J4 H4 J5 K2

G2 L1 G4 L2 H2 L3 F5

F4

N1

E5

N2

E3

N3

E4

M5

E2

P1

E1

P2

D3

R1

D2

P4 J2 K4

M4

N4

C1

E6

A7

B7

D6

B1

A2

B3

C7

B6

P5

M3

F1 L5 F2

F3

G1 L4 U5

M2

K5

W2

B5

A6

E8

C5

W6

AC

3A

B1

AB

4A

C4

AA

5

Y22

AB

23U

23A

A21

W21

V22

AB

22V

21Y

23U

22U

21W

23V

23

P21

N20

R23

M23

R22

J19

H19

K20

D5

C2

B4

A3

C8

D7

C3

C4

AC

13A

A19

J22

C12

D11

A8

D10

C11

A10

A9

A11

B10

C10

A12

B11

L19

L20

M19

M21

P19

R19

T20

R20

P23

L22

N22

K21

Y5

AD

0A

D1

AD

2A

D3

AD

4A

D5

AD

6A

D7

AD

8A

D9

AD

10A

D11

AD

12A

D13

AD

14A

D15

AD

16A

D17

AD

18A

D19

AD

20A

D21

AD

22A

D23

AD

24A

D25

AD

26A

D27

AD

28A

D29

AD

30A

D31

C/B

E0#

C/B

E1#

C/B

E2#

C/B

E3#

GN

T0#

GN

T1#

GN

T2#

GN

T3#

GN

T4#

RE

Q0#

RE

Q1#

RE

Q2#

RE

Q3#

RE

Q4#

PC

ICLK

DE

VS

EL#

FR

AM

E#

IRD

Y#

TR

DY

#

ST

OP

#

PA

R

PE

RR

#

PC

IRS

T#

PLO

CK

#

SE

RR

#

PM

E#

RE

QA

#/G

PIO

0

RE

Q5#

/RE

QB

#/G

PIO

1

GN

TA

#/G

PIO

16

GN

T5#

/GN

TB

#/G

PIO

17

INT

RU

DE

R#

SM

LIN

K0

SM

LIN

K1

SM

BD

AT

AS

MB

CLK

GP

IO11

/SM

BA

LER

T#

A20

GA

TE

A20

M#

DP

SLP

#/N

CF

ER

R#

IGN

NE

#IN

IT#

INT

RN

MI

CP

UP

WR

GD

RC

IN#

CP

US

LP#

SM

I#S

TP

CLK

#

HI_

ST

BS

/HI_

ST

BH

I_S

TB

F/H

I_S

TB

#

HIC

OM

P

HIR

EF

HI_

VS

WIN

G

AP

ICC

LKA

PIC

D0

AP

ICD

1

PIR

QA

#P

IRQ

B#

PIR

QC

#P

IRQ

D#

GP

IO2/

PIR

QE

#G

PIO

3/P

IRQ

F#

GP

IO4/

PIR

QG

#G

PIO

5/P

IRQ

H#

IRQ

14IR

Q15

SE

RIR

Q

EE

_SH

CLK

EE

_TO

DO

UT

EE

_TO

DIN

EE

_CS

LAN

_CLO

CK

LAN

_RXD

0LA

N_R

XD1

LAN

_RXD

2

LAN

_TXD

0LA

N_T

XD1

LAN

_TXD

2

LAN

_RS

TS

YN

C

HI0

HI1

HI2

HI3

HI4

HI5

HI6

HI7

HI8

HI9

HI1

0H

I11

LAN

_RS

T#

R31210KA

R31110KA

U6C

74LV

T12

5

10 9

14 78O

E#

IN

VC

C

GN

DO

UT

R31

68K

2A

R36

7

470R

A

R36

022

RA

R34

08K

2A

U6A

74LV

T12

5

1 2

14 73O

E#

IN

VC

C

GN

DO

UT

C23

3

10pA

XXX1

XXX2

U6B

74LV

T12

5

4 5

14 76O

E#

IN

VC

C

GN

DO

UT

R36

6

33R

A

R31

51K

5A

R36

247

0RA

R32

08K

2A

R35

022

RA

R34

310

KA

XXX1

XXX2

R31

08K

2A

R31410KA

R34

98K

2A

R32

30R

A

R35

922

RA

R35

222

RA

R33

48K

2A

Q5

BC

847/

B

3

1

2

R33

08K

2A

R33

78K

2A

R32

18K

2A

C22

8

10nA

C23

0

10pA

XXX1

XXX2

R35

422

RA

R30

91K

5A

R32

68K

2A

C23

4

10pA

XXX1

XXX2

R33

68K

2A

R35

78K

2AXX

X1XX

X2

R36

330

1RA

U6D

74LV

T12

5

13 12

14 711O

E#

IN

VC

C

GN

DO

UT

R34

48K

2A

CK

_IC

H33

12

P_S

ER

R#

24,2

9

P_P

ME

#24

,29

P_R

EQ

#029

P_R

EQ

#129

P_R

EQ

#229

P_R

EQ

#329

P_R

EQ

#424

LM87

INT

#33

P_R

EQ

A#

29

H_I

NT

R6

FW

H_I

NIT

#33

H_A

20M

#6

H_I

NIT

#6

P_R

ST

0#9,

18,3

3

H_N

MI

6

LAN

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231

PW

RG

OO

D6

ST

PC

LK#

6

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031

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US

LP#

6,18

H_S

MI#

6

LAN

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131

H_I

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NE

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TS

YN

C31

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RE

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29

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1#19

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6

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30

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19

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131

H_F

ER

R#

6

INT

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Q14

30

INT

RU

DE

R#

33

INT

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Q15

30

KB

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19

LAN

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031

LAN

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231

SM

BA

LER

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24

XC_L

AN

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18

P_G

NT

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P_G

NT

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P_G

NT

#229

P_G

NT

#329

P_G

NT

#424

P_G

NT

A#

29

H_H

IST

B+

9H

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TB

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INT

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QD

#29

SM

BD

AT

A24

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33

INT

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QA

#26

,29

INT

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QF

#29

INT

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QE

#29

H_H

I[0..1

0]9

SE

RIR

Q18

..20,

29

INT

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QG

#24

INT

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QB

#29

INT

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QH

#

SM

BC

LK24

,29,

33

INT

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QC

#29

P_F

RA

ME

#24

,29

P_A

D[0

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24,2

9

P_D

EV

SE

L#24

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P_T

RD

Y#

24,2

9

P_L

OC

K#

29

P_P

ER

R#

24,2

9

P_S

TO

P#

24,2

9

P_I

RD

Y#

24,2

9

P_P

AR

24,2

9

P_C

BE

#[0.

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24,2

9

V_1

V8

11,1

7,33

,35

V_3

V3

6,8,

12,1

6,17

,19,

20,2

3,26

..29,

33,3

5

V_R

TC

16,1

7

V_1

2V0

23,2

7,29

,32.

.35

GN

D4,

7,8,

10..1

4,16

..35

V_3

V3S

B16

..20,

24,2

5,29

,31.

.33,

35

SP

AR

EP

IN6,

7,9,

11,1

6,24

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SM

BIS

OD

12..1

4

SM

BIS

OC

12..1

4

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

clear CMOS

normal (default)

2-3

1-2

delay RTCRST# for 10-20ms

short for

SAFE MODE

ICH4 Strapping Options

R

C

A B JP

CNO STUFF

OPEN

reserved

NO STUFF

top block swap

NO STUFF

safe mode

EE_DOUT

Signal

Function

no reboot mode

SPKR

Default

AC_SDOUTX

P_GNTA#

B44

4B-W

2.00

ICH

4-LP

C &

IDE

& U

SB

Inte

l (R

) 84

5E In

tera

ctiv

e C

lient

Ref

eren

ce D

esig

n

C16

35M

onda

y, A

pril

21, 2

003

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e

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heet

of

IDE

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IDE

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CK

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IDE

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D12

IDE

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D15

IDE

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DA

CK

#

IDE

_SD

D14

IDE

_PD

IOW

#

IDE

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CS

3#

IDE

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A2

NR

MR

TC

RS

T#

IDE

_SD

A0

IDE

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DR

EQ

IDE

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D11

IDE

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D2

IDE

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A2

IDE

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D14

IDE

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RD

Y

IDE

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D0

IDE

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CS

1#

IDE

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IOR

#

IDE

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D[0

..15]

IDE

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D6

IDE

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A1

IDE

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D13

IDE

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D0

IDE

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D1

IDE

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IOR

#

IDE

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D6

IDE

_PD

D12

IDE

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D5

IDE

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D2

IDE

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D15

IDE

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D3

US

B_R

BIA

S#

IDE

_PD

D3

IDE

_SD

D7

IDE

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CS

1#

IDE

_PD

D7

IDE

_PD

D11

CK

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H66

TP

0

IDE

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D8

IDE

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D9

IDE

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D1

IDE

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D4

IDE

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D10

IDE

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D5

IDE

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DA

CK

#

CK

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H48

US

B_R

BIA

S

IDE

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IOW

#

CK

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SU

SX

IDE

_PD

D10

CLR

RT

CR

ST

#

IDE

_SD

D13

IDE

_SD

D9

IDE

_PD

CS

3#

IDE

_PD

DR

EQ

IDE

_SD

A1

IDE

_SD

A[0

..2]

AC

_SD

OU

TX

AC

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IN0X

L_A

D1

L_A

D3

L_A

D0

L_A

D2

IDE

_PD

A0

SP

KR

RT

CR

ST

#

RT

CX1

RT

CX2

SP

AR

EP

IN

AC

_SD

IN1X

SP

AR

EP

IN

IDE

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RD

Y

SP

AR

EP

IN

SP

AR

EP

IN

SP

AR

EP

INS

PA

RE

PIN

SP

AR

EP

IN

AC

_SD

OU

TY

AC

_SD

IN2X

RT

CX1

RT

CX2

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

V_3

V3

V_3

V3

V_3

V3

V_3

V3

V_3

V3S

B

V_3

V3S

B

V_3

V3S

B

V_R

TC

V_R

TC

V_R

TCB

IAS

V_R

TCB

IAS

V_3

V3

V_3

V3

GN

D

JP2

SM

02/R

AXX

X1XX

X2

1 2

PM

I/F

Inte

l (R

)S

peedS

tep(

R)

tech

nology

AC

'97

I/F

LPC

I/F

US

B I/

F

IDE I/

F

Prim

ary

Sec

onda

ry

CLO

CK I/

F

MIS

C

GP

IO

U4B

ICH

4

R2

AB

2

T3

AC

2

V20

AA

1

AB

6

Y1

AA

6

W18 Y

4

AA

2

W19

Y21

AA

4A

B3

V1

J21

Y20

V19 B

8

C13

D13

A13 D

9

C9

T2

R4

T4

U2

T5

U3

U4

C20

D20

A21

B21

C18

D18

A19

B19

C16

D16

A17

B17

B15

C14

A15

B14

A14

D14

J20

G22

F20

G20

Y13

AB

14

AA

13A

B13

W13

AB

11A

C11

Y10

AA

10A

A7

AB

8Y

8A

A8

AB

9Y

9A

C9

W9

AB

10W

10W

11Y

11

AC

12W

12

AB

12

F21

H20

F23

H22

G23

H21

F22

E23

A23

W16

AA

18

AC

20

Y18

Y14

AA

15

AA

20

AB

21

AC

21

W17

AB

15

AB

16

AB

17

AC

16

AB

19

AA

14

AA

17

Y15

AC

19

W15

AC

22

W14

AC

15

AB

18

Y16

Y17

J23

F19

W7

AC

7A

C6

H23

R3

V4

V5

W3

V2

W1

W4

B13Y

2

T21

Y3

W20

AA

11Y

12

B23

GP

IO6/

AG

PB

US

Y#

TP

0/B

AT

LOW

#

GP

IO21

/C3_

ST

AT

#

GP

IO24

/CLK

RU

N#

NC

/DP

RS

LPV

R

PW

RB

TN

#

PW

RO

K

RI#

RS

MR

ST

#

GP

IO19

/SLP

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SLP

_S3#

SLP

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GP

IO20

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PC

PU

#G

PIO

18/S

TP

PC

I#

SU

SC

LKS

US

_ST

AT

#/LP

CP

D#

TH

RM

#

GP

IO23

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MU

XSE

L

CP

UP

ER

F#/

GP

IO22

VR

MP

WR

GD

/VG

AT

E

AC

_BIT

_CLK

AC

_RS

T#

AC

_SD

IN0

AC

_SD

IN1

AC

_SD

OU

T

AC

_SY

NC

LAD

0/F

WH

0LA

D1/

FW

H1

LAD

2/F

WH

2LA

D3/

FW

H3

LFR

AM

E#/

FW

H4

LDR

Q0#

LDR

Q1#

US

BP

0PU

SB

P0N

US

BP

1PU

SB

P1N

US

BP

2PU

SB

P2N

US

BP

3PU

SB

P3N

US

BP

4PU

SB

P4N

US

BP

5PU

SB

P5N

OC

0#O

C1#

OC

2#O

C3#

OC

4#O

C5#

GP

IO32

GP

IO33

GP

IO34

GP

IO35

PD

CS

1#P

DC

S3#

PD

A0

PD

A1

PD

A2

PD

D0

PD

D1

PD

D2

PD

D3

PD

D4

PD

D5

PD

D6

PD

D7

PD

D8

PD

D9

PD

D10

PD

D11

PD

D12

PD

D13

PD

D14

PD

D15

PD

IOR

#P

DIO

W#

PIO

RD

Y

GP

IO36

GP

IO37

GP

IO38

GP

IO39

GP

IO40

GP

IO41

GP

IO42

GP

IO43

US

BR

BIA

S

SD

D2

SD

IOW

#

SD

A1

SD

IOR

#

SD

D8

SD

D10

SD

A0

SD

CS

1#

SD

A2

SD

D0

SD

D5

SD

D12

SD

D1

SD

D3

SD

DA

CK

#

SD

D7

SD

D14

SD

D11

SIO

RD

Y

SD

D4

SD

CS

3#

SD

D6

SD

D9

SD

DR

EQ

SD

D13

SD

D15

CLK

14C

LK48

RT

CR

ST

#

RT

CX1

RT

CX2

SP

KR

GP

I7G

PI8

GP

I12

GP

I13

GP

IO25

GP

IO27

GP

IO28

AC

_SD

IN2

SLP

_S4#

CLK

66

SY

S_R

ES

ET

#

TH

RM

TR

IP#

PD

DR

EQ

PD

DA

CK

#

US

BR

BIA

S#

R37

633

RA

R37

88K

2A

R37

74K

7A

R38

233

RA

XT2

32K

HZ7

68/Q

T

C23

7

10pA

C23

8

10pA

R37

1 100R

A

JP1

SM

03/R

A

1 32

R37

58K

2A

R37

010

KA

R38

722

RA

R3864K7A

R38

110

KA

XXX2

XXX1

R37

310

MA

R38

81K

AXX

X1XX

X2

R37

933

RA

R37

28K

2A

C23

6

1u/C

A

R37

410

MA

R38

033

RA

US

B_P

0OC

#31

US

B_P

5OC

#32

RS

MR

ST

#18

US

B_P

2OC

#32

RI#

18,2

4

PW

RB

TN

#33

L_D

RQ

#120

TH

ER

M#

33 US

B_P

3OC

#32

US

B_P

1OC

#31

TH

ER

MT

RIP

#6

CK

_AC

BIT

CLK

23,2

9

L_D

RQ

#019

US

B_P

4OC

#32

SY

S_R

ES

ET

#33

AC

_SD

IN1

29

IDE

_PD

IOW

#30

IDE

_PD

DA

CK

#30

IDE

_PD

IOR

#30

IDE

_SD

IOR

#30

IDE

_PD

CS

3#30

IDE

_SD

CS

3#30

IDE

_SD

IOW

#30

IDE

_SD

CS

1#30

IDE

_SD

DA

CK

#30

IDE

_PD

CS

1#30

US

B_P

WR

2EN

A#

32U

SB

_PW

R3E

NA

#32

AM

P_S

HD

N23

FW

H_W

P#

33F

WH

_TB

L#33

IDE

_SIO

RD

Y30

CK

_IC

H48

12

IDE

_PIO

RD

Y30

CK

_IC

H66

12

IDE

_SD

DR

EQ

30

IDE

_PD

DR

EQ

30

CK

_14M

12,1

9,20

,27

RIS

ER

_ID

129

RIS

ER

_ID

229

P_P

RS

NT

1#29

P_P

RS

NT

2#29

MP

CI_

AC

T#

29

IDE

_PP

DIA

G#

30ID

E_S

PD

IAG

#30

LPC

PD

#19

,20

SLP

_S5#

18

SLP

_S3#

18,3

1,32

AC

_SD

OU

T23

,29

CK

_32K

SU

S18

,19

AC

_SY

NC

23,2

9

XC_G

PIO

418

L_F

RA

ME

#18

..20,

33

SP

KR

23,3

3

SLP

_S4#

18

IDE

_PD

D[0

..15]

30

IDE

_SD

A[0

..2]

30

IDE

_SD

D[0

..15]

30

IDE

_PD

A[0

..2]

30

US

B_P

0-31

US

B_P

1+31

US

B_P

2-32

US

B_P

5-32

US

B_P

0+31

US

B_P

4-32

US

B_P

1-31

US

B_P

3-32

US

B_P

4+32

US

B_P

2+32

US

B_P

3+32

US

B_P

5+32

L_A

D[0

..3]

18..2

0,33

NO

GO

29

V_3

V3

6,8,

12,1

5,17

,19,

20,2

3,26

..29,

33,3

5

V_3

V3S

B15

,17.

.20,

24,2

5,29

,31.

.33,

35

V_R

TC

15,1

7

V_R

TC

BIA

S17

GN

D4,

7,8,

10..1

5,17

..35

SP

AR

EP

IN6,

7,9,

11,1

5,24

..27

LAN

0_E

NA

31

SIO

1_P

ME

#20

SIO

0_P

ME

#19

XC_G

PIO

118

XC_G

PIO

218

PW

RG

D_I

CH

18 VR

MP

WR

GD

_IC

H18

XC_G

PIO

318

AC

_RS

T#

23,2

9

AC

_SD

IN2

23

SIO

1_S

MI#

20

SIO

0_S

MI#

19

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Battery circuitry for RTC and CMOS

B44

4B-W

2.00

INT

EL

ICH

4 -

03Inte

l (R

) 84

5E In

tera

ctiv

e C

lient

Ref

eren

ce D

esig

n

C17

35M

onda

y, A

pril

21, 2

003

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

eS

heet

of

V_B

AT

X

V_5

V0R

EF

V_R

TC

BIA

SX

V_B

AT

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

V_1

V5

V_1

V5

V_1

V5S

B

V_1

V5S

B

V_1

V8

V_1

V8

V_3

V3

V_3

V3

V_3

V3

V_3

V3S

B

V_3

V3S

B

V_3

V3S

B

V_5

V0

V_5

V0

V_5

V0S

B

V_5

V0S

B

V_C

OR

E

V_C

OR

E

V_R

TC

V_R

TC

V_R

TC

V_R

TCB

IAS

V_R

TCB

IAS

V_R

TCB

IAS

GN

D

V_3

V3

V_1

V5

GN

DG

ND

GN

D

C24

7

100n

A

+C

252

22u/

TA

C25

4

100n

A

D1

BA

T54

C

12

3

R38

91K

A

+C

270

4u7/

TA

R39

11K

A

C26

6

100n

A

C28

6

100n

A

C27

6

100n

A

C25

3

100n

A

D2

BA

T54

C

12

3

+

BA

T1

SM

02/B

A

C27

7

100n

A

C25

6

100n

A

C25

8

100n

A

C25

7

100n

A

C24

3

47nA

C27

5

100n

A

C24

5

100n

A

C74

0

10nA

+C

282

22u/

TA

C24

6

100n

A

C24

1

1u/C

A

C27

1

100n

A

C24

0

1u/C

A

C25

5

100n

A

C26

7

100n

A

C29

2

100n

A

R39

01K

A

+C

244

22u/

TA

C23

9

100n

A

U4C

ICH

4

A1

A16

A18

A20

A22

A4

AA

12A

A16

AA

22A

A3

AA

9A

B20

AB

7A

C1

AC

10A

C14

AC

18A

C23

AC

5B

12B

16B

18B

20B

22B

9C

15C

17C

19C

21C

23C

6D

1D

12D

15D

17D

19D

21D

23D

4D

8D

22E

10E

14E

16E

17E

18E

19E

21E

22F

8G

19G

21G

3G

6H

1J6K

11K

13K

19K

23K

3L1

0L1

1L1

2L1

3L1

4L2

1M

1M

11M

12M

13M

20M

22N

10N

11N

12N

13N

14N

19N

21N

23N

5P

11P

13P

20P

22P

3R

18R

21R

5T

1T

19T

23U

20V

15V

17V

3W

22W

5W

8Y

19Y

7

Y6

F6

F7

C22

AB

5

E7

V6

E15

E12

E13

E20

F14

G18R

6T

6U

6

K10

K12

K18

K22

P10

T18

U19

V14

K14V

7V

8V

9

E11

F10

F15

F16

F17

F18

AA

23P

14U

18L23

M14

P18

T22A

5A

C17

AC

8B

2H

18H6J1J18

K6

M10

P12P

6U

1V

10V

16V

18E9

F9

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VS

SV

SS

VB

IAS

VC

CLA

N1V

5/V

CC

SU

S1V

5V

CC

LAN

1V5/

VC

CS

US

1V5

VC

CP

LL

VC

CR

TC

VC

C5R

EF

VC

C5R

EF

VC

C5R

EF

SU

S

VC

CS

US

1V5

VC

CS

US

1V5

VC

CS

US

1V5

VC

CS

US

1V5

VC

CS

US

1V5

VC

CS

US

1V5

VC

CS

US

1V5

VC

CS

US

1V5

VC

C1V

5V

CC

1V5

VC

C1V

5V

CC

1V5

VC

C1V

5V

CC

1V5

VC

C1V

5V

CC

1V5

VC

CS

US

3V3

VC

CS

US

3V3

VC

CS

US

3V3

VC

CS

US

3V3

VC

CS

US

3V3

VC

CS

US

3V3

VC

CS

US

3V3

VC

CS

US

3V3

VC

CS

US

3V3

VC

CS

US

3V3

VC

C_C

PU

IOV

CC

_CP

UIO

VC

C_C

PU

IO

VC

CH

IV

CC

HI

VC

CH

IV

CC

HI

VC

C3V

3V

CC

3V3

VC

C3V

3V

CC

3V3

VC

C3V

3V

CC

3V3

VC

C3V

3V

CC

3V3

VC

C3V

3V

CC

3V3

VC

C3V

3V

CC

3V3

VC

C3V

3V

CC

3V3

VC

C3V

3V

CC

3V3

VC

CLA

N3V

3/V

CC

SU

S3V

3V

CC

LAN

3V3/

VC

CS

US

3V3

+C

265

4u7/

TA

+C

274

22u/

TA

+C

251

22u/

TA

C28

5

100n

A

C24

2

100n

A

C28

4

100n

A

C25

9

100n

A

V_R

TC

BIA

S16

V_R

TC

15,1

6V

_CO

RE

4,6.

.8,1

1,33

,35

V_5

V0

19..2

1,23

,25.

.27,

29..3

5V

_5V

0SB

19,2

1,22

,31.

.35

V_3

V3

6,8,

12,1

5,16

,19,

20,2

3,26

..29,

33,3

5V

_3V

3SB

15,1

6,18

..20,

24,2

5,29

,31.

.33,

35

V_1

V8

11,1

5,33

,35

V_1

V5

10,1

1,28

,33,

34V

_1V

5SB

35

GN

D4,

7,8,

10..1

6,18

..35

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

SET = Intel

Pentium 4

Processor-M

HW REV 2

SW REV 0

B44

4B-W

2.00

GLU

E L

OG

IC

Inte

l (R

) 84

5E In

tera

ctiv

e C

lient

Ref

eren

ce D

esig

n

C18

35M

onda

y, A

pril

21, 2

003

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

eS

heet

of

DP

SLP

DP

SLP

X

CP

US

LPX#

CP

US

LP

7SE

G0A

X

XC_C

K1

7SE

G0D

P

7SE

G0D

7SE

G1D

X

VID

0

7SE

G1B

X

7SE

G0A

7SE

G1C

X

7SE

G0E

X

DP

SLP

7SE

G1G

X

7SE

G0C

7SE

G0C

X

PO

RT

_EN

7SE

G0F

PW

MV

ID0

XCT

MS

7SE

G1G

7SE

G0D

PX

7SE

G1A

L_A

D2

7SE

G0D

X

PW

MV

ID4

L_A

D3

7SE

G0B

X

7SE

G0F

X

XCT

DI

7SE

G0G

XCT

CK

7SE

G1F

VID

1

7SE

G1F

X

XCT

DO

7SE

G0E

XC_C

K0

7SE

G1E

7SE

G1C

7SE

G1D

PX

PW

MV

ID1

7SE

G0G

X

7SE

G0B

VID

4

7SE

G1D

P

L_A

D0

PW

MV

ID3

PW

MV

ID2

7SE

G1A

X

VID

2

7SE

G1D

VID

3

CP

US

LP

7SE

G1B

L_A

D1

7SE

G1E

X

NW

_MO

BIL

E#

SW

_RE

V2

SW

_RE

V1

SW

_RE

V0

DE

LAY

3V3

GN

D

GN

D

GN

D

V_3

V3S

B

V_3

V3

V_3

V3S

B

V_3

V3S

B

GN

D

V_3

V3S

B

GN

D

GN

D

GN

D

V_3

V3S

B

V_3

V3S

B

V_3

V3S

B

GN

D

V_3

V3S

B

V_3

V3S

B

V_3

V3S

B

GN

D

GN

D

GN

DV

_3V

3SB

V_3

V3S

B

GN

D

V_3

V3S

B

GN

D

GN

D

Q6

BC

847/

B

3

1

2

R40

210

KA

R42

415

0RA

R4070RA

R42

315

0RA

C29

3

100n

A

R405 10KA

U7

XCR

3128

XL

18 343 39 51 66 82 91 26 38 43 59748695114 157362 72 71 70 69 68 67 65 64 63 75 76 77 78 79 80 81 83 84 85 61 60 58 57 56 55 54 53 5290898887 40 41 42 44 45 46 47 48 49 50

2 1 100

99 98 97 96 94 93 92 5 6 7 8 9 12 13 14 37 36 35 33 32 31 30 29 28 27 16 17 19 20 21 22 23 24 2510

VC

C2

VC

C3

VC

C1

VC

C4

VC

C5

VC

C6

VC

C7

VC

C8

GN

D1

GN

D2

GN

D3

GN

D4

GN

D5

GN

D6

GN

D7

PO

RT

_EN

/PE

TD

I/F1

TM

S/H

1

TD

O/A

1T

CK

/C1

A2

A3

A4

A5

A6

A10

A12

A13

A14

B0

B1

B2

B3

B4

B5

B6

B10

B11

B12

C2

C3

C5

C6

C10

C11

C12

C13

C14

CLK

0/IN

0C

LK1/

IN1

CLK

2/IN

2C

LK3/

IN3

D1

D2

D3

D4

D5

D6

D10

D11

D12

D13

E0

E1

E2

E3

E4

E5

E6

E12

E13

E14 F

2F

3F

4F

5F

6

F13

F14

F15 G

1G

2G

3G

4G

5G

6G

10G

11G

12G

13 H2

H3

H5

H6

H10

H11

H12

H13

H14

F10

U8

TD

SR

1150

7 6 4 2 1 10 9 5

3 8

A B C D E F G DP

AN

1A

N2

R41

115

0RA

R39

3

470R

A

Q7

BC

847/

B

3

1

2

R76

010

KA

R39

4

470R

A

R39

910

KA

JP3

SM

02/R

AXX

X1XX

X2

1 2

R39

810

KA

R39

247

0RA

R40

010

KA

R41

815

0RA

U9

TD

SR

1150

7 6 4 2 1 10 9 5

3 8

A B C D E F G DP

AN

1A

N2

R41

915

0RA

R41

215

0RA

C29

5

100n

A

+C

741

4u7/

TA

R4080RA

R41

615

0RA

R41

515

0RA

C29

7

100n

A

R4090RA

R40

610

KA

R41

015

0RA

R41

415

0RA

R39

510

KA

R41

715

0RA

R40

110

KA

CN

4

SM

09/R

A

1 234

56 7

89

VC

C

GN

D

NC

1T

CK

NC

2T

DO

TD

IN

C3

TM

S

C29

4

100n

A

R39

710

KA

R42

115

0RA

R76

810

KA

R41

315

0RA

R42

015

0RA

R403 10KA

R42

215

0RA

R42

515

0RA

C29

6

100n

A

R39

610

KA

R404 10KA

CP

US

LP#

6,15

DP

SLP

#7

V_3

V3

6,8,

12,1

5..1

7,19

,20,

23,2

6..2

9,33

,35

GN

D4,

7,8,

10..1

7,19

..35

V_3

V3S

B15

..17,

19,2

0,24

,25,

29,3

1..3

3,35

SLP

_S4#

16CK

_32K

SU

S16

,19

SLP

_S3#

16,3

1,32

XC_G

PIO

316

P_R

ST

0#9,

15,3

3 PC

I_S

TO

P#

12

PG

OO

D40

8#12

L_F

RA

ME

#16

,19,

20,3

3

CK

_CP

LD12

PW

RD

WN

#12

SK

TO

CC

#6

SLP

_S5#

16

RS

MR

ST

#16P

WM

VID

[0..4

]35

L_A

D[0

..3]

16,1

9,20

,33

VID

[0..4

]7,

33

RI#

16,2

4

SE

RIR

Q15

,19,

20,2

9

CLK

RU

N#

20,2

4,29

XC_L

AN

0RS

T#

15

CP

U_S

TO

P#

12

PW

RO

K_V

RM

35P

WR

OK

_AT

X35

VR

MP

WR

GD

_IC

H16

PW

RG

D_I

CH

16V

RM

OU

TE

N35

VID

PW

RG

D35

PG

_VD

DR

34P

G_V

1V5

34

EN

_VD

DR

34E

N_V

1V5

34

SD

_DD

RV

TT

#34

ITP

_DB

R#

7,8

EN

_1V

2VID

35

XC_G

PIO

216

XC_G

PIO

116

XC_G

PIO

416

PS

_ON

35

EN

_DD

RS

UP

#34

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

I/O base

address at

0x02E

KEY

IR PORT

GAME PORT/MIDI

B44

4B-W

2.00

SIO

0-LP

C47

M10

7

Inte

l (R

) 84

5E In

tera

ctiv

e C

lient

Ref

eren

ce D

esig

n

C19

35M

onda

y, A

pril

21, 2

003

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

eS

heet

of

L_A

D0

L_A

D3

L_A

D2

SY

SO

PT

0

L_A

D1

LP_D

[0..7

]

LP_D

0

V_I

R

XJ2Y

XJ2X

XJ1Y

XJ1X

J1X

J1Y

J2X

J2Y

J2B

2J2

B1

J2B

1

J2B

2J2

X

J2Y

LP_D

1LP

_D2

LP_D

3LP

_D4

LP_D

5LP

_D6

LP_D

7

IRR

X_IR

IRR

X_IR

IRT

X_IR

MID

I_O

UT

XM

IDI_

INX

MID

I_O

UT

MID

I_IN

MID

I_O

UT

V_G

AM

E

IRT

X_IR

GN

D_I

R

J1B

1

J1X

J1B

1

J1B

2

J1B

2

J1Y

MID

I_IN

V_G

AM

EF

GN

D

GN

D

GN

DG

ND

GN

D

GN

D GN

D

GN

D

GN

D

V_3

V3

V_3

V3

V_3

V3S

B

V_3

V3S

B

V_3

V3S

B

V_5

V0

V_5

V0

V_5

V0

V_5

V0

V_5

V0

V_5

V0S

B

V_5

V0S

B

GN

DG

ND

F1

SM

D07

5-2

12

R42

8

1KA

C30

8

47pA

+C

299

4u7/

TA

+C

304

4u7/

TC

R43

722

0RA

+C

313

4u7/

TC

C30

9

10nA

C30

0

100n

A

R43

12K

A

R43

5

4K7A

R438 2KA

U10

LPC

47M

107

3160

7

76

28302725 242629 19

9190888786898584 95 96 100

97 98 99 92 94 15 13 14 16 4 3 5 8 9 11 10 12 1 283 82 66 67 80 81 77 79 787574737271706968

63

62 61

17 23222120 48 4950 5152 5455 5657 5859 632 33 34 3536 37 38 39

40

41

424345 46 4764

18

536593

44

GNDGND

GND

GND

GP

IO43

/DD

RC

SE

R_I

RQ

LPC

PD

#

LDR

Q#

LFR

AM

E#

PC

I_R

ES

ET

#

PC

I_C

LOC

K

CLO

CK

I

DC

D1#

RI1

#C

TS

1#S

YS

OP

/RT

S1#

DS

R1#

DT

R1#

TXD

1R

XD1

GP

IO52

/IRR

X/R

XD2

GP

IO53

/IRT

X/T

XD2

GP

IO57

/DT

R2#

GP

IO54

/DS

R2#

GP

IO55

/RT

S2#

GP

IO56

/CT

S2#

GP

IO50

/RI2

#G

PIO

51/D

CD

2#

WP

#IN

DE

X#T

RA

K0#

RD

AT

A#

DS

KC

HG

#M

TR

0#

DS

0#

DIR

#S

TE

P#

WG

AT

E#

WD

AT

A#

HD

SE

L#G

PIO

40/D

RV

DE

N0

GP

IO41

/DR

VD

EN

1

ST

B#

AF

D#

INIT

#S

LCT

IN#

AC

K#

ER

R#

SLC

TB

US

YP

E

PD

7P

D6

PD

5P

D4

PD

3P

D2

PD

1P

D0

KB

DR

ST

#/G

PIO

36

GP

35/IR

TX2

GP

34/IR

RX2

IO_P

ME

#/G

PIO

42

LAD

3LA

D2

LAD

1LA

D0

LED

1/G

PIO

60LE

D2/

GP

IO61

IO_S

MI#

/GP

IO27

FA

N_T

AC

H2/

GP

IO30

FA

N_T

AC

H1/

GP

IO31

FA

N2/

GP

IO32

FA

N1/

GP

IO33

KD

AT

KC

LOC

K

MD

AT

MC

LOC

K

CLO

CK

I32

J1B

1/G

PIO

10J1

B2/

GP

IO11

J2B

1/G

PIO

12J2

B2/

GP

IO13

J1X/

GP

IO14

J1Y

/GP

IO15

J2X/

GP

IO16

J2Y

/GP

IO17

AGND

GP

IO20

/P17

GP

IO21

/P16

/DS

1#

GP

IO22

/P12

/MT

R1#

GP

IO24

/SY

SO

PT

MID

I_IN

/GP

IO25

MID

I_O

UT

/GP

IO26

A20

M/G

PIO

37

VTR

VCCVCCVCC

VREF

C31

1

10nA

R43

22K

A

C30

5

47pA

C30

6

47pA

C31

2

10nA

C30

1

100n

A

C31

0

10nA

C30

2

100n

A

R42

9

1KA

C29

8

100n

A

R43

0

1KA

R42

610

KA

FB

5B

LM21

B60

1S

C30

3

100n

A

R43

622

0RA

CN

6

SM

16/W

A

12

34

56

78

910

1112

1314

1516

R43

42K

A

FB

7B

LM21

B60

1S

CN

5

SM

06/S

AXX

X1XX

X2

12

34

56

R439 2KA

R43

32K

A

FB

6B

LM21

B60

1S

C30

7

47pA

R42

7

1KA

P_R

ST

1#15

,20,

24,2

6

FA

N2_

SE

NS

E33

CK

_14M

12,1

6,20

,27

CK

_LP

C0

12

CK

_32K

SU

S16

,18

FA

N1_

SE

NS

E33

LPC

PD

#16

,20

SP

2_T

XD21

SP

1_R

TS

#21

LP_A

FD

#21

F_D

IR#

30

SP

1_T

XD21

SP

2_D

TR

#21

F_H

DS

EL#

30

LP_S

LIN

#21

F_S

TE

P#

30

SP

1_D

TR

#21

F_D

RV

DE

N0

30

F_D

S1#

30F

_DS

0#30

LP_S

TB

#21

F_W

DA

TA

#30

F_M

TR

0#30

F_D

RV

DE

N1

30

LP_I

NIT

#21

F_M

TR

1#30

F_W

GA

TE

#30

SP

2_R

TS

#21

LP_E

RR

#21

SP

1_C

TS

#21

F_R

DA

TA

#30

F_W

P#

30

SP

2_R

XD21

SP

2_R

I#21

F_T

RA

K0#

30

SP

2_D

SR

#21

LP_B

US

Y21

SP

1_D

CD

#21

LP_P

E21

F_D

SK

CH

G#

30

SP

1_R

XD21

F_I

ND

EX#

30

SP

1_R

I#21

SP

2_D

CD

#21

LP_A

CK

#21

SP

2_C

TS

#21

SP

1_D

SR

#21

KB

_RS

T#

15

SIO

0_S

MI#

16

A20

GA

TE

15

FA

N2_

PW

M33

L_D

RQ

#016

PW

M_B

L27

SIO

0_P

ME

#16

LP_D

[0..7

]21

LP_S

LCT

21

KB

_CLK

22K

B_D

AT

22

MS

_DA

T22

L_F

RA

ME

#16

,18,

20,3

3

MS

_CLK

22

L_A

D[0

..3]

16,1

8,20

,33

SE

RIR

Q15

,18,

20,2

9

V_3

V3S

B15

..18,

20,2

4,25

,29,

31..3

3,35

GN

D4,

7,8,

10..1

8,20

..35V

_3V

36,

8,12

,15.

.17,

20,2

3,26

..29,

33,3

5

V_5

V0S

B17

,21,

22,3

1..3

5V

_5V

017

,20,

21,2

3,25

..27,

29..3

5

PW

R_L

ED

_GR

N33

PW

R_L

ED

_YE

L33

SP

1_S

D#

21

SP

2_S

D#

21

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

FIR

PORT

KEY

I/O base address

at 0x04E

B44

4B-W

2.00

SIO

1-LP

C47

N22

7

Inte

l (R

) 84

5E In

tera

ctiv

e C

lient

Ref

eren

ce D

esig

n

C20

35M

onda

y, A

pril

21, 2

003

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

eS

heet

of

IRR

X_F

IR

IRT

X_F

IR

V_F

IRL_

AD

2

IRR

X_F

IR

L_A

D0

L_A

D3

L_A

D1

IRT

X1_F

IR

MO

DE

_IR

RX_

FIR

SY

SO

PT

1

GN

DG

ND

GN

D

GN

D

GN

D

GN

D

V_3

V3

V_3

V3

V_3

V3S

B

V_3

V3S

B

V_3

V3S

B

V_5

V0

V_5

V0

+C

319

4u7/

TC

C31

4

100n

A

R44

110

0KA

CN

7

SM

06/S

A

12

34

56

U11

LPC

47N

22753

31

65

60

93

7

76

28 302725 242629 19

18

9190888786898584 95 96 100

97 98 99 92 94 15 13 14 16 4 3 5 8 9 11 10 12 1 283 82 66 67 80 81 77 79 7875 74 73 72 71 70 69 68636261

17 23222120 4849 50 51 52 54 55 56 57 58 59 6 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 4764

VCC

GND

VCC

GND

VCC

GND

GND

CLK

RU

N#

SE

R_I

RQ

LPC

PD

#

LDR

Q#

LFR

AM

E#

PC

I_R

ES

ET

#

PC

I_C

LOC

K

CLO

CK

I

VCCSB

DC

D1#

RI1

#C

TS

1#R

TS

1#D

SR

1#D

TR

1#T

XD1

RXD

1

RXD

2T

XD2

DT

R2#

DS

R2#

RT

S2#

CT

S2#

RI2

#D

CD

2#

WP

#IN

DE

X#T

RA

K0#

RD

AT

A#

DS

KC

HG

#M

TR

0#

DS

0#

DIR

#S

TE

P#

WG

AT

E#

WD

AT

A#

HD

SE

L#D

RV

DE

N0

DR

VD

EN

1

DS

0#/S

TB

#D

RV

DE

N0#

/AF

D#

DIR

#/IN

IT#

ST

EP

#/S

LCT

IN#

DS

1#/A

CK

#H

DS

EL#

/ER

R#

WG

AT

E#/

SLC

TM

TR

1#/B

US

YW

RD

AT

A#/

PE

PD

7M

TR

0#/P

D6

PD

5D

SK

CH

G#/

PD

4R

DA

TA

#/P

D3

WP

#/P

D2

TR

K0#

/PD

1IN

DE

X#/P

D0

IRM

OD

E/IR

RX3

IRT

X2IR

RX2

IO_P

ME

#

LAD

3LA

D2

LAD

1LA

D0

GP

IO10

GP

IO11

/SY

SO

PT

GP

IO12

/IO_S

MI#

GP

IO13

/IRQ

IN1

GP

IO14

/IRQ

IN2

GP

IO15

GP

IO16

GP

IO17

GP

IO20

GP

IO21

GP

IO22

GP

IO24

GP

IO30

GP

IO31

GP

IO32

GP

IO33

GP

IO34

GP

IO35

GP

IO36

GP

IO37

GP

IO40

GP

IO41

GP

IO42

GP

IO43

GP

IO44

GP

IO45

GP

IO46

GP

IO47

GP

IO23

/FD

C_P

P

+C

315

4u7/

TA

C31

6

100n

A

C31

7

100n

A

R44

210

KA

C32

0

100n

A

R44

382

RA

R44

44K

7A

R44

010

0KA

FB

8B

LM21

B60

1S

C31

8

100n

A

CK

_14M

12,1

6,19

,27

P_R

ST

1#15

,19,

24,2

6

CK

_LP

C1

12

LPC

PD

#16

,19

SP

4_D

TR

#22

SP

3_R

TS

#22

SP

3_T

XD22

SP

4_R

TS

#22

SP

3_D

TR

#22

SP

4_T

XD22

SP

4_D

CD

#22

SP

3_D

CD

#22

SP

3_C

TS

#22

SP

4_R

XD22

SP

3_R

XD22

SP

4_D

SR

#22

SP

3_R

I#22

SP

4_R

I#22

SP

3_D

SR

#22

SP

4_C

TS

#22

SE

RIR

Q15

,18,

19,2

9C

LKR

UN

#18

,24,

29

L_D

RQ

#116

SIO

1_P

ME

#16

SIO

1_S

MI#

16

L_F

RA

ME

#16

,18,

19,3

3

L_A

D[0

..3]

16,1

8,19

,33

V_5

V0

17,1

9,21

,23,

25..2

7,29

..35

V_3

V3S

B15

..19,

24,2

5,29

,31.

.33,

35V

_3V

36,

8,12

,15.

.17,

19,2

3,26

..29,

33,3

5

GN

D4,

7,8,

10..1

9,21

..35

SP

3_S

D#

22S

P4_

SD

#22

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

LPT

COM2

COM1

B44

4B-W

2.00

CO

NN

CO

M1/

CO

M2/

LPT

Inte

l (R

) 84

5E In

tera

ctiv

e C

lient

Ref

eren

ce D

esig

n

C21

35M

onda

y, A

pril

21, 2

003

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

eS

heet

of

SP

1_D

CD

1#

V_S

P2V

-

V_S

P1C

1+

V_S

P1V

-V

_SP

1V+

V_S

P2C

2+

V_S

P2C

1+

V_S

P2V

+

SP

1_T

XD1

V_S

P1C

1-

V_S

P2C

1-

V_S

P1C

2+

SP

1_C

TS

1#

V_S

P1C

2-

SP

1_R

I2#

SP

2_R

I1#

SP

1_R

TS

2#S

P1_

DS

R1#

V_S

P2C

2-

GN

D_L

PT

SP

1_R

I1#

SP

1_D

TR

1#

SP

1_D

CD

2#

SP

1_T

XD2

SP

1_R

XD1

SP

1_R

TS

1#

SP

1_R

XD2

SP

1_E

N

SP

2_E

N

V_5

V0L

PT

SP

2_D

CD

1#S

P2_

CT

S2#

SP

2_C

TS

1#S

P2_

DC

D2#

SP

2_R

TS

1#S

P2_

RT

S2#

SP

2_D

TR

1#S

P2_

DS

R1#

SP

2_T

XD1

SP

2_D

SR

2#

SP

2_T

XD2

SP

2_D

TR

2#

SP

2_R

XD2

SP

2_R

XD1

SP

2_R

I2#

LP_D

0

LP_D

[0..7

]

LP_D

X7

LP_D

X0

LP_D

X3LP

_DX2

LP_D

X6

LP_S

TB

X#

LP_D

X1

LP_D

X4LP

_DX5

LP_S

TB

OU

T#

LP_D

OU

T0

LP_D

1LP

_D2

LP_D

3LP

_D4

LP_D

5LP

_D6

LP_D

7

LP_P

EX

LP_S

LCT

XLP

_AF

DX#

LP_S

LIN

X#

LP_B

US

YX

LP_I

NIT

X#LP

_ER

RX#

LP_A

CK

X#

LP_D

OU

T1

LP_D

OU

T2

LP_D

OU

T3

LP_D

OU

T4

LP_D

OU

T5

LP_D

OU

T6

LP_D

OU

T7

SP

1_D

SR

2#

SP

1_C

TS

2#

SP

1_D

TR

2#

GN

D

GN

D

GN

D

GN

D

GN

D

V_5

V0 V

_5V

0

V_5

V0S

B

V_5

V0S

B

V_5

V0S

B

V_5

V0S

B

V_5

V0S

B

SH

IELD

SH

IELD

SH

IELD

SH

IELD

GN

D

GN

D

GN

D

SH

IELD

GN

D

GN

D

GN

D

GN

D

GN

D

C32

2

100n

A

C33

6

100n

A

FB

45B

LM11

A60

1SPT

U12

MA

X213

EC

AI

11 13

12 14

22 6 7 8 20 5 26 19

241017

15 16 2523 3 2 9 1 4 27 18 2821

VC

C

V+

C1+ C1-

RXO

UT

4D

RIN

2D

RIN

1R

XOU

T1

DR

IN3

RXO

UT

2R

XOU

T3

RXO

UT

5

EN

GN

D

V-

C2+ C2-

SD

#

RXI

N4

DR

OU

T2

DR

OU

T1

RXI

N1

DR

OU

T3

RXI

N2

RXI

N3

RXI

N5

DR

OU

T4

DR

IN4

FB

44B

LM11

A60

1SPT

FB

33B

LM11

A60

1SPT

FB

N4A

BLA

3216

A60

11

2

C354220pA

CA1C 470pX45 6

C353220pA

C356220pA

CA1A 470pX41 2

FB

N3A

BLA

3216

A60

11

2

C361220pA

C358220pA

C362220pA

C32

3

100n

A

R44

510

KA

C360220pA

FB

N4D

BLA

3216

A60

17

8

CA1D 470pX47 8

C359220pA

FB

41B

LM11

A60

1SPT

FB

N3D

BLA

3216

A60

17

8

FB

N1A

BLA

3216

A60

11

2

C350220pA

FB

30B

LM11

A60

1SPT

CN

8B

SW

47/X

A

B2

B3

B4

B6

B7

B8

B9

B5

B1

RX2

TX2

DT

R2#

DS

R2#

RT

S2#

CT

S2#

RI2

#

GN

D2

DC

D2#

FB

31B

LM11

A60

1SPT

FB

N3C

BLA

3216

A60

15

6

FB

35B

LM11

A60

1SPT

R77

6

10K

A

C33

8

100n

A

CN

8C

SW

47/X

A

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C11

C12

C13

C14

C16

C15

C17

C18

C19

C20

C21

C22

C23

C24

C25

DR

1D

R2

DR

3D

R4

ST

RB

#

D0

D1

D2

D3

D4

D5

D6

D7

AC

K#

BU

SY

PE

SLC

TA

FD

#IN

IT#

ER

R#

SLC

TIN

#

GN

D2

GN

D3

GN

D4

GN

D5

GN

D6

GN

D7

GN

D8

GN

D9

DR

1D

R2

DR

3D

R4

C352220pA

D26

BA

T54

FB

N2C

BLA

3216

A60

15

6

C351220pA

CF

1P

AC

_LP

T12

84

281

227

1512108

26 20 22

314 13 11 9 7 6 5 4

16 17 18 19 21 23 24 25

AFD#INIT#

SLIN#ERR#

ACK#BUSYPESLCTS

TB

OU

T#

VC

CG

ND

ST

BIN

#

D7I

ND

6IN

D5I

ND

4IN

D3I

ND

2IN

D1I

ND

0IN

D7O

UT

D6O

UT

D5O

UT

D4O

UT

D3O

UT

D2O

UT

D1O

UT

D0O

UT

CA4D 470pX47 8

FB

N3B

BLA

3216

A60

13

4

C33

5

100n

A

FB

42B

LM11

A60

1SPT

CA2C 470pX45 6

FB

N1D

BLA

3216

A60

17

8

C347220pA

FB

34B

LM11

A60

1SPT

C349220pA

C33

4

100n

A

FB

N2A

BLA

3216

A60

11

2

CA3D 470pX47 8

CA4B 470pX43 4

FB

28B

LM11

A60

1SPT

CA2A 470pX41 2

FB

N1B

BLA

3216

A60

13

4

FB

38B

LM11

A60

1SPT

CN

8A

SW

47/X

A

A2

A3

A4

A6

A7

A8

A9

A5

A1

RX1

TX1

DT

R1#

DS

R1#

RT

S1#

CT

S1#

RI1

#

GN

D1

DC

D1#

R77

5

10K

A

FB

N2D

BLA

3216

A60

17

8

CA3A 470pX41 2

CA4A 470pX41 2

R44

610

KA

C363220pA

FB

43B

LM11

A60

1SPT

CA2B 470pX43 4

FB

N1C

BLA

3216

A60

15

6

C33

7

100n

AU

13

MA

X213

EC

AI

11 13

12 14

22 6 7 8 20 5 26 19

241017

15 16 2523 3 2 9 1 4 27 18 2821

VC

C

V+

C1+ C1-

RXO

UT

4D

RIN

2D

RIN

1R

XOU

T1

DR

IN3

RXO

UT

2R

XOU

T3

RXO

UT

5

EN

GN

D

V-

C2+ C2-

SD

#

RXI

N4

DR

OU

T2

DR

OU

T1

RXI

N1

DR

OU

T3

RXI

N2

RXI

N3

RXI

N5

DR

OU

T4

DR

IN4

FB

29B

LM11

A60

1SPT

FB

N2B

BLA

3216

A60

13

4

CA3C 470pX45 6

C32

5

100n

A

CA4C 470pX45 6

FB

N4C

BLA

3216

A60

15

6

FB

32B

LM11

A60

1SPT

CA2D 470pX47 8

FB

39B

LM11

A60

1SPT

C357220pA

FB

40B

LM11

A60

1SPT

FB

36B

LM11

A60

1SPT

CA3B 470pX43 4

C32

1

100n

A

FB

N4B

BLA

3216

A60

13

4

CA1B 470pX43 4

C32

4

100n

A

C355220pA

C348220pA

SP

1_R

TS

#19

SP

2_R

TS

#19

SP

1_D

TR

#19

SP

1_T

XD19

SP

1_S

D#

19

SP

2_D

TR

#19

SP

2_T

XD19

LP_S

TB

#19

LP_I

NIT

#19

LP_A

FD

#19

LP_S

LIN

#19

SP

2_R

XD19

SP

1_R

I#19

SP

1_R

XD19

SP

1_C

TS

#19

SP

2_D

SR

#19

SP

2_R

I#19

SP

1_D

CD

#19

SP

1_D

SR

#19

SP

2_C

TS

#19

SP

2_D

CD

#19

LP_B

US

Y19

LP_E

RR

#19

LP_P

E19

LP_S

LCT

19

LP_A

CK

#19

LP_D

[0..7

]19

V_5

V0S

B17

,19,

22,3

1..3

5

V_5

V0

17,1

9,20

,23,

25..2

7,29

..35

GN

D4,

7,8,

10..2

0,22

..35 S

HIE

LD23

,25,

27,3

1,32

SP

2_S

D#

19

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

COM3

COM4

KBC & MOUSE

B44

4B-W

2.00

CO

NN

CO

M3/

CO

M4/

KB

C

Inte

l (R

) 84

5E In

tera

ctiv

e C

lient

Ref

eren

ce D

esig

n

C22

35M

onda

y, A

pril

21, 2

003

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

eS

heet

of

V_S

P3C

2+

SP

3_D

CD

1#

SP

3_D

TR

1#

V_S

P3C

1-

SP

3_C

TS

1#

V_S

P4C

1-

SP

3_R

I1#

V_S

P4C

2-

V_S

P3V

-

SP

3_T

XD1

SP

3_R

TS

1#

SP

3_R

XD1

V_S

P3C

2-

V_S

P4C

1+

V_S

P4V

+

SP

3_D

SR

1#

V_S

P4V

-V

_SP

4C2+

SP

3_R

I2#

V_S

P3V

+

V_S

P3C

1+

SP

4_E

N

SP

3_R

XD2

SP

3_T

XD2

SP

3_D

TR

2#

SP

3_R

TS

2#S

P3_

CT

S2#

SP

3_D

CD

2#

SP

3_E

N

SP

3_D

SR

2#

SP

4_D

CD

2#

SP

4_T

XD2

SP

4_R

I2#

SP

4_R

XD2

SP

4_R

TS

2#S

P4_

CT

S2#

SP

4_D

TR

2#

MS

_DA

TO

UT

MS

_CLK

OU

TK

B_C

LKO

UT

KB

_DA

TO

UT

SP

4_C

TS

1#

SP

4_T

XD1

SP

4_R

TS

1#

SP

4_R

I1#

SP

4_R

XD1

SP

4_D

CD

1#

SP

4_D

TR

1#S

P4_

DS

R1#

SP

4_D

SR

2#

V_K

BO

UT

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

SH

IELD

GN

D

GN

D

GN

D

V_5

V0S

B

V_5

V0S

B

V_5

V0S

B

V_5

V0S

B

V_5

V0S

B

V_5

V0S

B

V_5

V0S

B

GN

D

GN

D

GN

D

GN

D

GN

D

FB

59B

LM11

A60

1SPT

R4494K7A

R44

710

KA

CN

11

SM

10/S

A

1 2 3 4 5 6 7 8 9 10

1 2 3 4 5 6 7 8 9 10

C371470pA

C382470pA

C373470pA

C375470pA

CN

9

SM

10/W

A

13 5 7

9

2 4 6 8

10

DC

D#

RX

TX

DT

R#

GN

D

DS

R#

RT

S#

CT

S#

RI#

NC

F2

SM

D07

5-2

1 2

FB

56B

LM11

A60

1SPT

FB

48B

LM11

A60

1SPT

C39347pA

XXX1XXX2

R77

3

10K

A

FB

50B

LM11

A60

1SPT

FB

49B

LM11

A60

1SPT

C386470pA

C37

9

100n

A

FB

51B

LM11

A60

1SPT

FB

64B

LM11

A60

1SPT

FB

55B

LM11

A60

1SPT

R4514K7A

FB

47B

LM11

A60

1SPT

C383470pA

FB

65B

LM11

A60

1SPT

FB

57B

LM11

A60

1SPT

FB

52B

LM11

A60

1SPT

C385470pA

C36

6

100n

A

C369470pA

CN

10

SM

10/W

A

13 5 7

9

2 4 6 8

10

DC

D#

RX

TX

DT

R#

GN

D

DS

R#

RT

S#

CT

S#

RI#

NC

C388470pA

C36

4

100n

A

C39447pA

XXX1XXX2

C36

7

100n

A

FB

61B

LM11

A60

1SPT

C39147pA

XXX1XXX2

FB

46B

LM11

A60

1SPT

U15

MA

X213

EC

AI

11 13

12 14

22 6 7 8 20 5 26 19

241017

15 16 2523 3 2 9 1 4 27 18 2821

VC

C

V+

C1+ C1-

RXO

UT

4D

RIN

2D

RIN

1R

XOU

T1

DR

IN3

RXO

UT

2R

XOU

T3

RXO

UT

5

EN

GN

D

V-

C2+ C2-

SD

#

RXI

N4

DR

OU

T2

DR

OU

T1

RXI

N1

DR

OU

T3

RXI

N2

RXI

N3

RXI

N5

DR

OU

T4

DR

IN4

R77

4

10K

A

C370470pA

C387470pA

C372470pA

C36

8

100n

A

C374470pA

C376470pA

FB

66B

LM11

A60

1SPT

FB

62B

LM11

A60

1SPT

R44

810

KA

FB

67B

LM11

A60

1SPT

C389470pA

C38

0

100n

A

R4524K7A

FB

58B

LM11

A60

1SPT

C37

8

100n

A

R4504K7A

FB

53B

LM11

A60

1SPT

C39247pA

XXX1XXX2

C39

0

100n

A

C384470pA

C38

1

100n

A

U14

MA

X213

EC

AI

11 13

12 14

22 6 7 8 20 5 26 19

241017

15 16 2523 3 2 9 1 4 27 18 2821

VC

C

V+

C1+ C1-

RXO

UT

4D

RIN

2D

RIN

1R

XOU

T1

DR

IN3

RXO

UT

2R

XOU

T3

RXO

UT

5

EN

GN

D

V-

C2+ C2-

SD

#

RXI

N4

DR

OU

T2

DR

OU

T1

RXI

N1

DR

OU

T3

RXI

N2

RXI

N3

RXI

N5

DR

OU

T4

DR

IN4

FB

60B

LM11

A60

1SPT

C36

5

100n

A

C37

7

100n

A

SP

4_D

TR

#20

SP

3_D

TR

#20

SP

4_T

XD20

SP

3_T

XD20

SP

4_R

TS

#20

SP

3_R

TS

#20

SP

3_D

CD

#20

SP

4_R

I#20

SP

3_R

I#20

SP

3_D

SR

#20

SP

4_R

XD20

SP

4_D

SR

#20

SP

3_C

TS

#20

SP

4_C

TS

#20

SP

3_R

XD20

SP

4_D

CD

#20

KB

_CLK

19

MS

_DA

T19

KB

_DA

T19

MS

_CLK

19

V_5

V0S

B17

,19,

21,3

1..3

5

GN

D4,

7,8,

10..2

1,23

..35

SH

IELD

21,2

3,25

,27,

31,3

2

SP

3_S

D#

20

SP

4_S

D#

20

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

KEY

RESERVED

5V/100mA for AUDIO CODEC

CD ROM AUDIO

LINE IN

(LIGHT BLUE)

RA=(VOUT/1.216-1) * RB

RA

RB

4.5V/1.5A for AUDIO AMPLIFIER

Note:

Single-ended amplified outputs defined in eATX

replaced by differential outputs (4 times output

power)! DO NOT CONNECT TO GROUNDED SPEAKERS!!

HEADPHONE

OUT (LIME)

AUDIO planar header

MIC (PINK)

planar header <-

AUDIO AMPLIFIER

(2 x 2.2W)

B44

4B-W

2.00

AC

97-A

D18

85

Inte

l (R

) 84

5E In

tera

ctiv

e C

lient

Ref

eren

ce D

esig

n

C23

35M

onda

y, A

pril

21, 2

003

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

eS

heet

of

AU

D_M

IC_I

NA

UD

_MIC

_BIA

SA

UD

_OU

T_R

AU

D_O

UT

_LA

UD

_AM

P_R

+A

UD

_AM

P_L

+

AU

D_R

ET

_L

AU

D_R

ET

_R

AU

D_V

RE

F

AC

XTL_

IN

AC

XTL_

OU

T

CK

_AC

BIT

X

SP

KR

X

AU

D_S

PK

R

AU

D_M

ON

O

AU

D_P

HO

NE

IN

JS0

AU

D_C

DR

_IN

X

AU

D_C

DG

ND

_IN

AU

D_C

DL_

IN

AU

D_C

DR

_IN

AU

D_C

DG

ND

AU

D_C

DR

AU

D_L

INR

_IN

Y

AU

D_L

INL_

INY

AU

D_C

DL

AU

D_L

INL_

INX

AU

D_C

DG

ND

_IN

X

AU

D_C

DL_

INX

AU

D_L

INR

_IN

X

AU

D_L

INR

AU

D_L

INL

ADJ_VAMP

EN

_VA

MP

AU

D_A

MP

_R-

AU

D_A

MP

_L-

AU

D_H

PR

OU

T

AU

D_H

PLO

UT

JS1Y

JS1X

JS1

AU

D_H

PR

AU

D_H

PL

AU

D_O

UT

_RA

UD

_OU

T_L

AU

D_R

ET

_RA

UD

_RE

T_L

AU

D_M

IC_I

N1

AU

D_V

RE

FO

UT

AU

D_M

IC_B

IAS

AU

D_M

IC1

AU

D_M

IC_I

N1X

AU

D_M

IC2

AU

D_M

IC_I

N

AU

D_L

INO

UT

RA

UD

_LIN

OU

TL

CX3D

AU

D_M

IC_I

NX

AU

D_A

MP

_L+

AU

D_H

PIN

AU

D_A

MP

_R+

AU

D_I

NB

-

AU

D_A

MP

_R-

AU

D_A

MP

_L-

AU

D_A

MP

BY

P

AU

D_I

NA

-

AUD_INAX-AUD_INBX-

FILT_R

FILT_L

AFILT2

AU

D_L

INL_

IN

AFILT1

RX3D

AU

D_L

INR

_IN

AU

D_M

ICB

IAS

1

GN

D_A

UD

GN

D_A

UD

GN

D_A

UD

GN

D_A

UD

GN

D_A

UD

GN

D_A

UD

GN

D_A

UD

GN

D_A

UD

GN

D_A

UD

GN

D_A

UD

GN

D_A

UD

GN

D_A

UD

GN

D_A

UD

GN

D_A

UD

GN

D_A

UD

GN

D_A

UD

GN

D_A

UD

GN

D_A

UD

GN

D_A

UD

GN

D_A

UD

GN

D_A

UD

GN

D_A

UD

GN

D_A

UD

GN

D

GN

DG

ND

GN

D

GN

D

GN

DG

ND

GN

D

GN

D

GN

DG

ND

GN

D

GN

DG

ND

GN

D

GN

D

GN

D

GN

D_A

UD

V_1

2V0

V_3

V3

V_3

V3

V_3

V3

V_5

V0

V_5

V0

V_5

VA

UD

V_5

VA

UD

V_5

VA

UD

V_5

VA

UD

V_5

VA

UD

V_A

MP

V_A

MP

V_A

MP

V_A

MP

SH

IELD

SH

IELD

GN

D_A

UD

SH

IELD

GN

D_A

UD

GN

D_A

UD

GN

D_A

UD

SH

IELD

V_3

V3

GN

D

GN

D_A

UD

GN

D_A

UD

GN

D_A

UD

C40

0

100n

AXX

X2

R47

947

KA

XXX2

U16

AD

1885

JST

XXX2

4

1

7

9

38

42

25

264044

43

12 24 2321 22 2018 19 1716 14 15 13

37 36 3541 39

29

30

32

31

33

34

27

28

3 2

11 5 8 10 6 4645 4847

DVSS1

DVDD1

DVSS2

DVDD2

AVDD2

NC

AVDD1

AVSS1AVSS2AVSS3

AVDD3

PC

_BE

EP

LIN

E_I

N_R

LIN

E_I

N_L

MIC

1M

IC2

CD

_R

CD

_LC

D_G

ND

_RE

F

VID

EO

_RV

IDE

O_L

AU

X_L

AU

X_R

PH

ON

E_I

N

MO

NO

_OU

T

LIN

E_O

UT

_RLI

NE

_OU

T_L

HP

_OU

T_R

HP

_OU

T_L

AFILT1

AFILT2

FILT_L

FILT_R

RX3D

CX3D

VREF

VREFOUT

XTL_

OU

T

XTL_

IN

RE

SE

T#

SD

AT

A_O

UT

SD

AT

A_I

NS

YN

CB

IT_C

LK ID1

ID0

JS1

JS0

C41

3

1u/C

AXX

X2

FB

73

BLM

11A

601S

PTXX

X2

C45

4

100n

AXX

X2

R47

14K

7AXX

X2

R47

610

KA

XXX2

FB

69B

LM11

A60

1SPT

XXX2

C42

4

470p

AXX

X2

C44

310

0nA

XXX2

R48

1

18K

AXX

X2

C44

6

100n

AXX

X2

C43

6

100n

AXX

X2

R48

018

KA

XXX2

C44

9

100p

AXX

X2

C40

9 1u/C

AXX

X2

R45

81K

AXX

X2

R46

610

KA

XXX2

R46

1

4K7A

XXX2

+

C4411u/TC XXX2

+C

428

100u

/TA

XXX2

C41

8

100n

AXX

X2

FB

75

BLM

41P

600S

PTXX

X2

CN

12B

SW

15/X

JXX

X29 8 7 6

1

14151617

C40

3

470p

AXX

X2

+

C41

5

1u/T

CXX

X2

R47

40R

AXX

X2

C43

2

100n

AXX

X2

+

C42

6

1u/T

CXX

X2

C41

4

1u/C

AXX

X2

D3

BA

T54

XXX2

R45

9

2KA

XXX2

R46

94K

7AXX

X2

C41

1

470p

AXX

X2

R47

50R

AXX

X2

C44247nA XXX2

R46

54K

7AXX

X2

R48

410

KA

XXX2

R48

7

18K

AXX

X2

R47

047

KA

XXX2

FB

71B

LM11

A60

1SPT

XXX2

+

C42

1 100u

/TA

XXX2

+C

444

100u

/TA

XXX2

C43

7

100n

AXX

X2

C41

9

22pA

XXX2

C40

8 1u/C

AXX

X2

R48

518

KA

XXX2

+C

456

1u/T

CXX

X2

C40

2

470p

AXX

X2

C43

4

100n

AXX

X2

C42

5

100n

AXX

X2

C39

9

100n

AXX

X2

+

C4401u/TC XXX2

C438220pA XXX2

FB

70

BLM

11A

601S

PTXX

X2

FB

72B

LM11

A60

1SPT

XXX2

R46

82K

AXX

X2

C45

8

100n

AXX

X2

R45

7

10K

AXX

X2

CN

13

SM

04/C

EXX

X2

1 2 3 4

+C

435

22u/

TA

XXX2

R46

34K

7AXX

X2

CN

14

SM

14/S

AXX

X2

12

34

56

78

910

1112

1314

R46

7

2KA

XXX2

C40

1 1u/C

AXX

X2

U17

LM48

63M

TEXX

X2

6 8 14 15 13 1 20

27910111219

5 3 16 18

417

INA

-IN

A+

BY

PA

INB

-IN

B+

SH

DN

HP

-IN

GNDGNDGNDGNDGNDGNDGND

OU

TA

-O

UT

A+

OU

TB

-O

UT

B+

VDDVDD

C439220pA XXX2

C41

0

470p

AXX

X2

R48

3

18K

AXX

X2

R46

24K

7AXX

X2

FB

68B

LM11

A60

1SPT

XXX2

C40

5

470p

AXX

X2

R47

34K

7AXX

X2

+

C42

7

1u/T

CXX

X2

C41

7

1u/C

AXX

X2

+C

457

1u/T

CXX

X2

R48

8

6K8A

XXX2

C40

7

100n

AXX

X2

C41

2

10pA

XXX2

C42

0

22pA

XXX2

C41

6

1u/C

AXX

X2

U19

78L0

5AC

MXX

X2

81

2367

4 5

VIN

VO

UT

GNDGNDGNDGND

NC

0N

C1

XT3

24M

HZ5

760/

QA

XXX2

+

C42

2 100u

/TA

XXX2

R47

710

KA

XXX2

R47

22K

AXX

X2

+C

406

10u/

UC

XXX2

R47

847

KA

XXX2

CN

12C

SW

15/X

JXX

X2

13 12 11 10

1

14151617

C40

4

1u/C

AXX

X2

C43

0

100n

AXX

X2

R46

433

RA

XXX2

FB

74

BLM

11A

601S

PTXX

X2

U18

LP39

65E

MP

-AD

JXX

X22

4

5

1

3V

IN

AD

J

GND

SD

HN

#

VO

UT

C42

3

470p

AXX

X2

R48

6

10K

AXX

X2

R48

210

KA

XXX2

R46

0

4K7A

XXX2

C44

8

100n

AXX

X2

CN

12A

SW

15/X

JXX

X25 4 3 2

1

14151617

SP

KR

16,3

3

MP

CI_

AU

DIN

29

AM

P_S

HD

N16

CK

_AC

BIT

CLK

16,2

9

AC

_SD

IN2

16

MP

CI_

AU

DO

UT

29

AC

_SY

NC

16,2

9

AC

_SD

OU

T16

,29

AC

_RS

T#

16,2

9

V_3

V3

6,8,

12,1

5..1

7,19

,20,

26..2

9,33

,35

V_5

V0

17,1

9..2

1,25

..27,

29..3

5V

_5V

AU

D29

V_A

MP

SH

IELD

21,2

5,27

,31,

32

GN

D_A

UD

29

GN

D4,

7,8,

10..2

2,24

..35

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

PCIRST#

MODIFY BY 3/20

B44

4B-W

2.00

LAN

-10/

100/

1000

BU

S

Inte

l (R

) 84

5E In

tera

ctiv

e C

lient

Ref

eren

ce D

esig

n

C24

35M

onda

y, A

pril

21, 2

003

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

eS

heet

of

EE

1_D

O

SP

AR

EP

IN

LAN

_G12

P_C

BE

#1

P_A

D[0

..31]

TC

K

P_A

D0

SP

AR

EP

IN

SP

AR

EP

IN

SP

AR

EP

IN

P_C

BE

#0

SP

AR

EP

IN

EE

1_D

I

SP

AR

EP

IN

TR

ST

#

P_C

BE

#2

SP

AR

EP

IN

EE

1_C

S

AW

OL_

B

SP

AR

EP

IN

CK

_LA

NC

SP

AR

EP

IN

EE

1_C

K

SP

AR

EP

IN

AU

XPW

R

SP

AR

EP

IN

SP

AR

EP

IN

SP

AR

EP

IN

AW

OL

P_C

BE

#3

SP

AR

EP

IN

LAN

_ID

SE

L

P_A

D1

P_A

D2

P_A

D3

P_A

D4

P_A

D5

P_A

D6

P_A

D7

P_A

D8

P_A

D9

P_A

D10

P_A

D11

P_A

D12

P_A

D13

P_A

D14

P_A

D15

P_A

D16

P_A

D17

P_A

D18

P_A

D19

P_A

D20

P_A

D21

P_A

D22

P_A

D23

P_A

D24

P_A

D25

P_A

D26

P_A

D27

P_A

D28

P_A

D29

P_A

D30

P_A

D31

P_AD17

CK

_LA

N

CLK

RU

NX#

SP

AR

EP

IN

EE

1_8#

_16

ISO

LAT

E#

SP

AR

EP

IN

AW

OL_

CP

_RS

TLA

N#

ALO

V_2

V5L

AN

V_3

V3L

AN

V_3

V3L

AN

V_3

V3L

AN

V_3

V3L

AN

V_3

V3L

AN

V_3

V3L

AN

V_3

V3L

AN

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

V_3

V3L

AN

V_2

V5L

AN

V_3

V3S

B

V_3

V3S

B

GN

D

U20

AIn

tel 8

2540

EM

Gig

abit

Eth

erne

t Con

trol

ler

P7

N9

M8

M9

P9

M10

N10

P10

M11

M12

N13

P13

N14

M13

M14

L12

L13

L14

K14

J12

J13

J14

H12

H13

H14

G12

F12

F13

F14

A10

C9

B10

A6

C5

B9

A9

G1

C8

A4

B8

A8

C7

C6

B6

B5

A5

B4

B2

B1

C1

D3

D2

D1

E3

K1 L2 L1 M3

M2

M1

N2

N3

P3

N4

P4

M5

N5

P5

P6

M7

N7

C4

F3 L3 M4

F1

F2

G3

H1

H3 J1 A2 J2 H2

C3 J3 C2

EE

CS

AE

N/F

LCS

#F

LOE

#F

LWE

#

FLA

[16]

FLA

[15]

/EE

SK

FLA

[14]

/EE

DO

FLA

[13]

/EE

DI

MC

NT

SM

#/F

LA[1

2]M

INT

/FLA

[11]

MR

ING

#/F

LA[1

0]M

RS

T/F

LA[0

9]IO

CH

RD

Y/F

LA[0

8]C

LKE

N/F

LA[0

7]/T

DI

FLA

[06]

/TD

OF

LA[0

5]/T

MS

FLA

[04]

/TR

ST

#F

LA[0

3]/T

CK

FLA

[02]

/XT

AL1

AU

XPW

R/F

LA[0

1]P

CIM

OD

E/F

LA[0

0]

FLD

[7]/X

TA

L2

FLD

[6]

FLD

[5]/M

DI_

3+F

LD[4

]/MD

I_3-

FLD

[3]/2

V5

FLD

[2]

FLD

[1]/M

DI_

2+F

LD[0

]/MD

I_2-

SM

BC

LKS

MB

D

SM

BA

LRT

#

PM

E#

CS

TS

CH

G/W

OL

ISO

LAT

E#/

PC

I_R

ST

#

ALT

RS

T#/

PW

RG

D

CLO

CK

CLK

RU

N#

IDS

EL

AD

[31]

AD

[30]

AD

[29]

AD

[28]

AD

[27]

AD

[26]

AD

[25]

AD

[24]

AD

[23]

AD

[22]

AD

[21]

AD

[20]

AD

[19]

AD

[18]

AD

[17]

AD

[16]

AD

[15]

AD

[14]

AD

[13]

AD

[12]

AD

[11]

AD

[10]

AD

[09]

AD

[08]

AD

[07]

AD

[06]

AD

[05]

AD

[04]

AD

[03]

AD

[02]

AD

[01]

AD

[00]

C/B

E[3

]#C

/BE

[2]#

C/B

E[1

]#C

/BE

[0]#

IRD

Y#

FR

AM

E#

TR

DY

#S

TO

P#

DE

VS

EL#

PA

R

SE

RR

#P

ER

R#

INT

A#

RE

Q#

GN

T#

RS

T#/

M66

EN

C46

3

100n

A

R50

70R

A

R49

010

0RA

R49

947

KA

R49

50R

A

R49

33K

3A

R49

64K

7A

R49

70R

A

U21

AT

93LC

66-2

V7

1 2 3 4

8 57 6

CS

CK

DI

DO

VC

C

GN

D

NC

16/8

#

R50

10R

AXX

X1XX

X2

R50

410

KA

R50

20R

AXX

X1XX

X2

Q8

BC

847/

B

3

1

2

R50

31K

AXX

X1XX

X2

R50

610

KA

C46

4

10pA

XXX1

XXX2

R48

94K

7A

R49

11K

A

R49

40R

AXX

X1XX

X2

R49

21K

A

R49

80R

AXX

X1XX

X2

R50

875

RA

XXX1

XXX2

R50

08K

2A

C74

2

470n

P_G

NT

#415

P_R

ST

1#15

,19,

20,2

6

CK

_LA

N12

P_P

ME

#15

,29

RI#

16,1

8

SM

BA

LER

T#

15

P_P

ER

R#

15,2

9P

_SE

RR

#15

,29

P_R

EQ

#415

SM

BC

LK15

,29,

33S

MB

DA

TA

15,2

9,33

P_D

EV

SE

L#15

,29

CLK

RU

N#

18,2

0,29

INT

_PIR

QG

#15

P_A

D[0

..31]

15,2

9

P_T

RD

Y#

15,2

9P_C

BE

#[0.

.3]

15,2

9

P_F

RA

ME

#15

,29

P_I

RD

Y#

15,2

9

P_S

TO

P#

15,2

9

P_P

AR

15,2

9

25M

_X2B

25

25M

_X1B

25

MD

I_2+

25M

DI_

2-25

MD

I_3-

25M

DI_

3+25

V_3

V3L

AN

25

GN

D4,

7,8,

10..2

3,25

..35

V_2

V5L

AN

25

SP

AR

EP

IN6,

7,9,

11,1

5,16

,25.

.27

V_3

V3S

B15

..20,

25,2

9,31

..33,

35

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

(1) : 549R for Intel 82551 LAN Controller

and 2,49K for Intel 82540EM Gigabit

Ethernet Controller

(1206:1/4W)

(! Alternate mount !)

(1)

B44

4B-W

2.00

LAN

-10/

100/

1000

CO

NN

Inte

l (R

) 84

5E In

tera

ctiv

e C

lient

Ref

eren

ce D

esig

n

C25

35M

onda

y, A

pril

21, 2

003

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

eS

heet

of

LAN

_G4

MDI0RC

SP

AR

EP

IN

GND_V2V5LAN

SP

AR

EP

IN

SP

AR

EP

INLA

N_T

EXE

C

SH

IELD

X

SP

AR

EP

IN

AC

TLE

D#C

TE

ST

SP

AR

EP

IN

GND_V1V5LAN

SP

AR

EP

IN

NE

TLN

K_L

ED

#

MDI1RC

SP

AR

EP

IN

SP

AR

EP

IN

SP

AR

EP

IN

LAN

_TXD

1+

LAN

_D9_

L8

LAN

_H4

MDI2RC

MDI3RC

LAN

_TXD

3-

LAN

_TXD

2-

LAN

_TXD

3+

MD

I_2+

LAN

_CM

T0

LAN

_TXD

0+

MD

I_1+

MD

I_0-

LAN

_CM

T3

LAN

_CM

T2

LAN

_TXD

0-

V_IOLAN

LAN

1_R

BIA

S10

LAN

1_V

RE

F

V_3

V3L

AN

C

A_2

5M_X

1A

CT

RL2

5

A_2

5M_1

A_2

5M_2

CT

RL1

5

MD

I_0+

MD

I_0+

MD

I_0-

MD

I_1+

MD

I_1-

MD

I_1-

A_2

5M_X

2A

LAN

_TXD

2+

SP

AR

EP

IN

SH

IELD

LAN

_CM

T1

MD

I_2-

MD

I_3+

MD

I_3-

LAN

_TXD

1-

LAN

_TC

D

SP

AR

EP

IN

SP

AR

EP

IN

V_2

V5L

AN

V_1

V5L

AN

V_2

V5L

AN

V_1

V5L

AN

V_2

V5L

AN

V_2

V5L

AN

V_1

V5L

AN

V_3

V3L

AN

V_3

V3L

AN

V_3

V3L

AN

V_3

V3L

AN

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

DG

ND

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

DG

ND

GN

D

GN

DG

ND

GN

D

GN

D

GN

D

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

D

GN

D

GN

D

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

D

GN

DG

ND

GN

DS

HIE

LD

V_3

V3L

AN

V_2

V5L

AN

GN

D

V_1

V5L

AN

GN

D

V_3

V3S

B

V_5

V0

V_5

V0

GN

D

GN

D

GN

DV

_3V

3LA

N

C467100nA

C491100nA

R53

20R

A

R50

90R

A

R51

90R

A

R52

30R

A

U20

B82

540E

M

A3A7E1K3N6P2

G13

K13N8P12

A11

E12G5G6H5H6H7H8J5J6J7J8J9J10J11

K4

K5K6K7K8K9K10K11L4L5L9L10

G2

B3B7E2K2M6N1

G14K12N12P8

C10

D4D5D6D7D8

D11

E4E5E6E7E8E9E10

E11

F4F5F6F7F8F9F10F11G7G8G9G10G11H9H10

H11

L6L11

B11

A12

C11

C13

C14

E13

E14

C12

B13

B14

A1

A14 D

9D

10 G4

H4 J4 L7 L8 P1

P14

B12

D12

D13

D14

A13

N11

P11

VCCPP0VCCPP1VCCPP2VCCPP3VCCPP4VCCPP5

VCCPL0

VCCPL1VCCPL2VCCPL3

VCCPT0

VCC0VCC1VCC2VCC3VCC4VCC5VCC6VCC7VCC8VCC9

VCC10VCC11VCC12VCC13

VCC14

VCC15VCC16VCC17VCC18VCC19VCC20VCC21VCC22VCC23VCC24VCC25

VIO

GNDPP0GNDPP1GNDPP2GNDPP3GNDPP4GNDPP5

GNDPL0GNDPL1GNDPL2GNDPL3

GNDPT0

GND0GND1GND2GND3GND4

GND5/2V5

GND6GND7GND8GND9GND10GND11GND12

GND13/1V5

GND14GND15GND16GND17GND18GND19GND20GND21GND22GND23GND24GND25GND26GND27GND28

GND29/1V5

GND30GND31

SP

DLE

D/L

NK

100#

LNK

LED

#A

CT

LED

#

TD

PT

DN

RD

PR

DN

VR

EF

/GN

D

RB

IAS

100/

CT

RL2

5

RB

IAS

10/P

HY

RE

F

NC

0N

C1

NC

2/2V

5N

C3

NC

4N

C5/

ZN_C

OM

PN

C6

NC

7/C

LK_B

YP

#N

C8/

2V5

NC

9N

C10

TO

/LN

K10

00#

TI

TE

XEC

/GN

DT

CK

TE

ST

X1/N

C

X2/C

TR

L15

R53

30R

AXX

X1XX

X2

+

C4724u7/TA

C492100nA

R53

10R

AXX

X1XX

X2

C479100nA

R545 51RA

C4991nA

R52

70R

AXX

X1XX

X2

R53

51R

0

R52

60R

AXX

X1XX

X2

TR

1

H50

07

12 3 45 6 78 9 1011 121314172023 22 19 16 24 21 18 15

TC

D_0

TR

D0+

TR

D0-

TC

D_1

TR

D1+

TR

D1-

TC

D_2

TR

D2+

TR

D2-

TC

D_3

TR

D+_

3T

RD

-_3

TXD

-_3

TXD

+_3

TXD

2+

TXD

1+

TXD

0+T

XD0-

TXD

1-

TXD

2-

CM

T_0

CM

T_1

CM

T_2

CM

T_3

+

C47010u/UC

Q10

MJD

210

2

1

3

+

C47610u/UC

C487100nA

C488100nA

C475100nA

R547 51RA

R546 51RA

R53

610

0KA

R52

20R

A

C484100nA

R51

72K

49A

R548 51RA

R549 51RA

R53

40R

A

C46

822

pA

C494100nA

C493100nA

R52

80R

A

R52

033

RA

R54

075

RA

CF

6N

FM

60R

30T

222

1

2

3

Q9

MJD

210

2

1

3 C482100nA

C50

2

10nA

C489100nA

R53

70R

A

R51

333

0RA

C50

3

10nA

R54

175

RA

R52

90R

A

R51

60R

A

R51

00R

AXX

X1XX

X2

R53

975

RA

C48

01n

5/H

V

+

C4784u7/TA

C5001nA

+C

483

22u/

TA

+

C4664u7/TA

R542 51RA

R52

54K

7A

C50

1

10nA

C490100nA

C50

4

10nA

+

C47710u/UC

C473100nA

R53

062

0RA

XXX1

XXX2

+

C4744u7/TA

CN

16

SW

08/R

J

1 2 3 4 56 7 8

9 1011 12T

X0+/

DA

T0+

TX0

-/D

AT

0-

RX0

+/D

AT

1+

DA

T2+

DA

T2-

RX0

-/D

AT

1-

DA

T3+

DA

T3-

SH

LD1

SH

LD2

DR

L1D

RL2

R52

447

KA

C46

922

pA

+

C47110u/UC

C485100nA

R543 51RA

R544 51RA

+

C49810u/UC

C46

510

0nA

XT4

25M

HZ0

000/

QB

13

24

R53

875

RA

C486100nA

R51

851

RA

NE

T_L

ED

_AC

T#

33N

ET

LNK

_LE

D#

33

25M

_X2B

24

25M

_X1B

24

MD

I_3+

24M

DI_

3-24

MD

I_2+

24M

DI_

2-24

V_2

V5L

AN

24

SP

AR

EP

IN6,

7,9,

11,1

5,16

,24,

26,2

7

V_3

V3L

AN

24

GN

D4,

7,8,

10..2

4,26

..35

V_1

V5L

AN

V_5

V0

17,1

9..2

1,23

,26,

27,2

9..3

5

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Set =

ENABLE

SDRAM

B44

4B-W

2.00

VG

A S

M73

1 -

01Inte

l (R

) 84

5E In

tera

ctiv

e C

lient

Ref

eren

ce D

esig

n

C26

35M

onda

y, A

pril

21, 2

003

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

eS

heet

of

ST

P_A

GP

#

G_M

A0

AC

ON

PM

E_V

GA

#

G_A

D0

G_A

D16

G_S

T0

G_M

A11

G_B

A0

G_M

A1

G_M

A4

G_M

A5

G_B

US

Y#

G_M

A10

G_C

/BE

#0

G_B

A1

G_S

T2

G_M

A6

G_A

D[0

..31]

G_M

A7

G_S

BA

0 G_T

EST

1

G_I

DS

EL

PD

OW

N#

G_M

A2

SP

AR

EP

IN

G_M

A9

G_M

A3

G_S

T1

G_M

A8

SP

AR

EP

IN

G_A

D1

G_A

D2

G_A

D3

G_A

D4

G_A

D5

G_A

D6

G_A

D7

G_A

D8

G_A

D9

G_A

D10

G_A

D11

G_A

D12

G_A

D13

G_A

D14

G_A

D15

G_A

D17

G_A

D18

G_A

D19

G_A

D20

G_A

D21

G_A

D22

G_A

D23

G_A

D24

G_A

D25

G_A

D26

G_A

D27

G_A

D28

G_A

D29

G_A

D30

G_A

D31

G_S

BA

1G

_SB

A2

G_S

BA

3G

_SB

A4

G_S

BA

5G

_SB

A6

G_S

BA

7

G_C

/BE

#1G

_C/B

E#2

G_C

/BE

#3

G_T

EST

0

SP

AR

EP

IN

SE

T_S

D

GN

D

GN

D

GN

D

GN

D

GN

D

V_1

V5

V_5

V0

V_5

V0

V_3

V3

V_3

V3

V_3

V3

GN

D

R55

64K

7AXX

X1XX

X2

R55

34K

7A

R78

90R

A

R56

48K

2A

R56

210

0RA

R56

68K

2A

U22

A

SM

731G

X16B

CXX

X2

D6

AC

5

L2 L3 K2

K1

J2 K3

Y7

P1

P2

H3

J4

N4

Y21

F20

E20

G20

D20

A16

A17

B17

C17

B18

C16

C21

H20

G21

F21

F22

G22 B

7

C8

C7

C9

B9

A8

D19

D18 B

8A

7

N21

P22

P23

B22

AB

23 W7

M23

T20

T21

T22

E23

E22

E21

D23

D22

D21

C23

C22

B21

C19

A21

B20

C18

A20

B19

A19

C15

A14

B15

A13

C14

B14

B13

C13

C12

C11

B11

B12

C10 A

9B

10A

10

K4

R4

P3

J3 N2

M2

N3

P4

M3

M4

L4 L1

D9

D10

D11

D12

D13

D14

D15

D16

C20

A18

B16

A15

R1

T4

R2

R3

G3

J1 H4

H1

AC

4A

C3

AB

3A

A3

AA

2A

A1

Y2

Y1

T3

U3

U4

V3

V4

W3

W4

Y6

W1

W2

V1

V2

U1

U2

T1

T2

Y4

Y3

AA

6A

A5

AA

4A

B6

AB

5A

B4

A5

A6

B6

B5

C6

C5

C4

D8

H2

G1

G2

F2

F1

E1

E2

D1

D7

D5

D4

D3

E4

E3

F4

F3

D2

C3

C2

C1

B4

B3

A3

A4

DQ

S0

DQ

S1

BA

0B

A1

RA

S#

CA

S#

WE

#C

S0#

RO

M#

SD

CK

SD

CK

#S

DC

KE

N

DS

F

RS

1R

S0

AD

_ST

B0

AD

_ST

B1

AD

_ST

B#0

AD

_ST

B#1

PA

RF

RA

ME

#T

RD

Y#

IRD

Y#

ST

OP

#D

EV

SE

L#ID

SE

L

CLO

CK

RS

T#

RE

Q#

GN

T#

INT

A#

PM

E#

PIP

E#

RB

F#

ST

0S

T1

ST

2

SB

_ST

BS

B_S

TB

#

AG

P_B

US

Y#

ST

P_A

GP

#

PD

OW

N#

CLK

RU

N#/

AC

TIV

ITY

AC

ON

RS

2R

S3

RS

4R

S5

RS

6

TE

ST

0T

ES

T1

AD

31A

D30

AD

29A

D28

AD

27A

D26

AD

25A

D24

AD

23A

D22

AD

21A

D20

AD

19A

D18

AD

17A

D16

AD

15A

D14

AD

13A

D12

AD

11A

D10

AD

9A

D8

AD

7A

D6

AD

5A

D4

AD

3A

D2

AD

1A

D0

MA

11M

A10

MA

9M

A8

MA

7M

A6

MA

5M

A4

MA

3M

A2

MA

1M

A0

SB

A7

SB

A6

SB

A5

SB

A4

SB

A3

SB

A2

SB

A1

SB

A0

BE

#3B

E#2

BE

#1B

E#0

DQ

M#7

DQ

M#6

DQ

M#5

DQ

M#4

DQ

M#3

DQ

M#2

DQ

M#1

DQ

M#0

MD

63M

D62

MD

61M

D60

MD

59M

D58

MD

57M

D56

MD

55M

D54

MD

53M

D52

MD

51M

D50

MD

49M

D48

MD

47M

D46

MD

45M

D44

MD

43M

D42

MD

41M

D40

MD

39M

D38

MD

37M

D36

MD

35M

D34

MD

33M

D32

MD

31M

D30

MD

29M

D28

MD

27M

D26

MD

25M

D24

MD

23M

D22

MD

21M

D20

MD

19M

D18

MD

17M

D16

MD

15M

D14

MD

13M

D12

MD

11M

D10

MD

9M

D8

MD

7M

D6

MD

5M

D4

MD

3M

D2

MD

1M

D0

R56

74K

7A

R56

04K

7AXX

X1XX

X2

R55

84K

7AXX

X1XX

X2

R56

94K

7A

R57

14K

7AXX

X1

XXX2

R57

04K

7A

R56

58K

2A

R55

74K

7AXX

X1XX

X2

R55

44K

7A

R55

24K

7AXX

X1XX

X2R

551

4K7A

R79

14K

7A

R56

14K

7AXX

X1XX

X2

R55

94K

7AXX

X1XX

X2

R55

04K

7A

R57

24K

7AXX

X1

XXX2

R56

38K

2A

R55

54K

7A

R56

810

kAXX

X1XX

X2

CK

_AG

P66

12

G_S

BA

[0..7

]10

G_I

RD

Y#

10

G_A

DS

TB

0-10

G_P

IPE

#10

G_S

T[0

..2]

10

P_R

ST

1#15

,19,

20,2

4G_A

DS

TB

1+10

G_F

RA

ME

#10

G_R

BF

#10

G_A

DS

TB

1-10

G_G

NT

#10

G_S

BS

TB

+10G

_C/B

E#[

0..3

]10

G_S

BS

TB

-10

G_A

DS

TB

0+10

AC

TIV

ITY

28

INT

_PIR

QA

#15

,29

G_R

EQ

#10

G_A

D[0

..31]

10

G_P

AR

10

G_S

TO

P#10

G_D

EV

SE

L#10

G_T

RD

Y#

10

V_5

V0

17,1

9..2

1,23

,25,

27,2

9..3

5

V_1

V5

10,1

1,17

,28,

33,3

4

V_3

V3

6,8,

12,1

5..1

7,19

,20,

23,2

7..2

9,33

,35

GN

D4,

7,8,

10..2

5,27

..35

SP

AR

EP

IN6,

7,9,

11,1

5,16

,24,

25,2

7

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

SM

B-A

ddre

ss is

fixed

to 7

0H

GND to GND_VID:

see at sheet

SM731-03

B44

4B-W

2.00

VG

A S

M73

1 -

02Inte

l (R

) 84

5E In

tera

ctiv

e C

lient

Ref

eren

ce D

esig

n

C27

35M

onda

y, A

pril

21, 2

003

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

eS

heet

of

TX3

_4+

V_5DVI

V_D

L_C

L

ENA_VDL#

ST

27#

SP

AR

EP

IN

CH

RO

MA

CV

BS

LUM

A

TM

DS

2+

CO

MP

FLT

1

TM

DS

2C+

TM

DS

CLK

+

TM

DS

0-

TM

DS

1C+

DD

C_D

AT

V_D

BL

V_B

LI

ISE

L

TM

DS

1-

SIL

_RS

VD

TM

DS

CLK

C+

TM

DS

1C-

TM

DS

1+

TM

DS

0C-

V_5

DV

IFD

DC

_CLK

TM

DS

2-

V_A

VC

C1

V_DL_CLF

TM

DS

CLK

C-

GN

D_D

VI

DK

EN

V_P

VC

C1

HO

TP

LUG

AB

LUE

TM

DS

2C-

TM

DS

0+T

MD

S0C

+

V_V

CC

1

CK

_27

EXT

_SW

ING

TM

DS

CLK

-

V_V

RE

F_S

II

SP

AR

EP

IN

AR

ED

SP

AR

EP

IN

FD

AT

A16

FD

AT

A2

TXC

LK1-

FP

HS

YN

C

FD

AT

A20

FD

AT

A19

FD

AT

A8

SP

AR

EP

IN

FD

AT

A21

SP

AR

EP

IN

TX1

-

TX2

-

ITV

_RE

D

ITV

_HS

YN

C

TXC

LK2-

SP

AR

EP

IN

SP

AR

EP

IN

FP

EN

1

FD

AT

A13

ITV

_C

SP

AR

EP

IN

SP

AR

EP

IN

FD

AT

A12

ITV

_GR

EE

N

SP

AR

EP

IN

SP

AR

EP

IN

SP

NLC

LKI

TX5

+

FD

AT

A3

ITV

_Y

SP

AR

EP

IN

FD

AT

A6

SP

AR

EP

IN

TX5

-

FD

AT

A15

FP

DE

SP

AR

EP

IN

SP

AR

EP

IN

TX2

+

IRE

F_V

GA

1

IRE

F_V

GA

2

SP

AR

EP

IN

ITV

_VS

YN

C

FP

VS

YN

C

CK

_PA

L

FD

AT

A10

SP

AR

EP

IN

TXC

LK2+

FD

AT

A23

SP

AR

EP

IN

FD

AT

A4

FD

AT

A14

MS

EN

X

ITV

_BLU

E

SP

AR

EP

IN

SP

AR

EP

IN

FD

AT

A22

SP

AR

EP

IN

TX6

+

SP

AR

EP

IN

ITV

_CV

BS

TX1

+

FD

AT

A17

TX4

-

SP

AR

EP

IN

SP

AR

EP

IN

EN

A_V

DL

EXC

KE

N#

SP

AR

EP

IN

TX6

-

TX4

+

SP

AR

EP

IN

TXC

LK1+

TX3

-

SP

AR

EP

IN

SP

AR

EP

IN

FD

AT

A18

SP

AR

EP

IN

TX0

-T

X0+

CK

_FP

S

FD

AT

A11

FD

AT

A9

FD

AT

A7

FD

AT

A5

FD

AT

A1

FD

AT

A0

TX6

C-

TX6

C+

TX5

C-

TX5

C+

TX3

_4-

TX3

_4C

-T

X3_4

C+

TXC

LK2C

-T

XCLK

2C+

TX2

C-

TX2

C+

TX1

C+

TX1

C-

TX0

C+

TX0

C-

TXC

LK1C

+T

XCLK

1C-

MS

EN

SI_

PW

RD

N#

SIL

_BS

EL

SIL

_DS

EL

ITV

_HS

YN

CX

AH

SY

NCA

GR

EE

N

ITV

_SD

A

AV

SY

NC

ITV

_SC

L

ITV

_VS

YN

CX

V_5

V0V

GA

TX3

+

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

DG

ND

GN

D

GN

D

GN

D

GN

D

GN

D

GN

DG

ND

GN

D

GN

D

GN

D

GN

D

GN

DG

ND

GN

D

GN

D

GN

D_V

ID

GN

D_V

ID

GN

D_V

IDG

ND

_VID

GN

D_V

ID

SH

IELD

SH

IELD

SH

IELD

GN

D

GN

D

V_1

2V0

V_1

2V0

V_5

V0

V_5

V0

V_3

V3

V_3

V3

V_3

V3

V_3

V3

V_3

V3

V_3

V3

V_3

V3

GN

D

GN

D_V

IDG

ND

_VID

GN

D_V

ID

SH

IELD

GN

D_V

ID

GN

D_V

ID

GN

D_V

ID

GN

D

GN

D

GN

D

V_3

V3

GN

D

GN

D

V_5

V0

+C

515

22u/

TA

XXX2

L22

PLW

3216

S10

2XX

X2

13

42

FB

82

BLM

11A

601S

PTXX

X2

L21

PLW

3216

S10

2XX

X2

13

42

U25

27M

HZ0

000/

OC

XXX2

4

21

3V

CC

GN

DS

T#

OU

T

R58

30R

A

FB

79

BLM

11A

601S

PTXX

X2

L23

PLW

3216

S10

2XX

X2

13

42

CN

39

SM

02/R

AXX

X2

12

C51

0

100n

AXX

X2

R76

64K

7A

R57

71K

A

FB

84

BLM

11A

601S

PTXX

X2

L17

PLW

3216

S10

2XX

X2

13

42

CN

19

SM

07/F

AXX

X2

1 4 3 2 5 67

VD

D_B

LI

VD

D_D

BL

VS

S_D

BL

VS

S_B

LI

RS

VD

VA

RY

_BL

EN

A_B

L

D S

G2N

7002

/BQ

12

XXX2

CN

40

SW

04/R

BXX

X2

123 4

5

6

7

R59

01K

AXX

X2

L19

PLW

3216

S10

2XX

X2

13

42

CF

8

NF

M60

R30

T22

2XX

X2

1

2

3

C52

010

0nA

XXX2

C52

3

220p

AXX

X2

FB

83

BLM

11A

601S

PTXX

X2

+C

512

22u/

TA

XXX2

CF

10N

FM

60R

30T

222

XXX2 1

2

3

CN

18

SW

29/V

IXX

X2

1 2

34 5 6 789 10

11

12 13

14 15

1617 18

1920 21

22

2324 C1

C2

C3

C4

C5

C6

DR

2

DR

1

TM

DS

_Dat

a2-

TM

DS

_Dat

a2+

TM

DS

_Dat

2/4_

Shl

dT

MD

S_D

ata4

-T

MD

S_D

ata4

+

DD

C_C

lock

DD

C_D

ata

Ana

log_

VS

YN

C

TM

DS

_Dat

a1-

TM

DS

_Dat

a1+

TM

DS

_Dat

1/3_

Shl

d

TM

DS

_Dat

a3-

TM

DS

_Dat

a3+

+5V

GN

D

Hot

_Plu

g_D

etec

t

TM

DS

_Dat

a0-

TM

DS

_Dat

a0+

TM

DS

_Dat

0/5_

Shl

dT

MD

S_D

ata5

-T

MD

S_D

ata5

+

TM

DS

_Clo

ck_S

hld

TM

DS

_Clo

ck+

TM

DS

_Clo

ck -

Ana

log_

Red

Ana

log_

Gre

enA

nalo

g_B

lue

Ana

log_

HS

YN

C

GN

DA

1

GN

DA

2

DR

2

DR

1

D25

BA

T54

XXX2

+C

507

4u7/

TA

XXX2

R59

3

75R

AXX

X2

R58

7

47K

AXX

X2

R76

74K

7A R58

133

RA

C50

5

100n

AXX

X2

R57

30R

A

L20

PLW

3216

S10

2XX

X2

13

42

R57

51K

A

R58

0

510R

AXX

X2

L26

PLW

3216

S10

2XX

X2

13

42

C52

147

pAXX

X2

U24

A

74LV

T12

5XX

X2

1 2

14 73O

E#

IN

VC

C

GN

DO

UT

CF

7

NF

M60

R30

T22

2XX

X2

1

2

3

C51

7

100n

AXX

X2

R58

40R

A

F3

SM

D07

5-2

XXX2

12

U24

B

74LV

T12

5XX

X2

4 5

14 76O

E#

IN

VC

C

GN

DO

UT

L24

PLW

3216

S10

2XX

X2

13

42

FB

80

BLM

11A

601S

PTXX

X2

CF

11

NF

M60

R30

T22

2

XXX21

2

3

C50

6

100n

AXX

X2 CF

9

NF

M60

R30

T22

2XX

X2

1

2

3

L25

PLW

3216

S10

2XX

X2

13

42

FB

78

BLM

11A

601S

PTXX

X2

D

S G

SI4

425D

YQ

11

XXX2

4

8

1237 6 5

U22

B

SM

731G

X16B

CXX

X2

M21

T23

N22

N20

AC

21

AB

21

AA

9Y

10

Y8

AB

16

AB

15

AC

15

Y9

AC

6

AA

10

AB

10

AC

18

AA

19

AA

20

AC

20

AB

18

Y19

Y20

AB

20

AB

19A

C19

AC

17A

B17

AA

18Y

18

Y16

AA

16

AA

17Y

17

AA

15Y

15

F23

G23

H21

H22

H23 J2

2J2

1J2

0K

22K

20M

22K

21K

23 L20

L23

L21

M20L2

2N

23 J23

U23

V23

V22

V21

W23

Y23

AA

23

P20

P21

Y22

AC

16A

B14

AC

14A

C13

Y14

AA

14A

B13

AA

13Y

13Y

12A

B12

AA

12Y

11A

C10

AB

11A

A11

AA

8A

B9

AC

9A

B8

AC

8A

A7

AB

7A

C7

R23

R22

R21

R20

PA

LCLO

CK

CK

IN

MC

KIN

/TM

DS

CLK

EXC

KE

N#

SP

NLC

LKO

SP

NLC

LKI

FP

HS

YN

CF

PV

SY

NC

FP

DE

FP

EN

2

FP

VD

DE

N2

FP

VB

IAS

EN

2

FP

SC

LK

FP

EN

1

FP

VD

DE

N1

FP

VB

IAS

EN

1

TX+

0

TX+

1

TX+

2

TX+

3

TX-

0

TX-

1

TX-

2

TX-

3

TXC

LK+1

TXC

LK-1

TX+

4T

X-4

TX+

5T

X-5

TXC

LK+2

TXC

LK-2

TX+

6T

X-6

TX+

7T

X-7

P0

P1

P2

P3

P4

P5

P6

P7

P8

P9

P10

P11

P12

P13

P14

P15

BLA

NK

HR

EF

VR

EF

PC

LK

IRE

F2

CV

BS CY

RE

DG

RE

EN

BLU

E

CR

TH

SY

NC

CR

TV

SY

NC

IRE

F

FD

AT

A23

FD

AT

A22

FD

AT

A21

FD

AT

A20

FD

AT

A19

FD

AT

A18

FD

AT

A17

FD

AT

A16

FD

AT

A15

FD

AT

A14

FD

AT

A13

FD

AT

A12

FD

AT

A11

FD

AT

A10

FD

AT

A9

FD

AT

A8

FD

AT

A7

FD

AT

A6

FD

AT

A5

FD

AT

A4

FD

AT

A3

FD

AT

A2

FD

AT

A1

FD

AT

A0

US

R0/

SC

LU

SR

1/S

DA

US

R2

US

R3

R58

50R

AXX

X1XX

X2

R57

81K

A

R57

48K

2A

U23

SiI1

64C

T64

XXX2

49

11

16 18 320 266448331 1712 32

34

23 29 252428273130 2221

5 1014 13 2435 5657

9

815 7 6

19

36 37 38 39 40 41 42 43 44 45 46 47 50 51 52 53 54 55 58 59 60 61 62 63

PV

CC

2

MS

EN

GN

D1

PV

CC

1

VR

EF

AG

ND

1A

GN

D2

GN

D3

GN

D2

VC

C3

VC

C1

PG

ND

VC

C2

AG

ND

3

RE

SE

RV

ED

AV

CC

1A

VC

C2

TX0

+T

X0-

TX1

+T

X1-

TX2

+T

X2-

TXC

+T

XC-

VS

YN

C

PW

RD

N#

DS

EL/

SD

A

ISE

L/R

ST

DE

HS

YN

C

DK

EN

IDC

K-

IDC

K+

ED

GE

/HT

PLG

CT

L1/A

1/D

K1

BS

EL/

SC

L

CT

L2/A

2/D

K2

CT

L3/A

3/D

K3

EXT

_SW

ING

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

R57

651

0RA

L27

PLW

3216

S10

2XX

X2

13

42

C51

9

100n

AXX

X2

R58

24K

7A

R58

933

RA

XXX2

R58

875

0RA

+C

511

4u7/

TA

XXX2

U24

C

74LV

T12

5XX

X2

10 9

14 78O

E#

IN

VC

C

GN

DO

UT

L18

PLW

3216

S10

2XX

X2

13

42

U24

D

74LV

T12

5XX

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B10

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A1

A3

A2

A4

A6

A8

A7

A9

A10

A11

GN

D

GN

D

GN

D

GN

D

GN

D

PC

I_C

LK1

PC

I_C

LK2

PC

I_C

LK3

PC

I_R

EQ

1#

PC

I_R

EQ

2#

PC

/PC

I_D

RE

Q#

PC

/PC

I_D

GN

T#

PC

I_G

NT

1#

PC

I_G

NT

2#G

ND

GN

D

RIS

ER

_ID

1

RIS

ER

_ID

2R

ES

VD

NO

GO

+12V

SE

R_I

RQ

CN

24

SW

124/

BB

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

171819 20 21222324 25 26 2728 29 3031 32

33

34

35

3637

3839

40

41 42

43

44 454647

48 4950

51 5253 54

5556

57 58 5960

61 6263 6465 66 67 68 6970 71 72

73

74

75 76

77

78798081

82 83

8485 8687

88 89

909192 9394 9596

97 98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

TIP

RIN

G8P

MJ-

38P

MJ-

18P

MJ-

68P

MJ-

28P

MJ-

78P

MJ-

48P

MJ-

88P

MJ-

5

LED

1GP

LED

2YP

LED

1GN

LED

2YN

CH

SG

ND

RE

SV

3

INT

B#

+5V

+3.3

V

INT

A#

RE

SV

5R

ES

V4

GN

D

+3.3

VA

UX

CLO

CK

RS

T#

GN

D

+3.3

V

RE

Q#

GN

T#

+3.3

V

GN

D

AD

31

PM

E#

AD

29

RE

SV

6

GN

D

AD

30

AD

27

+3.3

V

AD

25

AD

28

RE

SV

7

AD

26

C/B

E3#

AD

24A

D23

IDS

EL

GN

DG

ND

AD

21A

D22

AD

19A

D20

GN

D

PA

R

AD

17A

D18

C/B

E2#

AD

16

IRD

Y#

GN

D

+3.3

V

FR

AM

E#

CLK

RU

N#

TR

DY

#S

ER

R#

ST

OP

#

GN

D

+3.3

V

PE

RR

#

DE

VS

EL#

C/B

E1#

GN

D

AD

14A

D15

GN

D

AD

13A

D12

AD

11A

D10

GN

DG

ND

AD

9A

D8

C/B

E0#

AD

7

+3.3

V+3

.3V

AD

6A

D5

AD

4

RE

SV

1

AD

2A

D3

AD

0

+5V

RE

S_W

IP0

AD

1

RE

S_W

IP1

GN

DG

ND

AC

SY

NC

M66

EN

AC

SD

IN

AC

SD

OU

TA

CB

ITC

LK

AC

CID

0#A

CC

ID1#

AC

RS

T#

M-A

U-M

ON

RE

SV

0

AU

DIO

GN

D

GN

D

SY

SA

OU

TS

YS

AIN

SY

SA

OU

TG

SY

SA

ING

AU

DIO

GN

DA

UD

IOG

ND

RE

SV

2

MP

CIA

CT

#

VC

C5V

A

+3.3

VA

UX

C63

0

100n

A

R62

210

KA

+C

600

22u/

TA

+C

610

22u/

TF

C60

3

100n

A

C63

2

100n

A

+C

599

22u/

TA

C61

3

100n

A

CN

23

SW

124/

BA

B1

B2

B3

B4

B5

B6

B7

B8

B9

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B24

B25

B26

B27

B28

B29

B30

B31

B32

B33

B34

B35

B36

B37

B38

B39

B40

B41

B42

B43

B44

B45

B46

B47

B48

B49

B53

B54

B55

B56

B57

B58

B59

B60

B61

B62

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

A32

A33

A34

A35

A36

A37

A38

A39

A40

A41

A42

A43

A44

A45

A46

A47

A48

A49

A53

A54

A55

A56

A57

A58

A60

A61

A62

B23

A59

B52

A52

-12V

TC

KG

ND

TD

O+5

V+5

VIN

TB

#IN

TD

#P

RS

NT

1#R

SV

0P

RS

NT

2#G

ND

GN

DR

SV

1G

ND

CLO

CK

GN

DR

EQ

#+5

VA

D31

AD

29G

ND

AD

25+3

.3V

C/B

E3#

AD

23G

ND

AD

21A

D19

+3.3

VA

D17

C/B

E2#

GN

DIR

DY

#+3

.3V

DE

VS

EL#

GN

DLO

CK

#P

ER

R#

+3.3

VS

ER

R#

+3.3

VC

/BE

1#A

D14

GN

DA

D12

AD

10G

ND

AD

7+3

.3V

AD

5A

D3

GN

DA

D1

+5V

AC

K64

#+5

V+5

V

TR

ST

#+1

2VT

MS

TD

I+5

VIN

TA

#IN

TC

#+5

VR

SV

2+5

VR

SV

3G

ND

GN

D+3

.3V

AU

XR

ES

ET

#+5

VG

NT

#G

ND

PM

E#

AD

30+3

.3V

AD

28A

D26

GN

DA

D24

IDS

EL

+3.3

VA

D22

AD

20G

ND

AD

18A

D16

+3.3

VF

RA

ME

#G

ND

TR

DY

#G

ND

ST

OP

#+3

.3V

SD

ON

ES

BO

#G

ND

PA

RA

D15

+3.3

VA

D13

AD

11G

ND

AD

9

+3.3

VA

D6

AD

4G

ND

AD

2A

D0

RE

Q64

#+5

V+5

V

AD

27

+5V

AD

8C

/BE

0#

C61

9

100n

A

C62

1

100n

A

C62

9

100n

A

+C

607

22u/

TA

C62

0

100n

A

+C

614

22u/

TA

CK

_SLO

T2

12

AC

_SY

NC

16,2

3

AC

_RS

T#

16,2

3

CK

_SLO

T1

12

P_G

NT

A#

15

CK

_AC

BIT

CLK

16,2

3A

C_S

DO

UT

16,2

3

CK

_SLO

T1

12

RIS

ER

_ID

116

RIS

ER

_ID

216

SE

RIR

Q15

,18.

.20

MP

CI_

AC

T#

16

MP

CI_

AU

DIN

23

MP

CI_

AU

DM

ON

33

P_R

EQ

#315

P_P

ME

#15

,24

MP

CI_

AU

DO

UT

23

P_G

NT

#015

CK

_MP

CI

12

CK

_SLO

T3

12

P_R

ST

_SLO

TS

#15

P_G

NT

#215

P_G

NT

#315

P_G

NT

#115

P_R

EQ

#215

P_P

RS

NT

2#16

P_R

EQ

#015

P_R

EQ

#115

AC

_SD

IN1

16

P_R

EQ

A#

15

P_P

RS

NT

1#16

P_T

RD

Y#

15,2

4

P_S

TO

P#

15,2

4

INT

_PIR

QA

#15

,26

INT

_PIR

QE

#15

INT

_PIR

QC

#15

INT

_PIR

QF

#15

P_P

AR

15,2

4

P_F

RA

ME

#15

,24

CLK

RU

N#

18,2

0,24

P_D

EV

SE

L#15

,24

INT

_PIR

QB

#15

P_A

D[0

..31]

15,2

4

INT

_PIR

QD

#15

P_S

ER

R#

15,2

4

P_L

OC

K#

15P

_PE

RR

#15

,24

P_I

RD

Y#

15,2

4

P_C

BE

#[0.

.3]

15,2

4

NO

GO

16

GN

D_A

UD

23G

ND

4,7,

8,10

..28,

30..3

5

V_3

V3S

B15

..20,

24,2

5,31

..33,

35

V_-

12V

033

,35

V_3

V3

6,8,

12,1

5..1

7,19

,20,

23,2

6..2

8,33

,35

V_5

V0

17,1

9..2

1,23

,25.

.27,

30..3

5

V_1

2V0

15,2

3,27

,32.

.35

V_5

VA

UD

23

SM

BD

AT

A15

,24,

33S

MB

CLK

15,2

4,33

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

FLOPPY

PRIMARY IDE

SECONDARY IDE

populate for

deviceside cable

detection

populate for

deviceside cable

detection

B44

4B-W

2.00

CO

NN

-01

IDE

-FLO

PP

Y

Inte

l (R

) 84

5E In

tera

ctiv

e C

lient

Ref

eren

ce D

esig

n

C30

35M

onda

y, A

pril

21, 2

003

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

eS

heet

of

IDE

_SD

D3

IDE

_SLE

D#

IDE

_SD

D14

IDE

_SD

D9

IDE

_PD

D11

IDE

_SD

D5

IDE

_SD

D15

IDE

_SD

D4

IDE

_PD

D1

IDE

_PD

D2

IDE

_PLE

D#

IDE

_RS

T#

IDE

_SD

D6

IDE

_PD

D3

IDE

_PD

D8

IDE

_PD

D10

IDE

_PD

D0

IDE

_PD

A0

IDE

_SD

A0

IDE

_PD

D7

IDE

_SD

D7

IDE

_SD

D1

IDE

_PD

D13

IDE

_PD

D12

IDE

_SD

D10

IDE

_PD

A1

IDE

_SD

A2

IDE

_SD

D11

IDE

_SD

D2

IDE

_PD

D14

IDE

_PD

D4

IDE

_PD

D5

IDE

_PD

A2

IDE

_SD

D8

IDE

_PD

D15

IDE

_SD

D12

IDE

_SD

D0

IDE

_PD

D9

IDE

_SD

A1

IDE

_PD

D6

IDE

_SD

D13

IDE

_RS

T#

V_P

IDE

V_S

IDE

GN

D

GN

DG

ND

GN

DG

ND

GN

D

GN

D

GN

DG

ND

GN

D

GN

D

GN

D

GN

D

V_5

V0

V_5

V0

V_5

V0

V_5

V0

V_5

V0S

B

GN

D

CF

15

NF

M60

R30

T22

2

1

2

3

R62

8

1KA

D5

BA

T54

CN

27

SM

34/W

A

12

34

56

78

910

1112

1314

1516

1718

1920

2122

2324

2526

2728

2930

3132

3334

GN

D0

DE

NS

EL

GN

D1

NC

0G

ND

2N

C1

GN

D3

IND

EX#

GN

D4

MT

RA

#G

ND

5D

SB

#G

ND

6D

SA

#G

ND

7M

TR

B#

GN

D8

FLP

DIR

#G

ND

9S

TE

P#

GN

D10

WD

AT

A#

GN

D11

WG

AT

E#

GN

D12

TR

K0#

GN

D13

WP

RO

T#

GN

D14

RD

AT

A#

GN

D15

HD

SE

LG

ND

16D

SK

CH

G

CN

26

SM

44/M

C

3238 2337 25 12127 2931 39

41 42 44

36 33 35

18 16 14 12 10 8 6 4 3 5 7 9 11 13 15 17 2 19 22 24 26 30 40 43202834

IOC

S16

#

CS

1#

IOW

R#

CS

0#

IOR

D#

RE

SE

T#

DR

EQ

IOR

DY

#

DA

CK

#

IRQ

LED

#

VC

C0

VC

C1

VC

C2

A[2

]A

[1]

A[0

]

D[1

5]D

[14]

D[1

3]D

[12]

D[1

1]D

[10]

D[9

]D

[8]

D[7

]D

[6]

D[5

]D

[4]

D[3

]D

[2]

D[1

]D

[0]

GN

D0

GN

D1

GN

D2

GN

D3

GN

D4

GN

D5

GN

D6

GN

D7

NC

0C

SE

L

PD

IAG

#

R63

310

KA

R62

710

KA

C63

9

47nA

XXX1

XXX2

+C

636

22u/

TA

R63

0

1KA

R62

9

1KA

+C

638

22u/

TA

D4

BA

T54

R63

1

1KA

CN

28

SM

44/M

C

3238 2337 25 12127 2931 39

41 42 44

36 33 35

18 16 14 12 10 8 6 4 3 5 7 9 11 13 15 17 2 19 22 24 26 30 40 43202834

IOC

S16

#

CS

1#

IOW

R#

CS

0#

IOR

D#

RE

SE

T#

DR

EQ

IOR

DY

#

DA

CK

#

IRQ

LED

#

VC

C0

VC

C1

VC

C2

A[2

]A

[1]

A[0

]

D[1

5]D

[14]

D[1

3]D

[12]

D[1

1]D

[10]

D[9

]D

[8]

D[7

]D

[6]

D[5

]D

[4]

D[3

]D

[2]

D[1

]D

[0]

GN

D0

GN

D1

GN

D2

GN

D3

GN

D4

GN

D5

GN

D6

GN

D7

NC

0C

SE

L

PD

IAG

#

C63

7

47nA

XXX1

XXX2

R63

2

1KA

CF

16

NF

M60

R30

T22

2

1

2

3

F_W

GA

TE

#19

F_D

RV

DE

N0

19

F_S

TE

P#

19

F_M

TR

0#19

F_H

DS

EL#

19

F_W

DA

TA

#19

F_D

IR#

19F

_MT

R1#

19F_D

RV

DE

N1

19

F_D

S0#

19F

_DS

1#19

IDE

_SD

DA

CK

#16

INT

_IR

Q14

15

IDE

_PIO

RD

Y16

IDE

_SIO

RD

Y16

IDE

_PD

DA

CK

#16

HD

_LE

D#

33

INT

_IR

Q15

15

IDE

_SP

DIA

G#

16

IDE

_PP

DIA

G#

16

IDE

_PD

IOW

#16

IDE

_PD

IOR

#16

IDE

_SD

IOW

#16

IDE

_SD

CS

1#16

IDE

_PD

DR

EQ

16

IDE

_SD

DR

EQ

16

IDE

_SD

IOR

#16

IDE

_SD

CS

3#16

IDE

_PD

CS

3#16

IDE

_PD

CS

1#16

IDE

_RS

T#

15

F_T

RA

K0#

19F

_WP

#19 F

_RD

AT

A#

19

F_I

ND

EX#

19

F_D

SK

CH

G#

19

IDE

_PD

D[0

..15]

16

IDE

_PD

A[0

..2]

16

IDE

_SD

D[0

..15]

16

IDE

_SD

A[0

..2]

16

V_5

V0

17,1

9..2

1,23

,25.

.27,

29,3

1..3

5 V_5

V0S

B17

,19,

21,2

2,31

..35

GN

D4,

7,8,

10..2

9,31

..35

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

USB0 & USB1

TOP PORT

LAN0

BOTTOM PORT

stacked RJ45/USB

connector

Disable circuitry according to

Intel 845E Chipset Design

Guide Rev.0.7 p. 181

B44

4B-W

2.00

US

B0/

US

B1/

LAN

0

Inte

l (R

) 84

5E In

tera

ctiv

e C

lient

Ref

eren

ce D

esig

n

C31

35M

onda

y, A

pril

21, 2

003

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

eS

heet

of

ISO

L_T

EX

TE

ST

EN

LAN

0_T

DP

LAN

0_T

DN

SP

DLE

D

ISO

L_T

I

LAN

0_R

BIA

S10

US

B1-

US

B1+

LAN

0_R

DN

LAN

0_R

DP

LAN

0_R

BIA

S10

0LA

N0_

X2

CT

RD

LAN

0_E

NA

E

CT

TD

LAN

0_X1

LILE

D#

US

B0-

XAC

TLE

D#

SP

DLE

D#

LAN

0_E

NA

B

ISO

L_T

CK

US

B0+

AC

TLE

D#

V_U

SB

0

V_U

SB

1XV

_US

B1

V_U

SB

0X

GN

DG

ND

GN

D

GN

DG

ND

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

DG

ND

V_3

V3S

BV

_3V

3SB

V_3

V3S

B

V_5

V0

V_5

V0

V_5

V0S

B

V_5

V0S

B

SH

IELD

SH

IELD

SH

IELD

SH

IELD

SH

IELD

SH

IELD

SH

IELD

SH

IELD

GN

D

GN

D

V_3

V3S

B

V_3

V3S

B

GN

DG

ND

GN

D

V_3

V3S

B

R64

1

100R

A

XT5

25M

HZ0

000/

QB

13

24

R64

010

MA

+C

640

100u

/TC

R77

90R

A

CF

17

NF

M60

R30

T22

2

1

2

3

R64

3

549R

A

CN

29B

SW

26/X

A

8567

GN

D

VC

CD

-D

+

C64

8

100n

A

C65

433

pA

C64

4

100n

A

R63

633

0RA

R78

00R

A

R63

8

100R

A

C65

1

100n

A

R63

510

KA

U31

8256

2EM

XXX1

XXX2

42 37 39 34 35 43 44 45 46 47 29 30 28 41 26

10 11 15 16 27 31 32 4 5 21

8131824333848222063

40362512319171412972

JRS

TS

YN

CJR

XD2

JCLO

CK

JRXD

0JR

XD1

JTXD

0JT

XD1

JTXD

2

X1 X2 ISO

L_T

EX

ISO

L_T

OX

ISO

L_R

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