Document Number: 324645-006

Intel 6 Series Chipset and Intel C200 Series ChipsetDatasheet

May 2011

2 Datasheet

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Copyright 2011, Intel Corporation

Datasheet 3

Contents

1 Introduction ............................................................................................................ 411.1 About This Manual ............................................................................................. 411.2 Overview ......................................................................................................... 44

1.2.1 Capability Overview............................................................................. 451.3 Intel 6 Series Chipset and Intel C200 Series Chipset SKU Definition ..................... 51

2 Signal Description ................................................................................................... 552.1 Direct Media Interface (DMI) to Host Controller ..................................................... 572.2 PCI Express* .................................................................................................... 572.3 PCI Interface .................................................................................................... 582.4 Serial ATA Interface........................................................................................... 602.5 LPC Interface.................................................................................................... 632.6 Interrupt Interface ............................................................................................ 632.7 USB Interface ................................................................................................... 642.8 Power Management Interface.............................................................................. 652.9 Processor Interface............................................................................................ 692.10 SMBus Interface................................................................................................ 692.11 System Management Interface............................................................................ 692.12 Real Time Clock Interface................................................................................... 702.13 Miscellaneous Signals ........................................................................................ 702.14 Intel High Definition Audio Link ......................................................................... 722.15 Controller Link .................................................................................................. 732.16 Serial Peripheral Interface (SPI) .......................................................................... 732.17 Thermal Signals ................................................................................................ 732.18 Testability Signals ............................................................................................. 742.19 Clock Signals .................................................................................................... 742.20 LVDS Signals .................................................................................................... 772.21 Analog Display /VGA DAC Signals ........................................................................ 782.22 Intel Flexible Display Interface (Intel FDI) ........................................................ 782.23 Digital Display Signals........................................................................................ 792.24 General Purpose I/O Signals ............................................................................... 822.25 Manageability Signals ........................................................................................ 862.26 Power and Ground Signals.................................................................................. 872.27 Pin Straps ........................................................................................................ 892.28 External RTC Circuitry........................................................................................ 92

3 PCH Pin States......................................................................................................... 933.1 Integrated Pull-Ups and Pull-Downs ..................................................................... 933.2 Output and I/O Signals Planes and States............................................................. 953.3 Power Planes for Input Signals .......................................................................... 107

4 PCH and System Clocks ......................................................................................... 1134.1 Platform Clocking Requirements ........................................................................ 1134.2 Functional Blocks ............................................................................................ 1164.3 Clock Configuration Access Overview ................................................................. 1174.4 Straps Related to Clock Configuration ................................................................ 117

5 Functional Description ........................................................................................... 1195.1 DMI-to-PCI Bridge (D30:F0) ............................................................................. 119

5.1.1 PCI Bus Interface.............................................................................. 1195.1.2 PCI Bridge As an Initiator................................................................... 120

5.1.2.1 Memory Reads and Writes .................................................. 1205.1.2.2 I/O Reads and Writes ......................................................... 1205.1.2.3 Configuration Reads and Writes ........................................... 1205.1.2.4 Locked Cycles ................................................................... 1205.1.2.5 Target / Master Aborts ....................................................... 1205.1.2.6 Secondary Master Latency Timer ......................................... 1205.1.2.7 Dual Address Cycle (DAC)................................................... 1215.1.2.8 Memory and I/O Decode to PCI ........................................... 121

5.1.3 Parity Error Detection and Generation.................................................. 1215.1.4 PCIRST# ......................................................................................... 1225.1.5 Peer Cycles ...................................................................................... 122

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5.1.6 PCI-to-PCI Bridge Model.....................................................................1225.1.7 IDSEL to Device Number Mapping........................................................1235.1.8 Standard PCI Bus Configuration Mechanism ..........................................1235.1.9 PCI Legacy Mode...............................................................................123

5.2 PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5, F6, F7) .....................................1245.2.1 Interrupt Generation..........................................................................1245.2.2 Power Management ...........................................................................125

5.2.2.1 S3/S4/S5 Support..............................................................1255.2.2.2 Resuming from Suspended State..........................................1255.2.2.3 Device Initiated PM_PME Message ........................................1255.2.2.4 SMI/SCI Generation ...........................................................126

5.2.3 SERR# Generation.............................................................................1265.2.4 Hot-Plug ..........................................................................................126

5.2.4.1 Presence Detection.............................................................1265.2.4.2 Message Generation ...........................................................1275.2.4.3 Attention Button Detection ..................................................1275.2.4.4 SMI/SCI Generation ...........................................................127

5.3 Gigabit Ethernet Controller (B0:D25:F0) .............................................................1285.3.1 GbE PCI Express* Bus Interface ..........................................................130

5.3.1.1 Transaction Layer...............................................................1305.3.1.2 Data Alignment..................................................................1305.3.1.3 Configuration Request Retry Status ......................................130

5.3.2 Error Events and Error Reporting .........................................................1315.3.2.1 Data Parity Error................................................................1315.3.2.2 Completion with Unsuccessful Completion Status....................131

5.3.3 Ethernet Interface .............................................................................1315.3.3.1 82579 LAN PHY Interface ....................................................131

5.3.4 PCI Power Management......................................................................1325.3.4.1 Wake Up...........................................................................132

5.3.5 Configurable LEDs .............................................................................1345.3.6 Function Level Reset Support (FLR) .....................................................135

5.3.6.1 FLR Steps .........................................................................1355.4 LPC Bridge (with System and Management Functions) (D31:F0).............................136

5.4.1 LPC Interface....................................................................................1365.4.1.1 LPC Cycle Types.................................................................1375.4.1.2 Start Field Definition...........................................................1375.4.1.3 Cycle Type / Direction (CYCTYPE + DIR) ...............................1385.4.1.4 Size .................................................................................1385.4.1.5 SYNC................................................................................1385.4.1.6 SYNC Time-Out..................................................................1395.4.1.7 SYNC Error Indication .........................................................1395.4.1.8 LFRAME# Usage.................................................................1395.4.1.9 I/O Cycles.........................................................................1395.4.1.10 Bus Master Cycles ..............................................................1405.4.1.11 LPC Power Management......................................................1405.4.1.12 Configuration and PCH Implications ......................................140

5.5 DMA Operation (D31:F0) ..................................................................................1415.5.1 Channel Priority ................................................................................141

5.5.1.1 Fixed Priority .....................................................................1415.5.1.2 Rotating Priority.................................................................142

5.5.2 Address Compatibility Mode ................................................................1425.5.3 Summary of DMA Transfer Sizes..........................................................142

5.5.3.1 Address Shifting When Programmed for 16-Bit I/O Count by Words ..........................................................................142

5.5.4 Autoinitialize.....................................................................................1435.5.5 Software Commands..........................................................................143

5.6 LPC DMA ........................................................................................................1445.6.1 Asserting DMA Requests.....................................................................1445.6.2 Abandoning DMA Requests .................................................................1455.6.3 General Flow of DMA Transfers............................................................1455.6.4 Terminal Count .................................................................................1455.6.5 Verify Mode ......................................................................................1465.6.6 DMA Request Deassertion...................................................................1465.6.7 SYNC Field / LDRQ# Rules..................................................................147

5.7 8254 Timers (D31:F0)......................................................................................1475.7.1 Timer Programming ...........................................................................1485.7.2 Reading from the Interval Timer..........................................................149

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5.7.2.1 Simple Read ..................................................................... 1495.7.2.2 Counter Latch Command .................................................... 1495.7.2.3 Read Back Command ......................................................... 149

5.8 8259 Interrupt Controllers (PIC) (D31:F0) .......................................................... 1505.8.1 Interrupt Handling ............................................................................ 151

5.8.1.1 Generating Interrupts......................................................... 1515.8.1.2 Acknowledging Interrupts ................................................... 1515.8.1.3 Hardware/Software Interrupt Sequence ................................ 152

5.8.2 Initialization Command Words (ICWx) ................................................. 1525.8.2.1 ICW1 ............................................................................... 1525.8.2.2 ICW2 ............................................................................... 1535.8.2.3 ICW3 ............................................................................... 1535.8.2.4 ICW4 ............................................................................... 153

5.8.3 Operation Command Words (OCW) ..................................................... 1535.8.4 Modes of Operation ........................................................................... 153

5.8.4.1 Fully Nested Mode ............................................................. 1535.8.4.2 Special Fully-Nested Mode .................................................. 1545.8.4.3 Automatic Rotation Mode (Equal Priority Devices) .................. 1545.8.4.4 Specific Rotation Mode (Specific Priority) .............................. 1545.8.4.5 Poll Mode.......................................................................... 1545.8.4.6 Cascade Mode ................................................................... 1555.8.4.7 Edge and Level Triggered Mode ........................................... 1555.8.4.8 End of Interrupt (EOI) Operations ........................................ 1555.8.4.9 Normal End of Interrupt ..................................................... 1555.8.4.10 Automatic End of Interrupt Mode ......................................... 155

5.8.5 Masking Interrupts............................................................................ 1565.8.5.1 Masking on an Individual Interrupt Request........................... 1565.8.5.2 Special Mask Mode............................................................. 156

5.8.6 Steering PCI Interrupts...................................................................... 1565.9 Advanced Programmable Interrupt Controller (APIC) (D31:F0) .............................. 157

5.9.1 Interrupt Handling ............................................................................ 1575.9.2 Interrupt Mapping ............................................................................. 1575.9.3 PCI / PCI Express* Message-Based Interrupts....................................... 1585.9.4 IOxAPIC Address Remapping .............................................................. 1585.9.5 External Interrupt Controller Support................................................... 158

5.10 Serial Interrupt (D31:F0) ................................................................................. 1595.10.1 Start Frame ..................................................................................... 1595.10.2 Data Frames .................................................................................... 1605.10.3 Stop Frame...................................................................................... 1605.10.4 Specific Interrupts Not Supported Using SERIRQ ................................... 1605.10.5 Data Frame Format ........................................................................... 161

5.11 Real Time Clock (D31:F0)................................................................................. 1625.11.1 Update Cycles .................................................................................. 1625.11.2 Interrupts ........................................................................................ 1635.11.3 Lockable RAM Ranges........................................................................ 1635.11.4 Century Rollover ............................................................................... 1635.11.5 Clearing Battery-Backed RTC RAM....................................................... 163

5.12 Processor Interface (D31:F0) ............................................................................ 1655.12.1 Processor Interface Signals and VLW Messages ..................................... 165

5.12.1.1 A20M# (Mask A20) / A20GATE............................................ 1655.12.1.2 INIT (Initialization) ............................................................ 1665.12.1.3 FERR# (Numeric Coprocessor Error)..................................... 1665.12.1.4 NMI (Non-Maskable Interrupt)............................................. 1675.12.1.5 Processor Power Good (PROCPWRGD) .................................. 167

5.12.2 Dual-Processor Issues ....................................................................... 1675.12.2.1 Usage Differences.............................................................. 167

5.12.3 Virtual Legacy Wire (VLW) Messages ................................................... 1675.13 Power Management ......................................................................................... 168

5.13.1 Features .......................................................................................... 1685.13.2 PCH and System Power States............................................................ 1685.13.3 System Power Planes ........................................................................ 1705.13.4 SMI#/SCI Generation ........................................................................ 171

5.13.4.1 PCI Express* SCI............................................................... 1735.13.4.2 PCI Express* Hot-Plug........................................................ 173

5.13.5 C-States .......................................................................................... 1735.13.6 Dynamic PCI Clock Control (Mobile Only) ............................................. 173

5.13.6.1 Conditions for Checking the PCI Clock .................................. 173

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5.13.6.2 Conditions for Maintaining the PCI Clock................................1745.13.6.3 Conditions for Stopping the PCI Clock ...................................1745.13.6.4 Conditions for Re-Starting the PCI Clock................................1745.13.6.5 LPC Devices and CLKRUN#..................................................174

5.13.7 Sleep States .....................................................................................1745.13.7.1 Sleep State Overview .........................................................1745.13.7.2 Initiating Sleep State..........................................................1755.13.7.3 Exiting Sleep States ...........................................................1755.13.7.4 PCI Express* WAKE# Signal and PME Event Message..............1775.13.7.5 Sx-G3-Sx, Handling Power Failures.......................................1785.13.7.6 Deep S4/S5.......................................................................179

5.13.8 Event Input Signals and Their Usage....................................................1805.13.8.1 PWRBTN# (Power Button) ...................................................1805.13.8.2 RI# (Ring Indicator) ...........................................................1815.13.8.3 PME# (PCI Power Management Event) ..................................1815.13.8.4 SYS_RESET# Signal ...........................................................1825.13.8.5 THRMTRIP# Signal .............................................................182

5.13.9 ALT Access Mode...............................................................................1835.13.9.1 Write Only Registers with Read Paths in ALT Access Mode........1845.13.9.2 PIC Reserved Bits...............................................................1865.13.9.3 Read Only Registers with Write Paths in ALT Access Mode........186

5.13.10 System Power Supplies, Planes, and Signals .........................................1875.13.10.1 Power Plane Control with SLP_S3#,

SLP_S4#, SLP_S5#, SLP_A# and SLP_LAN# .........................1875.13.10.2 SLP_S4# and Suspend-To-RAM Sequencing...........................1875.13.10.3 PWROK Signal ...................................................................1875.13.10.4 BATLOW# (Battery Low) (Mobile Only) .................................1885.13.10.5 SLP_LAN# Pin Behavior ......................................................1885.13.10.6 RTCRST# and SRTCRST#....................................................188

5.13.11 Clock Generators...............................................................................1885.13.12 Legacy Power Management Theory of Operation ....................................189

5.13.12.1 APM Power Management (Desktop Only) ...............................1895.13.12.2 Mobile APM Power Management (Mobile Only)........................189

5.13.13 Reset Behavior..................................................................................1895.14 System Management (D31:F0) ..........................................................................192

5.14.1 Theory of Operation...........................................................................1925.14.1.1 Detecting a System Lockup .................................................1925.14.1.2 Handling an Intruder ..........................................................1935.14.1.3 Detecting Improper Flash Programming ................................1935.14.1.4 Heartbeat and Event Reporting using SMLink/SMBus...............193

5.14.2 TCO Modes .......................................................................................1945.14.2.1 TCO Legacy/Compatible Mode..............................................1945.14.2.2 Advanced TCO Mode...........................................................195

5.15 General Purpose I/O (D31:F0) ...........................................................................1965.15.1 Power Wells......................................................................................1965.15.2 SMI# SCI and NMI Routing.................................................................1965.15.3 Triggering ........................................................................................1965.15.4 GPIO Registers Lockdown ...................................................................1965.15.5 Serial POST Codes over GPIO..............................................................197

5.15.5.1 Theory of Operation ...........................................................1975.15.5.2 Serial Message Format........................................................198

5.16 SATA Host Controller (D31:F2, F5).....................................................................1995.16.1 SATA 6 Gb/s Support .........................................................................2005.16.2 SATA Feature Support........................................................................2005.16.3 Theory of Operation...........................................................................201

5.16.3.1 Standard ATA Emulation .....................................................2015.16.3.2 48-Bit LBA Operation..........................................................201

5.16.4 SATA Swap Bay Support.....................................................................2015.16.5 Hot Plug Operation ............................................................................201

5.16.5.1 Low Power Device Presence Detection...................................2015.16.6 Function Level Reset Support (FLR) .....................................................202

5.16.6.1 FLR Steps .........................................................................2025.16.7 Intel Rapid Storage Technology Configuration .....................................202

5.16.7.1 Intel Rapid Storage Manager RAID Option ROM....................2035.16.8 Intel Smart Response Technology......................................................2035.16.9 Power Management Operation.............................................................203

5.16.9.1 Power State Mappings ........................................................203

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5.16.9.2 Power State Transitions ...................................................... 2045.16.9.3 SMI Trapping (APM)........................................................... 205

5.16.10 SATA Device Presence ....................................................................... 2055.16.11 SATA LED ........................................................................................ 2065.16.12 AHCI Operation ................................................................................ 2065.16.13 SGPIO Signals .................................................................................. 206

5.16.13.1 Mechanism ....................................................................... 2065.16.13.2 Message Format ................................................................ 2075.16.13.3 LED Message Type............................................................. 2085.16.13.4 SGPIO Waveform............................................................... 209

5.16.14 External SATA .................................................................................. 2105.17 High Precision Event Timers.............................................................................. 210

5.17.1 Timer Accuracy................................................................................. 2105.17.2 Interrupt Mapping ............................................................................. 2115.17.3 Periodic versus Non-Periodic Modes ..................................................... 2125.17.4 Enabling the Timers .......................................................................... 2125.17.5 Interrupt Levels ................................................................................ 2135.17.6 Handling Interrupts ........................................................................... 2135.17.7 Issues Related to 64-Bit Timers with 32-Bit Processors .......................... 213

5.18 USB EHCI Host Controllers (D29:F0 and D26:F0)................................................. 2145.18.1 EHC Initialization .............................................................................. 214

5.18.1.1 BIOS Initialization.............................................................. 2145.18.1.2 Driver Initialization ............................................................ 2145.18.1.3 EHC Resets....................................................................... 214

5.18.2 Data Structures in Main Memory ......................................................... 2145.18.3 USB 2.0 Enhanced Host Controller DMA ............................................... 2155.18.4 Data Encoding and Bit Stuffing ........................................................... 2155.18.5 Packet Formats................................................................................. 2155.18.6 USB 2.0 Interrupts and Error Conditions .............................................. 215

5.18.6.1 Aborts on USB 2.0-Initiated Memory Reads ........................... 2165.18.7 USB 2.0 Power Management............................................................... 216

5.18.7.1 Pause Feature ................................................................... 2165.18.7.2 Suspend Feature ............................................................... 2165.18.7.3 ACPI Device States ............................................................ 2165.18.7.4 ACPI System States ........................................................... 217

5.18.8 USB 2.0 Legacy Keyboard Operation.................................................... 2175.18.9 USB 2.0 Based Debug Port ................................................................. 217

5.18.9.1 Theory of Operation .......................................................... 2185.18.10 EHCI Caching ................................................................................... 2225.18.11 Intel USB Pre-Fetch Based Pause ...................................................... 2225.18.12 Function Level Reset Support (FLR) ..................................................... 222

5.18.12.1 FLR Steps ......................................................................... 2225.18.13 USB Overcurrent Protection................................................................ 223

5.19 Integrated USB 2.0 Rate Matching Hub .............................................................. 2245.19.1 Overview ......................................................................................... 2245.19.2 Architecture ..................................................................................... 224

5.20 SMBus Controller (D31:F3) ............................................................................... 2255.20.1 Host Controller ................................................................................. 225

5.20.1.1 Command Protocols ........................................................... 2265.20.2 Bus Arbitration ................................................................................. 2295.20.3 Bus Timing....................................................................................... 230

5.20.3.1 Clock Stretching ................................................................ 2305.20.3.2 Bus Time Out (The PCH as SMBus Master) ............................ 230

5.20.4 Interrupts / SMI# ............................................................................. 2305.20.5 SMBALERT#..................................................................................... 2315.20.6 SMBus CRC Generation and Checking .................................................. 2315.20.7 SMBus Slave Interface....................................................................... 232

5.20.7.1 Format of Slave Write Cycle ................................................ 2335.20.7.2 Format of Read Command .................................................. 2345.20.7.3 Slave Read of RTC Time Bytes............................................. 2365.20.7.4 Format of Host Notify Command.......................................... 237

5.21 Thermal Management ...................................................................................... 2385.21.1 Thermal Sensor ................................................................................ 238

5.21.1.1 Internal Thermal Sensor Operation ...................................... 2385.21.2 PCH Thermal Throttling...................................................................... 2395.21.3 Thermal Reporting Over System Management Link 1 Interface (SMLink1). 240

5.21.3.1 Supported Addresses ......................................................... 241

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5.21.3.2 I2C Write Commands to the Intel ME ..................................2425.21.3.3 Block Read Command.........................................................2425.21.3.4 Read Data Format ..............................................................2445.21.3.5 Thermal Data Update Rate ..................................................2445.21.3.6 Temperature Comparator and Alert ......................................2445.21.3.7 BIOS Set Up......................................................................2465.21.3.8 SMBus Rules .....................................................................2465.21.3.9 Case for Considerations ......................................................247

5.22 Intel High Definition Audio Overview (D27:F0)...................................................2495.22.1 Intel High Definition Audio Docking (Mobile Only) ................................249

5.22.1.1 Dock Sequence ..................................................................2495.22.1.2 Exiting D3/CRST# When Docked ..........................................2505.22.1.3 Cold Boot/Resume from S3 When Docked..............................2515.22.1.4 Undock Sequence...............................................................2515.22.1.5 Normal Undock ..................................................................2515.22.1.6 Surprise Undock ................................................................2525.22.1.7 Interaction between Dock/Undock and Power Management

States ..............................................................................2525.22.1.8 Relationship between HDA_DOCK_RST# and HDA_RST#.........252

5.23 Intel ME and Intel ME Firmware 7.0 ...............................................................2535.23.1 Intel ME Requirements.....................................................................254

5.24 Serial Peripheral Interface (SPI) ........................................................................2555.24.1 SPI Supported Feature Overview .........................................................255

5.24.1.1 Non-Descriptor Mode ..........................................................2555.24.1.2 Descriptor Mode.................................................................255

5.24.2 Flash Descriptor ................................................................................2565.24.2.1 Descriptor Master Region ....................................................258

5.24.3 Flash Access .....................................................................................2595.24.3.1 Direct Access Security ........................................................2595.24.3.2 Register Access Security .....................................................259

5.24.4 Serial Flash Device Compatibility Requirements .....................................2605.24.4.1 PCH SPI-Based BIOS Requirements ......................................2605.24.4.2 Integrated LAN Firmware SPI Flash Requirements ..................2605.24.4.3 Intel Management Engine Firmware SPI Flash Requirements..2615.24.4.4 Hardware Sequencing Requirements.....................................261

5.24.5 Multiple Page Write Usage Model .........................................................2625.24.5.1 Soft Flash Protection...........................................................2635.24.5.2 BIOS Range Write Protection ...............................................2635.24.5.3 SMI# Based Global Write Protection .....................................263

5.24.6 Flash Device Configurations ................................................................2635.24.7 SPI Flash Device Recommended Pinout ................................................2645.24.8 Serial Flash Device Package ................................................................264

5.24.8.1 Common Footprint Usage Model ...........................................2645.24.8.2 Serial Flash Device Package Recommendations ......................265

5.24.9 PWM Outputs (Server/Workstation Only) ..............................................2655.24.10 TACH Inputs (Server/Workstation Only) ...............................................265

5.25 Feature Capability Mechanism ...........................................................................2655.26 PCH Display Interfaces and Intel Flexible Display Interconnect.............................266

5.26.1 Analog Display Interface Characteristics ...............................................2665.26.1.1 Integrated RAMDAC............................................................2675.26.1.2 DDC (Display Data Channel)................................................267

5.26.2 Digital Display Interfaces....................................................................2675.26.2.1 LVDS (Mobile only).............................................................2675.26.2.2 High Definition Multimedia Interface .....................................2705.26.2.3 Digital Video Interface (DVI)................................................2715.26.2.4 DisplayPort*......................................................................2715.26.2.5 Embedded DisplayPort ........................................................2725.26.2.6 DisplayPort Aux Channel .....................................................2725.26.2.7 DisplayPort Hot-Plug Detect (HPD) .......................................2725.26.2.8 Integrated Audio over HDMI and DisplayPort .........................2725.26.2.9 Serial Digital Video Out (SDVO) ...........................................272

5.26.3 Mapping of Digital Display Interface Signals ..........................................2745.26.4 Multiple Display Configurations............................................................2755.26.5 High-bandwidth Digital Content Protection (HDCP).................................2755.26.6 Intel Flexible Display Interconnect .....................................................276

5.27 Intel Virtualization Technology ........................................................................2765.27.1 Intel VT-d Objectives .......................................................................276

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5.27.2 Intel VT-d Features Supported.......................................................... 2765.27.3 Support for Function Level Reset (FLR) in PCH ...................................... 2775.27.4 Virtualization Support for PCHs IOxAPIC.............................................. 2775.27.5 Virtualization Support for High Precision Event Timer (HPET) .................. 277

6 Ballout Definition................................................................................................... 2796.1 Desktop PCH Ballout ........................................................................................ 2796.2 Mobile PCH Ballout .......................................................................................... 2906.3 Mobile SFF PCH Ballout .................................................................................... 302

7 Package Information ............................................................................................. 3077.1 Desktop PCH package ...................................................................................... 3077.2 Mobile PCH Package......................................................................................... 3097.3 Mobile SFF PCH Package................................................................................... 311

8 Electrical Characteristics ....................................................................................... 3138.1 Thermal Specifications ..................................................................................... 313

8.1.1 Desktop Storage Specifications and Thermal Design Power (TDP) ............ 3138.1.2 Mobile Storage Specifications and Thermal Design Power (TDP) .............. 313

8.2 Absolute Maximum Ratings............................................................................... 3148.3 PCH Power Supply Range ................................................................................. 3158.4 General DC Characteristics ............................................................................... 3158.5 Display DC Characteristics ................................................................................ 3288.6 AC Characteristics ........................................................................................... 3308.7 Power Sequencing and Reset Signal Timings ....................................................... 3478.8 Power Management Timing Diagrams................................................................. 3508.9 AC Timing Diagrams ........................................................................................ 355

9 Register and Memory Mapping............................................................................... 3659.1 PCI Devices and Functions................................................................................ 3669.2 PCI Configuration Map ..................................................................................... 3679.3 I/O Map ......................................................................................................... 367

9.3.1 Fixed I/O Address Ranges .................................................................. 3679.3.2 Variable I/O Decode Ranges ............................................................... 370

9.4 Memory Map................................................................................................... 3719.4.1 Boot-Block Update Scheme ................................................................ 373

10 Chipset Configuration Registers............................................................................. 37510.1 Chipset Configuration Registers (Memory Space) ................................................. 375

10.1.1 CIR0Chipset Initialization Register 0 ................................................. 37710.1.2 RPCRoot Port Configuration Register ................................................. 37710.1.3 RPFNRoot Port Function Number and Hide for PCI

Express* Root Ports Register .............................................................. 37810.1.4 FLRSTATFunction Level Reset Pending Status Register ........................ 37910.1.5 TRSRTrap Status Register ............................................................... 38010.1.6 TRCRTrapped Cycle Register ............................................................ 38010.1.7 TWDRTrapped Write Data Register ................................................... 38110.1.8 IOTRnI/O Trap Register (03).......................................................... 38110.1.9 V0CTLVirtual Channel 0 Resource Control Register.............................. 38210.1.10 V0STSVirtual Channel 0 Resource Status Register............................... 38210.1.11 V1CTLVirtual Channel 1 Resource Control Register.............................. 38310.1.12 V1STSVirtual Channel 1 Resource Status Register............................... 38310.1.13 RECRoot Error Command Register .................................................... 38410.1.14 LCAPLink Capabilities Register ......................................................... 38410.1.15 LCTLLink Control Register................................................................ 38510.1.16 LSTSLink Status Register ................................................................ 38510.1.17 DLCTL2DMI Link Control 2 Register .................................................. 38510.1.18 DMICDMI Control Register............................................................... 38610.1.19 TCTLTCO Configuration Register....................................................... 38610.1.20 D31IPDevice 31 Interrupt Pin Register .............................................. 38710.1.21 D30IPDevice 30 Interrupt Pin Register .............................................. 38810.1.22 D29IPDevice 29 Interrupt Pin Register .............................................. 38810.1.23 D28IPDevice 28 Interrupt Pin Register .............................................. 38810.1.24 D27IPDevice 27 Interrupt Pin Register .............................................. 39010.1.25 D26IPDevice 26 Interrupt Pin Register .............................................. 39010.1.26 D25IPDevice 25 Interrupt Pin Register .............................................. 39010.1.27 D22IPDevice 22 Interrupt Pin Register .............................................. 39110.1.28 D31IRDevice 31 Interrupt Route Register .......................................... 392

10 Datasheet

10.1.29 D29IRDevice 29 Interrupt Route Register...........................................39310.1.30 D28IRDevice 28 Interrupt Route Register...........................................39410.1.31 D27IRDevice 27 Interrupt Route Register...........................................39510.1.32 D26IRDevice 26 Interrupt Route Register...........................................39610.1.33 D25IRDevice 25 Interrupt Route Register...........................................39710.1.34 D22IRDevice 22 Interrupt Route Register...........................................39810.1.35 OICOther Interrupt Control Register ..................................................39910.1.36 PRSTSPower and Reset Status Register .............................................40010.1.37 PM_CFGPower Management Configuration Register .............................40110.1.38 DEEP_S4_POLDeep S4/S5 From S4 Power Policies

Register ...........................................................................................40210.1.39 DEEP_S5_POLDeep S4/S5 From S5 Power Policies

Register ...........................................................................................40210.1.40 PMSYNC_CFGPMSYNC Configuration Register .....................................40310.1.41 RCRTC Configuration Register ..........................................................40410.1.42 HPTCHigh Precision Timer Configuration Register ................................40410.1.43 GCSGeneral Control and Status Register............................................40510.1.44 BUCBacked Up Control Register ........................................................40710.1.45 FDFunction Disable Register .............................................................40710.1.46 CGClock Gating Register ..................................................................40910.1.47 FDSWFunction Disable SUS Well Register...........................................41010.1.48 DISPBDFDisplay Bus, Device and Function

Initialization Register .........................................................................41110.1.49 FD2Function Disable 2 Register ........................................................41110.1.50 MISCCTLMiscellaneous Control Register .............................................41210.1.51 USBOCM1Overcurrent MAP Register 1 ...............................................41310.1.52 USBOCM2Overcurrent MAP Register 2 ...............................................41410.1.53 RMHWKCTLRate Matching Hub Wake Control Register..........................415

11 PCI-to-PCI Bridge Registers (D30:F0)....................................................................41711.1 PCI Configuration Registers (D30:F0) .................................................................417

11.1.1 VID Vendor Identification Register (PCI-PCID30:F0) .........................41811.1.2 DID Device Identification Register (PCI-PCID30:F0)..........................41811.1.3 PCICMDPCI Command (PCI-PCID30:F0)..........................................41811.1.4 PSTSPCI Status Register (PCI-PCID30:F0).......................................41911.1.5 RIDRevision Identification Register (PCI-PCID30:F0) ........................42111.1.6 CCClass Code Register (PCI-PCID30:F0) .........................................42111.1.7 PMLTPrimary Master Latency Timer Register

(PCI-PCID30:F0) ............................................................................42211.1.8 HEADTYPHeader Type Register (PCI-PCID30:F0) ..............................42211.1.9 BNUMBus Number Register (PCI-PCID30:F0) ...................................42211.1.10 SMLTSecondary Master Latency Timer Register

(PCI-PCID30:F0) ............................................................................42311.1.11 IOBASE_LIMITI/O Base and Limit Register

(PCI-PCID30:F0) ............................................................................42311.1.12 SECSTSSecondary Status Register (PCI-PCID30:F0) .........................42411.1.13 MEMBASE_LIMITMemory Base and Limit Register

(PCI-PCID30:F0) ............................................................................42511.1.14 PREF_MEM_BASE_LIMITPrefetchable Memory Base

and Limit Register (PCI-PCID30:F0) ..................................................42511.1.15 PMBU32Prefetchable Memory Base Upper 32 Bits

Register (PCI-PCID30:F0) ................................................................42611.1.16 PMLU32Prefetchable Memory Limit Upper 32 Bits

Register (PCI-PCID30:F0) ................................................................42611.1.17 CAPPCapability List Pointer Register (PCI-PCID30:F0) .......................42611.1.18 INTRInterrupt Information Register (PCI-PCID30:F0)........................42611.1.19 BCTRLBridge Control Register (PCI-PCID30:F0) ...............................42711.1.20 SPDHSecondary PCI Device Hiding Register

(PCI-PCID30:F0) ............................................................................42811.1.21 DTCDelayed Transaction Control Register

(PCI-PCID30:F0) ............................................................................42911.1.22 BPSBridge Proprietary Status Register

(PCI-PCID30:F0) ............................................................................43011.1.23 BPCBridge Policy Configuration Register

(PCI-PCID30:F0) ............................................................................43111.1.24 SVCAPSubsystem Vendor Capability Register

(PCI-PCID30:F0) ............................................................................432

Datasheet 11

11.1.25 SVIDSubsystem Vendor IDs Register (PCI-PCID30:F0) ..................... 433

12 Gigabit LAN Configuration Registers ...................................................................... 43512.1 Gigabit LAN Configuration Registers

(Gigabit LAN D25:F0)................................................................................... 43512.1.1 VIDVendor Identification Register

(Gigabit LAND25:F0) ...................................................................... 43612.1.2 DIDDevice Identification Register

(Gigabit LAND25:F0) ...................................................................... 43612.1.3 PCICMDPCI Command Register

(Gigabit LAND25:F0) ...................................................................... 43712.1.4 PCISTSPCI Status Register

(Gigabit LAND25:F0) ...................................................................... 43812.1.5 RIDRevision Identification Register

(Gigabit LAND25:F0) ...................................................................... 43912.1.6 CCClass Code Register

(Gigabit LAND25:F0) ...................................................................... 43912.1.7 CLSCache Line Size Register

(Gigabit LAND25:F0) ...................................................................... 43912.1.8 PLTPrimary Latency Timer Register

(Gigabit LAND25:F0) ...................................................................... 43912.1.9 HEADTYPHeader Type Register

(Gigabit LAND25:F0) ...................................................................... 43912.1.10 MBARAMemory Base Address Register A

(Gigabit LAND25:F0) ...................................................................... 44012.1.11 MBARBMemory Base Address Register B

(Gigabit LAND25:F0) ...................................................................... 44012.1.12 MBARCMemory Base Address Register C

(Gigabit LAND25:F0) ...................................................................... 44112.1.13 SVIDSubsystem Vendor ID Register

(Gigabit LAND25:F0) ...................................................................... 44112.1.14 SIDSubsystem ID Register

(Gigabit LAND25:F0) ...................................................................... 44112.1.15 ERBAExpansion ROM Base Address Register

(Gigabit LAND25:F0) ...................................................................... 44112.1.16 CAPPCapabilities List Pointer Register

(Gigabit LAND25:F0) ...................................................................... 44212.1.17 INTRInterrupt Information Register

(Gigabit LAND25:F0) ...................................................................... 44212.1.18 MLMGMaximum Latency/Minimum Grant Register

(Gigabit LAND25:F0) ...................................................................... 44212.1.19 CLIST1Capabilities List Register 1

(Gigabit LAND25:F0) ...................................................................... 44212.1.20 PMCPCI Power Management Capabilities Register

(Gigabit LAND25:F0) ...................................................................... 44312.1.21 PMCSPCI Power Management Control and Status

Register (Gigabit LAND25:F0) .......................................................... 44412.1.22 DRData Register

(Gigabit LAND25:F0) ...................................................................... 44512.1.23 CLIST2Capabilities List Register 2

(Gigabit LAND25:F0) ...................................................................... 44512.1.24 MCTLMessage Control Register

(Gigabit LAND25:F0) ...................................................................... 44512.1.25 MADDLMessage Address Low Register

(Gigabit LAND25:F0) ...................................................................... 44612.1.26 MADDHMessage Address High Register

(Gigabit LAND25:F0) ...................................................................... 44612.1.27 MDATMessage Data Register

(Gigabit LAND25:F0) ...................................................................... 44612.1.28 FLRCAPFunction Level Reset Capability

(Gigabit LAND25:F0) ...................................................................... 44612.1.29 FLRCLVFunction Level Reset Capability Length and

Version Register (Gigabit LAND25:F0)............................................... 44712.1.30 DEVCTRLDevice Control Register (Gigabit LAND25:F0) ..................... 447

12 Datasheet

13 LPC Interface Bridge Registers (D31:F0) ...............................................................44913.1 PCI Configuration Registers (LPC I/FD31:F0) ....................................................449

13.1.1 VIDVendor Identification Register (LPC I/FD31:F0)...........................45013.1.2 DIDDevice Identification Register (LPC I/FD31:F0) ...........................45013.1.3 PCICMDPCI COMMAND Register (LPC I/FD31:F0) .............................45113.1.4 PCISTSPCI Status Register (LPC I/FD31:F0) ....................................45113.1.5 RIDRevision Identification Register (LPC I/FD31:F0) .........................45213.1.6 PIProgramming Interface Register (LPC I/FD31:F0) ..........................45213.1.7 SCCSub Class Code Register (LPC I/FD31:F0)..................................45313.1.8 BCCBase Class Code Register (LPC I/FD31:F0).................................45313.1.9 PLTPrimary Latency Timer Register (LPC I/FD31:F0).........................45313.1.10 HEADTYPHeader Type Register (LPC I/FD31:F0)...............................45313.1.11 SSSub System Identifiers Register (LPC I/FD31:F0)..........................45413.1.12 PMBASEACPI Base Address Register (LPC I/FD31:F0) .......................45413.1.13 ACPI_CNTLACPI Control Register (LPC I/F D31:F0)..........................45513.1.14 GPIOBASEGPIO Base Address Register (LPC I/F D31:F0)..................45513.1.15 GCGPIO Control Register (LPC I/F D31:F0).....................................45613.1.16 PIRQ[n]_ROUTPIRQ[A,B,C,D] Routing Control Register

(LPC I/FD31:F0) .............................................................................45713.1.17 SIRQ_CNTLSerial IRQ Control Register

(LPC I/FD31:F0) .............................................................................45813.1.18 PIRQ[n]_ROUTPIRQ[E,F,G,H] Routing Control Register

(LPC I/FD31:F0) .............................................................................45913.1.19 LPC_IBDFIOxAPIC Bus:Device:Function

(LPC I/FD31:F0) .............................................................................45913.1.20 LPC_HnBDFHPET n Bus:Device:Function

(LPC I/FD31:F0) .............................................................................46013.1.21 LPC_I/O_DECI/O Decode Ranges Register

(LPC I/FD31:F0) .............................................................................46113.1.22 LPC_ENLPC I/F Enables Register (LPC I/FD31:F0).............................46213.1.23 GEN1_DECLPC I/F Generic Decode Range 1 Register

(LPC I/FD31:F0) .............................................................................46313.1.24 GEN2_DECLPC I/F Generic Decode Range 2 Register

(LPC I/FD31:F0) .............................................................................46313.1.25 GEN3_DECLPC I/F Generic Decode Range 3 Register

(LPC I/FD31:F0) .............................................................................46413.1.26 GEN4_DECLPC I/F Generic Decode Range 4 Register

(LPC I/FD31:F0) .............................................................................46413.1.27 ULKMC USB Legacy Keyboard / Mouse

Control Register (LPC I/FD31:F0)......................................................46513.1.28 LGMR LPC I/F Generic Memory Range Register

(LPC I/FD31:F0) .............................................................................46613.1.29 BIOS_SEL1BIOS Select 1 Register

(LPC I/FD31:F0) .............................................................................46713.1.30 BIOS_SEL2BIOS Select 2 Register

(LPC I/FD31:F0) .............................................................................46813.1.31 BIOS_DEC_EN1BIOS Decode Enable

Register (LPC I/FD31:F0).................................................................46913.1.32 BIOS_CNTLBIOS Control Register

(LPC I/FD31:F0) .............................................................................47113.1.33 FDCAPFeature Detection Capability ID Register

(LPC I/FD31:F0) .............................................................................47213.1.34 FDLENFeature Detection Capability Length Register

(LPC I/FD31:F0) .............................................................................47213.1.35 FDVERFeature Detection Version Register

(LPC I/FD31:F0) .............................................................................47213.1.36 FVECIDXFeature Vector Index Register

(LPC I/FD31:F0) .............................................................................47213.1.37 FVECDFeature Vector Data Register

(LPC I/FD31:F0) .............................................................................47313.1.38 Feature Vector Space.........................................................................473

13.1.38.1 FVEC0Feature Vector Register 0 ........................................47313.1.38.2 FVEC1Feature Vector Register 1 ........................................47413.1.38.3 FVEC2Feature Vector Register 2 ........................................47413.1.38.4 FVEC3Feature Vector Register 3 ........................................475

13.1.39 RCBARoot Complex Base Address Register (LPC I/FD31:F0) .............................................................................475

Datasheet 13

13.2 DMA I/O Registers........................................................................................... 47613.2.1 DMABASE_CADMA Base and Current Address Registers ....................... 47713.2.2 DMABASE_CCDMA Base and Current Count Registers.......................... 47813.2.3 DMAMEM_LPDMA Memory Low Page Registers ................................... 47813.2.4 DMACMDDMA Command Register ..................................................... 47913.2.5 DMASTADMA Status Register ........................................................... 47913.2.6 DMA_WRSMSKDMA Write Single Mask Register .................................. 48013.2.7 DMACH_MODEDMA Channel Mode Register........................................ 48013.2.8 DMA Clear Byte Pointer Register ......................................................... 48113.2.9 DMA Master Clear Register ................................................................. 48113.2.10 DMA_CLMSKDMA Clear Mask Register ............................................... 48113.2.11 DMA_WRMSKDMA Write All Mask Register ......................................... 482

13.3 Timer I/O Registers ......................................................................................... 48213.3.1 TCWTimer Control Word Register ..................................................... 48313.3.2 SBYTE_FMTInterval Timer Status Byte Format Register ....................... 48513.3.3 Counter Access Ports Register............................................................. 486

13.4 8259 Interrupt Controller (PIC) Registers ........................................................... 48613.4.1 Interrupt Controller I/O MAP............................................................... 48613.4.2 ICW1Initialization Command Word 1 Register .................................... 48713.4.3 ICW2Initialization Command Word 2 Register .................................... 48813.4.4 ICW3Master Controller Initialization Command

Word 3 Register................................................................................ 48813.4.5 ICW3Slave Controller Initialization Command

Word 3 Register................................................................................ 48913.4.6 ICW4Initialization Command Word 4 Register .................................... 48913.4.7 OCW1Operational Control Word 1 (Interrupt Mask)

Register........................................................................................... 49013.4.8 OCW2Operational Control Word 2 Register ........................................ 49013.4.9 OCW3Operational Control Word 3 Register ........................................ 49113.4.10 ELCR1Master Controller Edge/Level Triggered Register ........................ 49213.4.11 ELCR2Slave Controller Edge/Level Triggered Register.......................... 493

13.5 Advanced Programmable Interrupt Controller (APIC)............................................ 49413.5.1 APIC Register Map ............................................................................ 49413.5.2 INDIndex Register.......................................................................... 49413.5.3 DATData Register........................................................................... 49513.5.4 EOIREOI Register ........................................................................... 49513.5.5 IDIdentification Register.................................................................. 49613.5.6 VERVersion Register ....................................................................... 49613.5.7 REDIR_TBLRedirection Table Register ............................................... 497

13.6 Real Time Clock Registers................................................................................. 49913.6.1 I/O Register Address Map .................................................................. 49913.6.2 Indexed Registers ............................................................................. 500

13.6.2.1 RTC_REGARegister A....................................................... 50113.6.2.2 RTC_REGBRegister B (General Configuration) ..................... 50213.6.2.3 RTC_REGCRegister C (Flag Register) ................................. 50313.6.2.4 RTC_REGDRegister D (Flag Register) ................................. 503

13.7 Processor Interface Registers ............................................................................ 50413.7.1 NMI_SCNMI Status and Control Register ........................................... 50413.7.2 NMI_ENNMI Enable (and Real Time Clock Index)

Register........................................................................................... 50513.7.3 PORT92Fast A20 and Init Register .................................................... 50513.7.4 COPROC_ERRCoprocessor Error Register ........................................... 50513.7.5 RST_CNTReset Control Register ....................................................... 506

13.8 Power Management Registers ........................................................................... 50713.8.1 Power Management PCI Configuration Registers

(PMD31:F0)................................................................................... 50713.8.1.1 GEN_PMCON_1General PM Configuration 1 Register

(PMD31:F0) ................................................................... 50813.8.1.2 GEN_PMCON_2General PM Configuration 2 Register

(PMD31:F0) ................................................................... 50913.8.1.3 GEN_PMCON_3General PM Configuration 3 Register

(PMD31:F0) ................................................................... 51013.8.1.4 GEN_PMCON_LOCKGeneral Power Management

Configuration Lock Register................................................. 51413.8.1.5 CIR4Chipset Initialization Register 4 (PMD31:F0).............. 51413.8.1.6 BM_BREAK_EN_2 Register #2 (PMD31:F0)......................... 51413.8.1.7 BM_BREAK_EN Register (PMD31:F0) ................................. 515

14 Datasheet

13.8.1.8 PMIRPower Management Initialization Register (PMD31:F0)51613.8.1.9 GPIO_ROUTGPIO Routing Control Register

(PMD31:F0)....................................................................51613.8.2 APM I/O Decode Register....................................................................517

13.8.2.1 APM_CNTAdvanced Power Management Control Port Register............................................................................517

13.8.2.2 APM_STSAdvanced Power Management Status Port Register............................................................................517

13.8.3 Power Management I/O Registers ........................................................51813.8.3.1 PM1_STSPower Management 1 Status Register ...................51913.8.3.2 PM1_ENPower Management 1 Enable Register.....................52113.8.3.3 PM1_CNTPower Management 1 Control Register ..................52213.8.3.4 PM1_TMRPower Management 1 Timer Register ....................52313.8.3.5 GPE0_STSGeneral Purpose Event 0 Status Register..............52413.8.3.6 GPE0_ENGeneral Purpose Event 0 Enables Register .............52713.8.3.7 SMI_ENSMI Control and Enable Register.............................52913.8.3.8 SMI_STSSMI Status Register ............................................53113.8.3.9 ALT_GP_SMI_ENAlternate GPI SMI Enable Register..............53313.8.3.10 ALT_GP_SMI_STSAlternate GPI SMI Status Register ............53413.8.3.11 GPE_CNTLGeneral Purpose Control Register ........................53413.8.3.12 DEVACT_STS Device Activity Status Register .....................53513.8.3.13 PM2_CNTPower Management 2 Control Register ..................535

13.9 System Management TCO Registers ...................................................................53613.9.1 TCO_RLDTCO Timer Reload and Current Value Register .......................53613.9.2 TCO_DAT_INTCO Data In Register ....................................................53713.9.3 TCO_DAT_OUTTCO Data Out Register ...............................................53713.9.4 TCO1_STSTCO1 Status Register .......................................................53713.9.5 TCO2_STSTCO2 Status Register .......................................................53913.9.6 TCO1_CNTTCO1 Control Register ......................................................54013.9.7 TCO2_CNTTCO2 Control Register ......................................................54113.9.8 TCO_MESSAGE1 and TCO_MESSAGE2 Registers ....................................54113.9.9 TCO_WDCNTTCO Watchdog Control Register ......................................54213.9.10 SW_IRQ_GENSoftware IRQ Generation Register .................................54213.9.11 TCO_TMRTCO Timer Initial Value Register..........................................542

13.10 General Purpose I/O Registers...........................................................................54313.10.1 GPIO_USE_SELGPIO Use Select Register ...........................................54413.10.2 GP_IO_SELGPIO Input/Output Select Register ....................................54413.10.3 GP_LVLGPIO Level for Input or Output Register ..................................54513.10.4 GPO_BLINKGPO Blink Enable Register ...............................................54513.10.5 GP_SER_BLINKGP Serial Blink Register..............................................54613.10.6 GP_SB_CMDSTSGP Serial Blink Command

Status Register .................................................................................54613.10.7 GP_SB_DATAGP Serial Blink Data Register .........................................54713.10.8 GPI_NMI_ENGPI NMI Enable Register ................................................54713.10.9 GPI_NMI_STSGPI NMI Status Register...............................................54713.10.10 GPI_INVGPIO Signal Invert Register..................................................54813.10.11 GPIO_USE_SEL2GPIO Use Select 2 Register .......................................54813.10.12 GP_IO_SEL2GPIO Input/Output Select 2 Register ...............................54913.10.13 GP_LVL2GPIO Level for Input or Output 2 Register..............................54913.10.14 GPIO_USE_SEL3GPIO Use Select 3 Register .......................................55013.10.15 GPIO_SEL3GPIO Input/Output Select 3 Register .................................55013.10.16 GP_LVL3GPIO Level for Input or Output 3 Register..............................55113.10.17 GP_RST_SEL1GPIO Reset Select Register...........................................55113.10.18 GP_RST_SEL2GPIO Reset Select Register...........................................55213.10.19 GP_RST_SEL3GPIO Reset Select Register...........................................552

14 SATA Controller Registers (D31:F2) .......................................................................55314.1 PCI Configuration Registers (SATAD31:F2) ........................................................553

14.1.1 VIDVendor Identification Register (SATAD31:F2)..............................55514.1.2 DIDDevice Identification Register (SATAD31:F2) ..............................55514.1.3 PCICMDPCI Command Register (SATAD31:F2)..................................55514.1.4 PCISTS PCI Status Register (SATAD31:F2) ......................................55614.1.5 RIDRevision Identification Register (SATAD31:F2)............................55714.1.6 PIProgramming Interface Register (SATAD31:F2)..............................557

14.1.6.1 When Sub Class Code Register (D31:F2:Offset 0Ah) = 01h......55714.1.6.2 When Sub Class Code Register (D31:F2:Offset 0Ah) = 04h......55714.1.6.3 When Sub Class Code Register (D31:F2:Offset 0Ah) = 06h......558

Datasheet 15

14.1.7 SCCSub Class Code Register (SATAD31:F2) ..................................... 55814.1.8 BCCBase Class Code Register

(SATAD31:F2SATAD31:F2) ............................................................. 55814.1.9 PMLTPrimary Master Latency Timer Register

(SATAD31:F2) ................................................................................ 55914.1.10 HTYPEHeader Type Register

(SATAD31:F2) ................................................................................ 55914.1.11 PCMD_BARPrimary Command Block Base Address

Register (SATAD31:F2) .................................................................... 55914.1.12 PCNL_BARPrimary Control Block Base Address Register

(SATAD31:F2) ................................................................................ 56014.1.13 SCMD_BARSecondary Command Block Base Address

Register (SATA D31:F2)..................................................................... 56014.1.14 SCNL_BARSecondary Control Block Base Address

Register (SATA D31:F2)..................................................................... 56014.1.15 BARLegacy Bus Master Base Address Register

(SATAD31:F2) ................................................................................ 56114.1.16 ABAR/SIDPBA1AHCI Base Address Register/Serial ATA

Index Data Pair Base Address (SATAD31:F2) ...................................... 56114.1.16.1 When SCC is not 01h ......................................................... 56114.1.16.2 When SCC is 01h............................................................... 562

14.1.17 SVIDSubsystem Vendor Identification Register (SATAD31:F2) ................................................................................ 562

14.1.18 SIDSubsystem Identification Register (SATAD31:F2)......................... 56214.1.19 CAPCapabilities Pointer Register (SATAD31:F2) ................................ 56214.1.20 INT_LNInterrupt Line Register (SATAD31:F2)................................... 56314.1.21 INT_PNInterrupt Pin Register (SATAD31:F2) .................................... 56314.1.22 IDE_TIMIDE Timing Register (SATAD31:F2) ..................................... 56314.1.23 PIDPCI Power Management Capability Identification

Register (SATAD31:F2) .................................................................... 56314.1.24 PCPCI Power Management Capabilities Register

(SATAD31:F2) ................................................................................ 56414.1.25 PMCSPCI Power Management Control and Status

Register (SATAD31:F2) .................................................................... 56514.1.26 MSICIMessage Signaled Interrupt Capability

Identification Register (SATAD31:F2)................................................. 56614.1.27 MSIMCMessage Signaled Interrupt Message

Control Register (SATAD31:F2) ......................................................... 56614.1.28 MSIMA Message Signaled Interrupt Message

Address Register (SATAD31:F2) ........................................................ 56814.1.29 MSIMDMessage Signaled Interrupt Message

Data Register (SATAD31:F2) ............................................................ 56814.1.30 MAPAddress Map Register (SATAD31:F2)......................................... 56914.1.31 PCSPort Control and Status Register (SATAD31:F2) .......................... 57014.1.32 SCLKCGSATA Clock Gating Control Register ....................................... 57214.1.33 SCLKGCSATA Clock General Configuration Register............................. 57214.1.34 SATACR0SATA Capability Register 0 (SATAD31:F2)........................... 57314.1.35 SATACR1SATA Capability Register 1 (SATAD31:F2)........................... 57414.1.36 FLRCIDFLR Capability ID Register (SATAD31:F2) .............................. 57414.1.37 FLRCLVFLR Capability Length and Version Register

(SATAD31:F2) ................................................................................ 57514.1.38 FLRCFLR Control Register (SATAD31:F2) ......................................... 57514.1.39 ATCAPM Trapping Control Register (SATAD31:F2)............................. 57614.1.40 ATSAPM Trapping Status Register (SATAD31:F2) .............................. 57614.1.41 SP Scratch Pad Register (SATAD31:F2) .............................................. 57614.1.42 BFCSBIST FIS Control/Status Register (SATAD31:F2)........................ 57714.1.43 BFTD1BIST FIS Transmit Data1 Register (SATAD31:F2)..................... 57914.1.44 BFTD2BIST FIS Transmit Data2 Register (SATAD31:F2)..................... 579

14.2 Bus Master IDE I/O Registers (D31:F2) .............................................................. 58014.2.1 BMIC[P,S]Bus Master IDE Command Register (D31:F2)....................... 58114.2.2 BMIS[P,S]Bus Master IDE Status Register (D31:F2)............................ 58214.2.3 BMID[P,S]Bus Master IDE Descriptor Table Pointer

Register (D31:F2) ............................................................................. 58314.2.4 AIRAHCI Index Register (D31:F2) .................................................... 58314.2.5 AIDRAHCI Index Data Register (D31:F2)........................................... 583

14.3 Serial ATA Index/Data Pair Superset Registers .................................................... 58414.3.1 SINDXSerial ATA Index Register (D31:F2) ......................................... 584

16 Datasheet

14.3.2 SDATASerial ATA Data Register (D31:F2)...........................................58514.3.2.1 PxSSTSSerial ATA Status Register (D31:F2)........................58514.3.2.2 PxSCTLSerial ATA Control Register (D31:F2) .......................58614.3.2.3 PxSERRSerial ATA Error Register (D31:F2)..........................587

14.4 AHCI Registers (D31:F2) ..................................................................................58814.4.1 AHCI Generic Host Control Registers (D31:F2) ......................................589

14.4.1.1 CAPHost Capabilities Register (D31:F2) ..............................59014.4.1.2 GHCGlobal PCH Control Register (D31:F2) ..........................59214.4.1.3 ISInterrupt Status Register (D31:F2) .................................59314.4.1.4 PIPorts Implemented Register (D31:F2) .............................59414.4.1.5 VSAHCI Version Register (D31:F2) ....................................59514.4.1.6 EM_LOCEnclosure Management Location Register (D31:F2) ..59514.4.1.7 EM_CTRLEnclosure Management Control Register (D31:F2) ..59614.4.1.8 CAP2HBA Capabilities Extended Register ............................59714.4.1.9 VSPVendor Specific Register (D31:F2)................................59714.4.1.10 RSTFIntel RST Feature Capabilities Register......................598

14.4.2 Port Registers (D31:F2) .....................................................................59914.4.2.1 PxCLBPort [5:0] Command List Base Address Register

(D31:F2) ..........................................................................60214.4.2.2 PxCLBUPort [5:0] Command List Base Address Upper

32-Bits Register (D31:F2) ...................................................60214.4.2.3 PxFBPort [5:0] FIS Base Address Register (D31:F2).............60214.4.2.4 PxFBUPort [5:0] FIS Base Address Upper 32-Bits

Register (D31:F2) ..............................................................60314.4.2.5 PxISPort [5:0] Interrupt Status Register (D31:F2) ...............60314.4.2.6 PxIEPort [5:0] Interrupt Enable Register (D31:F2)...............60514.4.2.7 PxCMDPort [5:0] Command Register (D31:F2) ....................60614.4.2.8 PxTFDPort [5:0] Task File Data Register (D31:F2) ...............60914.4.2.9 PxSIGPort [5:0] Signature Register (D31:F2)......................60914.4.2.10 PxSSTSPort [5:0] Serial ATA Status Register (D31:F2) .........61014.4.2.11 PxSCTL Port [5:0] Serial ATA Control Register (D31:F2) ......61114.4.2.12 PxSERRPort [5:0] Serial ATA Error Register (D31:F2)...........61214.4.2.13 PxSACTPort [5:0] Serial ATA Active Register (D31:F2) .........61414.4.2.14 PxCIPort [5:0] Command Issue Register (D31:F2) ...............614

15 SATA Controller Registers (D31:F5) .......................................................................61515.1 PCI Configuration Registers (SATAD31:F5) ........................................................615

15.1.1 VIDVendor Identification Register (SATAD31:F5)..............................61615.1.2 DIDDevice Identification Register (SATAD31:F5) ..............................61615.1.3 PCICMDPCI Command Register (SATAD31:F5)..................................61715.1.4 PCISTS PCI Status Register (SATAD31:F5) ......................................61815.1.5 RIDRevision Identification Register (SATAD31:F5)............................61815.1.6 PIProgramming Interface Register (SATAD31:F5)..............................61915.1.7 SCCSub Class Code Register (SATAD31:F5)......................................61915.1.8 BCCBase Class Code Register

(SATAD31:F5SATAD31:F5) .............................................................61915.1.9 PMLTPrimary Master Latency Timer Register

(SATAD31:F5).................................................................................62015.1.10 PCMD_BARPrimary Command Block Base Address

Register (SATAD31:F5) ....................................................................62015.1.11 PCNL_BARPrimary Control Block Base Address Register

(SATAD31:F5).................................................................................62015.1.12 SCMD_BARSecondary Command Block Base Address

Register (SATA D31:F5) .....................................................................62115.1.13 SCNL_BARSecondary Control Block Base Address

Register (SATA D31:F5) .....................................................................62115.1.14 BARLegacy Bus Master Base Address Register

(SATAD31:F5).................................................................................62215.1.15 SIDPBASATA Index/Data Pair Base Address Register

(SATAD31:F5).................................................................................62215.1.16 SVIDSubsystem Vendor Identification Register

(SATAD31:F5).................................................................................62315.1.17 SIDSubsystem Identification Register (SATAD31:F5) .........................62315.1.18 CAPCapabilities Pointer Register (SATAD31:F5).................................62315.1.19 INT_LNInterrupt Line Register (SATAD31:F5) ...................................62315.1.20 INT_PNInterrupt Pin Register (SATAD31:F5).....................................62315.1.21 IDE_TIMIDE Timing Register (SATAD31:F5) .....................................624

Datasheet 17

15.1.22 PIDPCI Power Management Capability IdentificationRegister (SATAD31:F5) .................................................................... 624

15.1.23 PCPCI Power Management Capabilities Register (SATAD31:F5) ................................................................................ 624

15.1.24 PMCSPCI Power Management Control and StatusRegister (SATAD31:F5) .................................................................... 625

15.1.25 MAPAddress Map Register (SATAD31:F5)......................................... 62615.1.26 PCSPort Control and Status Register (SATAD31:F5) .......................... 62715.1.27 SATACR0 SATA Capability Register 0 (SATAD31:F5).......................... 62815.1.28 SATACR1 SATA Capability Register 1 (SATAD31:F5).......................... 62815.1.29 FLRCID FLR Capability ID Register (SATAD31:F5) ............................. 62815.1.30 FLRCLV FLR Capability Length and

Value Register (SATAD31:F5) ........................................................... 62915.1.31 FLRCTRL F