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Copyright © 2013 American Scientific PublishersAll rights reservedPrinted in the United States of America

Journal ofNanoscience and Nanotechnology

Vol. 13, 3638–3640, 2013

Integrated Memristor-MOS (M2� Sensor forBasic Pattern Matching Applications

Omid Kavehei1, Kyoung-Rok Cho2�∗, Sang-Jin Lee2, Said Al-Sarawi3,Kamran Eshraghian2, and Derek Abbott3

1Centre for Neural Engineering, The University of Melbourne, VIC 3010, Australia2School of Electrical and Electronic Engineering, The University of Adelaide, SA 5005, Australia

3College of Electrical and Information Engineering, WCU Program,Chungbuk National University, Cheongju, 361-763, Korea

This paper introduces an integrated sensor circuit based on an analog Memristor-MOS (M2� pat-tern matching building block that calculates the similarity/dissimilarity between two analog values.A new approach for a pulse-width modulation pixel image sensor compatible with the memristive-MOS matching structure is introduced allowing direct comparison between incoming and storedimages. The pulsed-width encoded information from the pixels is forwarded to a matching circuitrythat provides an anti-Gaussian-like comparison between the states of memristors. The non-volatileand multi-state memory characteristics of memristor, together with the related ability to be pro-grammed at any one of the intermediate states between logic ‘1’ and logic ‘0’ brings us closer tothe implementation of bio-machines that can eventually emulate human-like sensory functions.

Keywords: Memristor, Pattern Matching, Non-Volatile Memory, TiO2, Thin Films.

1. INTRODUCTION

The increasing demand for ultra-dense chips, high-speedcommunication, and high storage creates a need for 3-Dintegrated architectures providing an option for higher lev-els of integration. High power consumption, and coolingtechniques, addressing modes, coding and decoding datastructures, and transferring data from a non-volatile type ofmemory to RAM (Random Access memory) type memo-ries at high speed create numerous complexities for futureintegrated systems. Numerous approaches have been pro-posed for pattern matching, recognition, and classificationthat are based on VLSI implementation as a common toolin many applications, including object recognition, stereomatching, and object tracking.However, despite advances in technology, hardware

implementation of an integrated sensory system remainas a barrier. The recent emergence of the memristor, the4th fundamental element,1�2 creates an opportunity forincreased integration density beyond the present limits ofCMOS scaling.In this paper a basic block for a sensor with applica-

tion in pattern recognition systems is proposed that com-bines the inherent memory behavior of memristors3 and

∗Author to whom correspondence should be addressed.

the computational functionality of MOS transistor as partof a smart sensory system. In the pattern recognition, thegoal is to identify a mapping function, h��→�, that mapsinputs � ∈ A to templates � ∈ B or generally to a numberof categories Cj , where j ∈ N .

The � and � vectors can be written in terms of nor-malized state variables wi and wt for the input mem-ristor Mi and template memristor Mt , respectively, asshown in Figure 1(a), where �= �w

�1�i �w

�2�i � �w

�n2�i and

�= �w�1��y�t �w

�2��y�t � �w

�n2��y�t .

The w�j�i variable represents the j-th instance of the input

vector, �, which corresponds to an input pixel value, andw

�x��y�t variable demonstrates the x-th instance of the y-th

template vector, where x= 1�2� � n2, y= 1�2� �m, n2

is the size of each vector, andm is the number of templates.The proposed sensory part of the imaging circuit com-

bines both the image sensor and pattern matching circuitryas a single entity. The computational process is performedin three steps: (1) Light-to-time conversion phase by theimage sensor. (2) Programming phase by memristor, and(3) Computational phase or matching process by M2 block.The imager has been implemented and fabricated using013 �m Samsung Electronics standard CMOS processdeveloped specifically for CMOS mixed-signal circuits.With reference to Figure 1, the imager raw data is fedto analog matching circuitry whereby the light output is

3638 J. Nanosci. Nanotechnol. 2013, Vol. 13, No. 5 1533-4880/2013/13/3638/003 doi:10.1166/jnn.2013.7295

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Kavehei et al. Integrated Memristor-MOS (M2� Sensor for Basic Pattern Matching Applications

Fig. 1. Block diagram of the proposed integrated memristor-MOS (M2) sensory circuit for pattern matching and recognition. (a) Single cell circuitand the sensor layout. (b) Micrograph of the pixel array.

encoded into a variable pulse widths determined by thelevel of light intensities. This signal changes the internalstate of memristor, Mi, and hence its conductance. Thestored template state is also encoded in memrisor Mt .Comparison between the two memristors states defines

the distance between the two image vectors, � and�. Memristor-based device SPICE simulations (CadenceSpectre) were used to verify the functionality.2–4

In this paper, a memristive device is a bipolar Resis-tive Random Access Memory (ReRAM) that its underlyingphysics of switching and/or gradual change of resistancecan be described based on either Valance Change Memory

Fig. 2. Simulated circuit response as a function of light intensity. Explanation of subfigures is provided within the text.

(VCM) or Electrochemical Metalization (ECM)systems.Each cell contains one transistor and one ReRAM device(1T1R).

2. INTEGRATED MEMRISTOR-MOSSENSORY CIRCUIT

The basic CMOS image sensor pixel, memristor-MOSanalog comparator schematics, and the pixel layout areillustrated in Figure 1(a). The micrograph of the fabricated64×64 CMOS image sensor chip is shown in Figure 1(b).5

Initially, the incident light is converted to time that appears

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Integrated Memristor-MOS (M2� Sensor for Basic Pattern Matching Applications Kavehei et al.

at the output. The offset voltage introduced by the inclu-sion of an inverter instead of the more complex comparatoris removed by inclusion of nMOS transistor, Mof , whilethe pixel is in its reset phase. The ‘tx’ signal is enabled andremains high for the entire integration period, Tint. In oursimulations Tint ≈ 2 ms.The flushed-based reset approach reduces the reset noise

and eliminates the possibility of image lag, which is aserious problem in image recognition systems.Figure 2(a) demonstrates the behavior of the expected

mapping function, h�·�, that corresponds to current Ioutwhich is a function of �w = wt −wi. The template mem-ristor’s state variable, wt , is programmed at 05. In thiscase, once wi corresponds to a perfect match, wi = 05and �w ≈ 0. In the absence of a perfect match, lowestIout shows the nearest match that can be attained. Sucha behavior is brought about by PMt −NMi and PMi −NMt transistor pairs in the cross-coupled structure. Animportant part of the computation phase is the applica-tion of an input ramp, Vin, for the matching duration, tm =10 �s. At each step the applied voltage corresponds toVDD = 08 V. Applying this input ramp to the two pMOSpull-up transistors in the memristive inverters structures,Pi and Pt , mimics the behavior of switching and translatesthe stored states into a time difference between switchingpoints Si and St shown in Figure 1(a). The VSS node illus-trates switching between ground and initialization voltageto program wi at 005.In our simulations, low light levels correspond to mem-

ristor’s high states (wi → 095� and conversely high lightlevels correspond to low states (wi → 005�, as shownin Figure 2(b). Programming of memristor state, wi, asa function of total photo current shows a capability ofwriting analog data for each particular light intensity. Thecurve in Figure 2(c) highlights a valley based on the pro-gramming steps of wi as a function of the incident light.High light levels write low values in wi, so the valleyoccurs when wt is close to its low states. When wt hasa high value low light illuminations result a better match(wt and wi ∈ 005�095��. The same scenario is applicablefor the intermediate states.The output currents from an array of parallel pixels

are subsequently summed to identify either similarity or

dissimilarity between incoming and stored images. Thus,the expected mapping function uses this information tomap the input pattern, A, to y-th template, By , and/or cat-egorizing A in j-th class, Cj .It worth mentioning that precise programming of mem-

ristive devices in different analog values is possible andhas already been proven experimentally.3

3. CONCLUSION

An integrated memristor-MOS smart sensor block aspart of a pattern recognition has been introduced thatintegrates the multi-state non-volatile memory character-istics of memristor as part of an analog similarity detec-tion circuitry. The integrated structure is based on a newsingle-inverter pulse-width modulation whereby the lightis converted into memristor states. The proposed approachis highly suitable for implementation in pattern recognizersand pattern matching architecture.

Acknowledgment: Image sensor fabrication in thiswork was supported by IDEC and the World Class Univer-sity (WCU) project of MEST and KOSEF through CBNUunder grant No. R33-2008-000-1040-0 and the School ofElectrical and Electronic Engineering of Adelaide Univer-sity, through the Simon Rockliff Scholarship and an earlycareer research grant from Melbourne School of Engi-neering, The University of Melbourne. This work (20110015702) was supported by Mid-career Researcher Pro-gram through NRF grant funded by the MEST.

References and Notes

1. L. O. Chua and S. M. Kang, Proceedings of the IEEE 64, 209 (1976).2. D. B. Strukov, G. S. Snider, D. R. Stewart, and R. S. Williams, Nature

453, 80 (2008).3. S. H. Jo, T. Chang, I. Ebong, B. B. Bhadviya, P. Mazumder, and

W. Lu, Nano Lett. 10, 1297 (2010).4. O. Kavehei, A. Iqbal, Y. Kim, K. Eshraghian, S. Al-Sarawi,

and D. Abbott, Proceedings of the Royal Society A 466, 2175(2010).

5. S. J. Lee, O. Kavehei, K. Eshraghian, and K. R. Cho, High fill factorCIS based on single inverter architecture, IEEE International Sym-posium on Circuits and Systems, Live Demonstration ISCAS, Seoul,Korea (2012).

Received: 7 November 2011. Accepted: 25 April 2012.

3640 J. Nanosci. Nanotechnol. 13, 3638–3640, 2013