instructional program outcome evidence … · • muhammad ali mazidi and janice gillispie mazidi,...

INSTRUCTIONAL OBJECTIVE PROGRAM OUTCOME EVIDENCE

• To Understand Microprocessor types and Programming of them

a) Graduates will demonstrate knowledge of mathematics, science and engineering. Cycle test-I

c) Graduates will demonstrate the ability to design and conduct experiments, analyze and interpret data.

Cycle test-I Qn no.13(even) & Qn no.11(odd) Lesson notes

k) Graduates will show the ability to participate and try to succeed in competitive examinations.

Tested with Objective Questions Capable of answering *competitive exams like JTO, GATE, IES etc.

• To Understand various interfacing circuits necessaay for various application

a) Graduates will demonstrate knowledge of mathematics, science and engineering. Cycle Test II and Model test

b) Graduates will demonstrate the ability to identify, formulate and solve engineering problems.

Cycle Test II and Model test


Analysed and performed experiments(no.7,8) in µp lab

d) Graduates will demonstrate the ability to design a system, component or process as per needs and specifications

Designed and performed experiments(no.5,6) in µp lab

• To Understand various interfacing concepts..


Analysed and performed experiments(no.5,6) in µp lab


Assignments on ROM and RAM memory interfacing



• To understand basic concepts of microcontroller 8051

b) Graduates will demonstrate the ability to identify, formulae and solve engineering problems.

Analysed and performed experiments(no.9) in µp lab Model test Qno.15


Model test Qno.17



Course Code Category Course Name L T P C

EC0309 P Microprocessors and Microcontrollers 3 0 0 3 Pre-requisite: EC0205

PURPOSE The purpose of this course is to introduce students about Microprocessors and Microcontrollers.

INSTRUCTIONAL OBJECTIVES • Understand Microprocessor types and programming of them • Understand various interfacing circuits necessary for various applications • Understand various interfacing concepts • Understand basic concepts of micro controller

MICROPROCESSOR - 8086 Register Organization – Architecture – Signals - Memory Organization - Bus Operation -IO Addressing - Minimum Mode - Maximum Mode - Timing Diagram - Interrupts - Service Routines

PROGRAMMING OF 8086 Addressing Modes - Instruction format - Instruction set - Assembly language programs in 8086.

INTERFACING DEVICES IO and Memory Interfacing concepts - Programmable interval timer (8254)- Programmable Interrupt Controller (8259A) - Programmable DMA Controller (8257) -Programmable communication Interface (8251) - Stepper motor interfacing.

MICROCONTROLLER-8051 Register Set - Architecture of 8051 microcontroller – I/O and memory addressing –Interrupts - Instruction set - Addressing modes.

PROGRAMMING OF 8051 Timer - Serial Communication - Interrupts Programming - Interfacing to External Memory - Interfacing to ADCs, Sensors.

TEXT BOOKS • K. Ray and K. M. Bhurchandi, "Advanced Microprocessors and Peripherals", Tata McGrawHill, 2000 • Muhammad Ali Mazidi and Janice Gillispie Mazidi, "The 8051 - Microcontroller and Embedded systems", 7th

Edition, Pearson Education, 2004

REFERENCE BOOKS • Doughlas.V.Hall, Microprocessor and Interfacing : Programming and Hardware, 2nd edition, McGraw Hill, 1991 • Kenneth.J.Ayala, 8051 Microcontroller Architecture, Programming and Applications.2nd edition, Thomson

SRM UNIVERSITY FACULTY OF ENGINEERING AND TECHNOLOGY

SCHOOL OF ELECTRICAL AND ELECTRONICS ENGINEERING DEPARTMENT OF ECE

COURSE PLAN

Course Code : EC0309 Course Title : MICROPROCESSORS AND MICROCONTROLLERS Semester : V Course Time : JULY – NOVEMBER 2012 Location : S.R.M.E.C Faculty Details Sec. Name Office Class Hour Mail id

A Mrs.J.Subhashini TP12S6 Day2- 7 Day4-2 &4 Day5-2

[email protected]

B Mrs. J. K. Kasthuri Bha TP9003

Day1-2 Day2-7 Day3-3 Day5-4

[email protected]

C Mr. Diwakar R Marur TP11S3 Day1-2 & 5 Day4-3 & 4

[email protected]

D Mrs. S. Vasanthadev Suryakala TP1003

Day1-1 Day3-3 & 7 Day5-5

[email protected]

E Mr. J.Selvakumar TP12S8 Day1- 4 & 5 Day3 -7 Day5-1

[email protected]

F Mr.E.Sivakumar TP12S9 Day1-4 Day2-4 Day4-2 & 5

[email protected]

Required Text Books

[1] A. K. Ray and K. M. Bhurchandi, “Advanced Microprocessors and Peripherals”, Tata McGrawHill, 2000. [2] Doughlas.V.Hall, Microprocessor and Interfacing : Programming and Hardware, 2nd edition, McGraw Hill,

1991 [3] Muhammad Ali Mazidi and Janice Gillispie Mazidi, “The 8051 – Microcontroller and Embedded Systems”, 7th

Edition, Pearson Education, 2004 Web Resources www.wikipedia.org www.aust.edu www.mikroe.com/en/books/8051 book.html www.dauniv.ac.in/downloads.html www.cpu-world.com/arch/8086.html www.8052.com Prerequisite : EC0205 Digital Systems

Objectives 1. To understand the architecture, programming and addressing modes of Intel 8086 . 2. To understand various interfacing circuits necessary for various applications. 3. To study the architecture of microcontroller 8051. 4. To study the instruction set and programming of 8051. 5. To understand various interfacing concepts.

Assessment Details

Cycle Test – I : 10 Marks Cycle Test – II : 10 Marks Surprise Test : 5 Marks Attendance : 5 Marks Model Exam : 20 Marks

Test Schedule

S.No. DATE TEST Portions DURATION 1. 25.07.2012 Cycle Test -I Session No. 1 to 18 2 Periods 2. 27.08.2012 Cycle Test –II Session No.19 to 27 2 Periods 3. 10.10.2012 Model Exam Session No. 1 to 45 3 hours

Outcomes Students who have successfully completed this course will be able to:

Instructional Objective Program outcome

1. To Understand the architecture, programming and addressing modes of Intel 8086 . a, d

2. To Understand various interfacing concepts and circuits necessary for various applications. b, c, d

3. To understand basic concepts of microcontroller 8051 a, b, c, d

Detailed Session Plan: Topics covered with its relationship between program objectives and program outcomes Session

No. Topics to be covered Text / chapter Instructional

Objectives Program

Objectives Program outcome

1. Register Organization [1] chapter(s) – 1 [2] chapter(s) – 2 1 2 a, k

2. Architecture of 8086 [1] chapter(s) – 1 [2] chapter(s) – 2 1 2,3 a, k

3. Architecture of 8086 [1] chapter(s) – 1 [2] chapter(s) – 2 1 2,3 a, k

4. Signals-Memory Organization

[1] chapter(s) – 1 [2] chapter(s) – 2 1 2 a, k

5. Bus Operation [1] chapter(s) – 1 [2] chapter(s) – 2 1 2 a, k

6. IO Addressing [1] chapter(s) – 1 [2] chapter(s) – 2 1 2 a

7. Minimum Mode System and Timing Diagram

[1] chapter(s) – 1 [2] chapter(s) – 2 1 3 a, d

8. Maximum Mode and Timing Diagram

[1] chapter(s) – 1 [2] chapter(s) – 2 1 3 a, d

9. Interrupts and Services Routines

[1] chapter(s) – 4 [2] chapter(s) – 8 1 2 a, k

10. Instruction format [1] chapter(s) – 2 [2] chapter(s) – 3 1 2, 3 a

11. Instruction set- Data transfer instructions

[1] chapter(s) – 2 [2] chapter(s) – 3 & 4 1 2, 3 a, c, k

12. Arithmetic instructions [1] chapter(s) – 2 [2] chapter(s) – 3 & 4 1 2, 3 a, c

13. Logical instructions [1] chapter(s) – 2 [2] chapter(s) – 3 & 4 1 2, 3 a, c

14. Branch instructions [1] chapter(s) – 2 [2] chapter(s) – 3 & 4 1 2, 3 a, c

15. Addressing modes [1] chapter(s) – 2 [2] chapter(s) – 3 1 2, 3 a, c

16. ALP for addition and subtraction of 16 bit

[1] chapter(s) – 3 [2] chapter(s) – 3 & 4 1 2, 3 a, c

17. ALP for Ascending and Descending order of numbers


18. ALP for sum of series, Fibonacci series, smallest and largest numbers


19. IO Interfacing concepts [1] chapter(s) – 5 [2] chapter(s) – 9 2 3 b, c, d, k

20. Memory Interfacing concepts [1] chapter(s) – 5 [2] chapter(s) – 9 2 3 b, c, d, k

21. Programmable interval timer (8254)

[1] chapter(s) – 6 [2] chapter(s) – 8 2 3 b, c, d, k

Session No.

Topics to be covered Text / chapter Instructional Objectives

Program Objectives

Program outcome

22. Programmable Interrupt Controller (8259A)


23. Programmable Interrupt Controller (8259A)


24. Programmable DMA Controller (8257)


25. Programmable communication Interface (8251)


26. Stepper moor interfacing [1] chapter(s) – 5 [2] chapter(s) – 9 2 3 b, c, d, k

27. Register Set [3] chapter(s) – 1 & 2 3 2 a, k

28. Architecture of 8051 microcontroller [3] chapter(s) – 1 & 2 3 2, 3 a, d, k

29. Architecture of 8051 microcontroller [3] chapter(s) – 1 & 2 3 2,3 a, d, k

30. IO and memory addressing [3] chapter(s) – 5 3 2, 3 b, c, d, k

31. Interrupts [3] chapter(s) – 1 & 11 3 2 a, c, k

32. Instruction set [3] chapter(s) – 6 3 2,3 b, c, k



35. Addressing modes. [3] chapter(s) – 5 3 2,3 b, c, k

36. Assembly Language Programming [3] chapter(s) – 6 3 2,3 a, c, k

37. Assembly Language Programming [3] chapter(s) – 6 3 2,3 a, c, k

38. Timer Programming [3] chapter(s) – 9 3 2,3 a, b, c, d, k

39. Timer Programming [3] chapter(s) – 9 3 2,3 a, b, c, d, k

40. Serial Communication [3] chapter(s) – 10 3 2,3 a, b, c, d, k

41. Interrupts Programming [3] chapter(s) – 11 3 2,3 a, b, c, d, k

42. Interfacing to External Memory [3] chapter(s) – 14 3 2,3 a, b, c, d, k

43. Interfacing to ADCs. [3] chapter(s) – 13 3 2,3 a, b, c, d

44. Interfacing to DACs [3] chapter(s) – 13 3 2,3 a, b, c, d

45. Interfacing to Sensors. [3] chapter(s) – 13 3 2,3 a, b, c, d

Program Educational Objectives

1. To prepare students to compete for a successful career in Electronics and Communication Engineering profession through global education standards.

2. To enable the students to aptly apply their acquired knowledge in basic sciences and mathematics in solving Electronics and Communication Engineering problems.

3. To produce skillful graduates to analyze, design and develop a system/component/ process for the required needs under the realistic constraints.

4. To train the students to approach ethically any multidisciplinary engineering challenges with economic, environmental and social contexts

5. To create an awareness among the students about the need for life long learning to succeed in their professional career as Electronics and Communication Engineers.

Meeting Instructional Objectives Evaluation sheet for Cycle test I

Program Name : B.Tech in Electronics and Communication Engineering Semester : Fifth semester Year : 2012 Course code and Name: EC0309 Microprocessors and Microcontrollers

Name and

Reg.number

Instructional Objective

Max Mark Assigned

Marks scored in Cycle test-I

Pass Criteria

Objective met

Yes/No

To Understand various interfacing circuits necessary for various applications.

COURSE COORDINATOR

Meeting Instructional Objectives Evaluation sheet for Cycle test II

Program Name : B.Tech in Electronics and Communication Engineering Semester : Fifth semester Year : 2012 Course code and Name: : EC0309 Microprocessors and Microcontrollers

Name Instructional Max Mark Marks scored in Cycle test- Pass Objective

and Reg.number

Objective Assigned

II

Criteria

met Yes/No


COURSE COORDINATOR

Meeting Instructional Objectives Evaluation sheet for Model exam

Program Name : B.Tech in Electronics and Communication Engineering Semester : Fifth sem Year :2012 Course code and Name: EC0309 Microprocessors and Microcontrollers

Name and register

number Instructional Objective

Max Mark Assign

Marks scored in Model exam

Pass Criteria

Objective met

Yes/No

To Understand the architecture, programming and addressing modes of Intel 8086.

40 20


30 15

To Understand various interfacing concepts 10 5

To understand basic concepts of microcontroller 8051

56 28

Total 100 50

COURSE COORDINATOR


Program Name : B.Tech in Electronics and Communication Engineering Semester : Fifth semester Year :2012 Course code and Name: EC0309 Microprocessors and Microcontrollers

Name and register

number


Max Mark Assign

Marks scored in

Model exam

Pass Criteria

Objective met Yes/No

To Understand the architecture, programming and addressing modes of Intel 8086 .

40 20

To Understand variousinterfacing circuits necessary for various applications.

30 15



56 28

Total 100 50

COURSE COORDINATOR



Name and register

number


Max Mark Assign

Marks scored in

Model exam

Pass Criteria



40 20


30 15



56 28

Total 100 50

COURSE COORDINATOR



Name and register number

Instructional Objective Max Mark Assign

Marks scored

in Model exam

Pass Criteria



40

20


30

15

To Understand various interfacing concepts 10

5


56

28

Total 100 50

COURSE COORDINATOR





Max Mark Assign (100)

Marks scored in Model exam

Pass Criteria

(50)



40 20


30 15



56 28

Total 100 50

COURSE COORDINATOR

Meeting Instructional Objectives Evaluation sheet for Surprise test 1




Max marks

Marks scored

Pass Criteria


To Understand the architecture, programming and addressing modes of Intel 8086

20

\

10

18

19

18

19

19

COURSE COORDINATOR

Meeting Instructional Objectives Evaluation sheet for Surprise test 2




Max marks

Marks scored

Pass Criteria

Objective met

Yes/No

To understand the basic concepts of microcontroller 8051

30

15

COURSE COORDINATOR





Max marks

Marks scored

Pass Criteria

Objective met

Yes/No

To understand the basic concepts of microcontroller 8051

30

15

COURSE COORDINATOR

SRM UNIVERSITY FACULTY OF ENGINEERING AND TECHNOLOGY

DEPARTMENT OF ELECTRONICS AND COMMUNICATION QUESTION BANK

SUB. CODE : EC0309 YEAR/BRANCH:III/ECE SUB. TITLE: Microprocessors & Microcontrollers SEMESTER : V __________________________________________________________________________________ 1. Draw and discuss the internal block diagram of 8086? 2. What do you meant by pipelined architecture? How is implemented in 8086? 3. Explain the concept of segmented memory? And What are its advantages? 4. Explain the physical address formation in 8086? 5. Draw and discuss the flag register of 8086 in brief? 6. Draw the register organization of 8086 and explain typical applications of each register? 7. Explain the functions of the following signals of 8086?

a) ALE b)TEST c)RQ/GT d)INTR e)HOLD f)DT/R g)MN/MX h)QS0/QS1 i)HLDA j)READY k)DEN l)BHE m)LOCK n)M/IO o)NMI

8. Explain the functions of opcode prefetch queue in 8086? 9. Explain the physical memory organization of 8086 system? 10. What is the memory addressing and IO addressing capability of 8086? 11. Draw and discuss the read and write cycle timing diagrams of 8086 in minimum mode? 12. Draw and discuss the read and write cycle timing diagrams of 8086 in maximum mode? 13. Draw and discuss the minimum mode 8086 system? 14. Draw and discuss the maximum mode 8086 system? 15. What do you mean by addressing modes? What are the different addressing modes supported by 8086? Explain each

of them with suitable examples? 16. Explain the stack structure of 8086 in detail 17. Draw and discuss the interrupt structure of 8086 in detail 18. What is interrupt vector table of 8086? Explain its structure 19. Explain the interrupt response sequence of 8086 20. How do you set or clear the interrupt flag IF? What is its importance in the interrupt structure of 8086 21. What are the interrupt vector addresses of the following interrupts in the 8086 interrupt vector table?

a)INT0 b)NMI c)INT 20h d)INT 55h 22. What are differences between hardware and software interrupt? 23. Explain the term nested interrupt. 24. How do you generate delays in a software? What are the limitations of this method of generating delays? How will

you synchronize one such delay with an external process? 25. Interface two 4K*8 EPROMS and two 4k*8 RAM chips with 8086. Select suitable maps. 26. What are the different instruction types of 8086? 27. Bring out the difference between the jump and loop instructions? 28. What is the difference between respective shifts and rotate instructions? 29. What is LOCK prefix? What is its use? 30. What is REP prefix? What is its use? 31. Explain conditional loop instructions with examples? 32. Write short notes on control transfer (Branch) instructions? 33. Add the contents of the memory location 2000:4000h to contents of 3000:6000h and store the results in 5000:7000h 34. Move a byte string, 16 bytes long, from the offset 200h to 300h in the segment 7000h? 35. Find out the largest no. from an unordered array of 16 8bit no.s stored sequentially in the memory locations starting

at offset 500h in the segment 2000h. 36. Write a program for a addition of series of 8 bit no. Draw and discuss the interrupt structure of 8086 in detail 37. What is interrupt vector table of 8086? Explain its structure 38. Explain the interrupt response sequence of 8086 39. How do yo set or clear the interrupt flag IF? What is its importance in the interrupt structure of 8086 40. What are the interrupt vector addresses of the following interrupts in the 8086 interrupt vector table?

a)INT0 b)NMI c)INT 20h d)INT 55h 41. What are differences between hardware and software interrupt?

42. Explain the term nested interrupt 43. How do you generate delays in a software? What are the limitations of this method of generating delays? How will

you synchronize one such delay with an external process? 44. The series contains 100 numbers. Write a program to find out the number of even and odd no.s from a given series of

16 bit hexadecimal numbers? 45. Write a program to find out the number of positive and negative no.s from a given series of signed numbers. 46. Write a ALP to arrange the given series of hexadecimal bytes in ascending order. 47. Write a program to perform a one byte BCD addition 48. Write a program to convert the BCD no’s 0 to 9 to their equivalent seven segment codes using the lookup table

technique. 49. Decide whether the parity of the given number is even or odd. If parity is even, set DL to 00; else DL to 01. The

given no. may be multibyte number. 50. Write a program to add more than two multibyte no.s 51. Describe the execution of a CALL instruction. 52. What is the difference between a NEAR and a FAR procedure? 53. Design an interface between 8086 CPU and two chips of 16K*8 EPROM and two chips of 32K*8RAM. Select the

starting address of EPROM suitable. The Ram Address must start at 00000h. 54. It is required to interface two chips of 32K*8 RAM with 8086, according to the following map.

ROM 1 and 2 – F0000h – FFFFFh RAM 1 and 2 – D0000h – DFFFFh RAM 3 and 4 – E0000h – EFFFFh Show the implementation of this memory system.

55. Describe the procedure of interfacing static memories with a CPU? Bring out the differences between static and dynamic RAM.

56. Interface an 8255 with 8086 so as to have port A address 00, port B address 02, port c address 01 and CWR address 03.

57. Explain the different modes of operation of 8255? 58. Interface an 4*4 hexa keyboard using two 8255 ports and write a program to read the code of a pressed key. 59. Interface 6 no.s of 7 segment LEDs using two 8255ports and write a program to display the first 6 characters of your

name. 60. Interface ADC 0808 mwith 8086 using 8255 ports. Use port A of 8255 for transferring digital data output of ADC to

the CPU and port c for control signals. Assume that an analog input is present at I/P2 of the ADC and a clock input of suitable frequency is available for ADC. Draw the schematic and write required ALP.

61. Interface a typical 8 bit DAC 0800 with 8250 and write a program to generate the following waveforms. a) Square b) triangular c) Saw tooth d) step

62. Draw a typical stepper motor interface with 8255 63. Write ALPs to rotate 200 teeth, 4 phase stepper motor as specified below

a) 5 rotations clockwise and then 5 rotations anticlockwise. b) Rotate though an angle 135 in 2 secs. c) Rotate at a speed of 10 rotations per minute.

64. Draw the discuss the internal architecture of 8253. 65. Describe the different modes of operation of 8253. 66. Design a programmable timer using 8253 and 8086. Interface 8253 at an address 0040h for counter 0 and write the

following ALPs. The 8086 and 8253 run at 6 MHz and 1.5 MHz respectively. (i) To generate a square wave of period 1 ms. (ii) To interrupt the processor after 10 ms (iii) To derive a monoshot pulse with quasistable state duration 5 ms.

67. Draw and discuss the internal architecture of 8259. 68. Explain the function of the following pins of 8259.

(i) CAS0 – CAS2 (ii) SP/EN 69. Describe an interrupt request response of a 8086 system. 70. How will you provide more than 8 input lines to an 8086 based system? 71. Explain the following terms in relation to 8259.

(i) EOI (ii) Automatic EOI (iii) Special Mask Mode (iv) Automatic rotation (v) Specific rotation (vi) Edge and level triggered mode (vii) Special fully nested mode.

72. Draw and discuss the internal architecture of 8251. 73. Explain the modem control signals of 8251.

74. Interface 8251 with 8086 at an address 80h. Initialize it in asynchronous transmit mode, with 7 bits character size, baud factor 16, one start bit, one stop bit, even parity enabled.

75. Write a program to initialize 8251 in synchronous mode with even parity, single SYNCH character, 7 bit data character. Then receive FFh bytes of data from a remote terminal and store it in the memory at address 5000h:2000h.

76. What is the advantage of DMA controlled data transfer over interrupt driven programmed controlled data transfers faster?

77. Draw and discuss the architecture of 8257? 78. Explain the functions of the following signals of 8257.

(i)HRQ (ii) ADSTB (iii) HLDA (iv) TC (v) MARK 79. What are the registers available in 8257? What are their functions? 80. Discuss the advantages of microcontroller based systems over microprocessor based systems? 81. Enlist the salient features of 8051 family of microcontroller? 82. Discuss the register set of Mcs-51 family of microcontrollers? 83. Draw and discuss the internal architecture of 8051. 84. Discuss the following signal description of 8051.

(i) ALE/PROG (ii) EA/Vpp (iii) PSEN (iv)TxD (v)RxD (vi) INT0 and INT1 (vii) T0 and T1 (viii) RD and WR

85. Draw and discuss the format and bit definitions of the following SFRs of 8051. (i)PCON (ii) TCON (iii)IE (iv)IP (v)TMOD (vi)PSW (vii)SCON

86. (i) List the timers of the 8051 and their associated registers. (ii) Describe the various modes of operation of 8051 timers. (iii) Program the 8051 timer to generate a square wave of 50% duty cycle on the p1.1 bit.

87. (i) Describe the serial communication features of 8051 (ii) Program 8051 serial port ot transfer the data serially, that is taken in through ports 0,1 and 2 continuously. (iii) Program 8051 serial port to receive serial data and send it out to port 0 in parallel form.

88. (i) Discuss the interrupt structure of 8051 (ii) Program the 8051 timer using interrupts to generate a square wave of 50% duty cycle.

89. (i) Discuss the ADC 0808 characteristics and show how to interface them to The 8051 (ii) Program the ADC chip in 8051 assembly.

90. (i) Describe the basic operation and characteristic s of DAC 0800 (ii) Program the DAC chi in 8051 assembly to generate -------- wave.

91. Show 8051 connection to 8K*8 data ROM. 92. Show 8051 connection to 8K*8 program ROM. 93. Show 8051 connection to 16K*8 data RAM. 94. Show 8031 connection to 16K*8 data RAM., 16K*8 data ROM, 16K*8 program ROM. 95. Show 8051 connection to 256K*8 external NVRAM..

SESSION CONTENTS (SESSION NO. 1 TO 18)

MICROPROCESSOR- 8086 PROGRAMMING OF 8086

INSTRUCTIONAL OBJECTIVE: To understand the architecture, programming and addressing modes of Intel 8086 PROGRAM OUTCOME: A, C, K

instructional program outcome evidence … · • muhammad ali mazidi and janice gillispie mazidi,...

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