instruction sets: ch 5 - purdue universityece495k/slides/ece495k-ch5.pdfspecial control transfers...

© 2009 Vijaykumar ECE495K Lecture Notes: Chapter 5 1

Instruction Sets: Ch 5

BitsDevices (Transistors)

CircuitsMicroarchitecture (Organization)

Instruction Set ArchitectureProg. Lang & Interfaces

AlgorithmsProblems

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H/w – s/w interface


What is an instruction set?

An instruction set specifies the machine-level (typically binary) representation of the instructions understood by a given computer

Sometimes called ISA (instruction set architecture)Instructions typically include information on:

•Type of operation to perform (opcode)•Where to get source operands•Where to put result (destination)

We will consider a specific baby instruction set: LC3


Sources and Destinations

Immediate – small constant specified in instruction itselfRegisters

•LC3 has 8 “General Purpose Registers” (GPRs)– Also some registers dedicated for special purposes

•How many bits must be used to specify a register?Memory

•LC3 has 16-bit addressability and 216 (65536) addresses•Addressable storage = 2 bytes per location ? 65536 locations = 131072 bytes = 128 kilobytes (KB)

• In memory, 1 KB = 210 B = 1024 B; 1 MB = 210 KB = 1024 KB; etc… (see Appendix E for more information)


Representing an instruction

Instruction format represents how information about instruction is mapped into bits

In LC3, all instructions are 16 bits, and first 4 bits specify opcode

•So, how many opcodes total?

Different opcodes have different formats for remaining bits•Computation, Data Transfer, Control Transfer


Computation Instructions on LC3

LC3 only implements binary ADD, logical AND and NOT

How to form a SUBTRACT?•Hint: remember definition of 2s complement…

More complex: How to form a MULTIPLY?

In general, whether an operation is in the ISA (it is done in hardware) OR is achieved as a sequence of simpler instructions (in software) depends on performance/power constraints

•But does not affect computational prowess of computer


Computation Instructions

Opcodes•ADD = 0001 ; 2 sources and 1 destination•AND = 0101 ; 2 sources and 1 destination•NOT = 1001 ; 1 source and 1 destination

Sources and destinations are registers•Except ADD and AND can optionally specify second

operand as a small constant in instruction itself– Called “immediate”, since value immediately available

Destination register may be the same as a source register•Result overwrites the old source value


Focus on ADD: 2nd source operand register

DR0 10 0 SR1 0 0 0 SR2

Used when both operands are in registers

How do we know this is ADD?

How wide are DR, SR1, and SR2 fields?

What does the “0” bit after SR1 mean?


Focus on ADD: 2nd source operand immediate

DR0 10 0 SR1 1 imm5Used when one operand is constant

What does “1” bit after SR1 mean?

Note: immediate field (5-bit wide) is sign-extended to 16 bits

How can we use an immediate source operand to set a register to 0?


Data Transfer Operations

Need separate opcodes for load (LD) and store (ST)•LD instructions have a destination register (after memory

read, copy value from MDR into dest. register)•ST instructions have a source value register (copy value

from SR into MDR, and then do memory write)

But how to specify the memory address desired?•4 possible answers: Data can be located in 4 places•Why these places? That is how programs work – ch 6-13•So 4 addressing modes


Specifying memory addresses : addressing modes (1 of 4)

Data is some known distance (offset) from the current PC + 1•Why current PC + 1 and not current PC?

•PC + 1 more readily available than PC because hardware changes PC to PC + 1 to get ready to fetch next instruction

PC-Relative Mode: LD and ST

Fig 5.6



PC-Relative Mode: LD and ST• form address by sign extending PCoffset9 to 16 bits, then

add to incremented PC; read address and write value to DR• Incremented PC is PC after the current instruction is

fetched

Driving directions:“whereever you are [PC], go x blocks further [offset]”



Data is located far away from current PC but the address of data is located at a known distance (offset) from the currentPC + 1

While PC-relative can reach only so far from the PC, indirect can (eventually) access any memory address

Indirect Mode: LDI and STI

Fig 5.7



Indirect Mode: LDI and STI•Form and fetch an address like PC-relative, treat that value

as address of actual operand and access memory again

Driving directions:“I don't know where it is but I know the address of a friend who knows where it is and the address of the friend is whereever you are [PC], go x blocks further [offset]”


Specifying memory addresses: addressing modes (3 of 4)

Data is some known distance (offset) from an address which is stored in a register

•You can load a register with one address and access many data with different offsets

Base+Offset Mode: LDR and STR (common in real systems)

Fig 5.8



Base+Offset Mode: LDR and STR (common in real systems)• Instruction specifies a register and a small constant offset;

form address by adding value in register to offset•Register can hold any address, so base+offset can access any memory address

Driving directions:“It is x blocks [offset] further from my friend's address and I can write down my friend's address [register]”



How do addresses get put into registers?•Form addresses as current PC + some offset•Use this address later

Immediate Mode: LEA (load effective address), no store•No actual memory fetch; just form address by adding

incremented PC to sign-extended offset•Copy address into DR rather than doing a memory fetch•How many addresses can one LEA specify?

Fig 5.9

Read pages 124-130


Data Transfer Instructions: Details

Opcodes•LD/ST = 0010/0011; direct mode address•LDI/STI = 1010/1011; indirect mode address•LDR/STR = 0110/0111; base+offset mode address•LEA = 1110 ; immediate mode address

Prior examples all showed loadsStores have an SR in place of DR

•Value of SR put into MDR when doing memory write• Indirect does load followed by store


Control transfer instructionsOften, we need to execute “if-else decision”

•Eg if some condition true do A else do BHow can we do this? We can write down the code for A and BCode for ACode for BBut with this, the computer will execute A and then B

•BOTH A and B will be executed - not what we want•Key reason is PC goes PC+1, +2, +3, etc•How do we make the computer skip over code?

• How do we make PC take values other than +1,+2,•How do we make the skipping based on a condition?


Control transfer instructionsControl transfer instructions change the PC to values other

than PC+1•Two types•E.g., if some condition true then other instruction else PC+1

– Conditional – decide whether or not to change PC•E.g., always go to some instruction other than PC+1

– Unconditional – always change PC

Some instructions also separately save the current PC • to be used later

How to specify the condition?How to specify the new (target) PC of the other instruction?


Control transfer instructions - ExampleIf a >= 0 add 1 to r2 else add 1 to r3add 22 from r5Code (labels for humans)

...LD r1, aBRn Label1 conditionalADD r2, r2, 1JMP Label2 unconditional

Label1: ADD r3, r3, 1Label2:

ADD r5, r5, 22...

Code (offsets for machine)

...LD r1, aBRn 3 ADD r2, r2, 1BRznp 1 ADD r3, r3, 1ADD r5, r5, 22...


Condition Code Registers

LC3 has 3 single-bit “condition code” registers (CCRs)•Z (zero), N (negative), P (positive)•Think of these as 1-bit registers•Set by all instructions that write a general purpose register

– ADD, AND, NOT, LD, LDI, LDR, LEA– The instructions write the register and condition code– Z set if written value zero, N if negative, P if positive

•Read by conditional control transfer instruction•Some other ISAs have no CCRs (only use GPRs); some

set CCRs only on certain instructions


Conditional Control Transfers (Branches)

Opcode•BR = 0000 ; target PC specified in PC-relative mode•Three bits after opcode specify whether to test N, Z, P•e.g., BRzp = 0000 011 <offset>

– In this case, set next PC to target if Z or P is set; otherwise next PC remains PC+1

– Target is sign-extended offset added to incremented PC


Focus on Conditional Branch Instruction


Unconditional Control Transfers (Jumps)

• JMP: 1100; target PC is base register+offset (what is the offset?)

•Next PC is base register + 0

• Brnzp is another way to get “unconditional” from conditional BR

• Then how is BRnzp different from JMP?•BR's offset can be only so much (how much?)•So BR can go only so far from the PC but JMP can go

anywhere•But JMP needs 2 instructions - load register first and JMP•BRznp can do with 1 instruction (if offset can fit in 9 bits)


Unconditional Control Transfers (JSR)(later in Chapter 9)

• JSR: 0100; PC-relative mode target PC• JSRR: 0100; base+offset target PC (what is the offset?)• JSR and JSRR distinguished by bit #11What is difference between JSR(R) and JMP ?

•JSR(R) save incremented PC in R7


Unconditional Control Transfers (Return)(later in Chapter 9)

Opcodes•RET: 1100 ; set PC to value stored in R7

Used to return back to sequence after a JSR(R)How could this be specified without a new opcode?


Special Control Transfers (TRAP)(later in Chapter 9)

TRAP: opcode 1111•Save incremented PC in R7•Set PC to value of memory address specified by 8-bit “trapvect” field – the high bits of address all get 0, so this loads from something in the lowest region of memory

•These typically do special system functions (e.g., interact with input/output devices, halt computer, etc.)

RTI: opcode 1000 (return from interrupt)•We’ll look at the details of traps later in semester


Example: Loop Control (1 of 2)

Add 12 integers (we know how many iterations)•Variable initialization, loops, loop iterations•R1 - address of next integer (starting at 0x3100), R2 -

number of remaining integers, R3 - running sum

See Fig 5.13 in book



0x3000 LEA r1, 011111111 (sext to x00FF=> addr = incremented PC x3001+ xFF = x3100)

0x3001 AND r3, r3, 000000x3002 AND r2, r2, 000000x3003 ADD r2, r2, 011000x3004 BRz 001010x3005 LDR r4, r1, 000000x3006 ADD r3, r3, r40x3007 ADD r1, r1, 000010x3008 ADD r2, r2, 11111 (sext to xFFFF = -1 )0x3009 Brznp 111111010 (sext xFFFA = -6 => next PC is

incremented PC - 6 = x300A - 6)



Add n positive integers (we don't know how many iterations)• Stop adding if the next value is negative (“sentinel” or guard)

See Fig 5.15 in book


LC3 Datapath

Solid arrows- data bits and hollow arrows- control signalsBus - a set of wires where exactly one value is sent at a timeMultiplexors (muxes) – choose one among many choicesSR2mux, PCmux, MARmux

Instruction cycle: Fetch (instruction), decode, address, fetch operand, execute, store results

Recall that the state machine controls instruction cycle•e.g., states could be fetch1, fetch2, decode1, decode2,

decode3, ev-addr1, ev-addr2, operand1, operand2, execute1, execute2, execute3, store-result1

Read pages 131-144


LC3 Datapath


Where are we headed? Ch 6

BitsDevices (Transistors)

CircuitsMicroarchitecture (Organization)

Prog. Lang & InterfacesAlgorithmsProblems

hard

war

eso

ftwar

e

H/w – s/w interface Instruction Set Architecture

instruction sets: ch 5 - purdue universityece495k/slides/ece495k-ch5.pdfspecial control transfers...

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