IO PROCESSING AND ACCESS SCHEMES

WHAT IS AN I/O INTERFACE?

• Interface is a hardware circuitry between the microcomputer and the I/O devices to provide all input and output transfer between them.

• These components are called interface because they interface between the computer and there peripheral device.

WHY I/O INTERFACE?

1) A conversion of signal values may be required.

CPU(Electronics) / Peripherals(Electromechanical and Electromagnet)

2) A synchronization mechanism may be needed

The data transfer rate of peripherals is usually slower than the transfer rate of the CPU

3) Data codes and formats in peripherals differ from the word format in the CPU and Memory

4) The operating modes of peripherals are different from each other

Each peripherals must be controlled so as not to disturb the operation of other peripherals connected to the CPU

MAGNETIC TAPE

MAGNETIC DISK

PRINTERKEYBOAR

D AND DISPLAY

PROCESSOR

INTERFACE

INTERFACE

INTERFACE

INTERFACE

Data

AddressControl

1 2 3 4

PORT ADDRESS

I/O VERSUS MEMORY BUS

There are three ways through which computer buses can communicate with memory and I/O. They Are

1. Use two separate buses, one for memory and other for I/O(IOP Processor)

2. use one common bus for both memory and I/O but has separate control lines for each(Isolated I/O)

3. Use one common bus for memory and I/O with common control lines(Memory mapped I/O)

MEMORY AND I/O ADDRESSING

Memory addressing capacity depends upon number of address lines in CPU

Set of all possible addresses that can be generated by CPU is called address space. CPU can directly address all the addresses of it’s address space

Eg: 8086 intel microprocessor has 20 address lines and can address 1MB of memory directly using 20 bit address bus

Thus 1mb is the address space of INTEL 8086 microprocessor

TWO METHODS OF MAPPING

There are two techniques for addressing an I/O device by CPU:

Memory mapped I/O I/O mapped I/O (Standard I/O or

Isolated I/O or port I/O)

ISOLATED I/O

Here two separate address spaces are used - one for memory location and other for I/O devices.

The I/O devices are provided dedicated address space.

Hence there are two separate control lines for memory and I/O transfer.

I/O read and I/O write lines for I/O transfer

Memory Write and Memory Read for memory transfer

Hence IN and OUT instruction deals with I/O transfer and MOV with memory transfer.

MEMORY MAPPED I/O

The technique in which CPU addresses an I/O device just like a memory location is called memory mapped I/O scheme.

In this scheme only one address space is used by CPU. Some addresses of the address space are assigned to memory location and other are assigned to I/O devices.

There is only one set of read and write lines. Hence there is no separate IN,OUT instructions. MOVE instruction can be used to accomplish both the transfer.

The instructions used to manipulate the memory can be used for I/O devices.

In memory mapped I/O the same address cannot be assigned to both memory location and I/O devices

For example : If memory locations - address from 00000 to 4FFFF , the addresses which have not been assigned for Ex: 50000,50001,50002 to memory locations can be assigned to I/O devices

IN INTEL 8086? 8086 has both memory mapped and I/O mapped I/O. The

video RAM are memory mapped where as the Keyborad , Counter and Other devices are I/O Mapped.

In I/O mapped I/O there are two set of instructions: IN and OUT to transfer data between I/O devices and accumulator ( AX,AL)

To distinguish between the memory read/write and I/O read or write M/IO signal is used. IF M/IO is high memory read and write are enabled else the I/O read and write

Two ways to specify the I/O port address are:

An 8 bit immediate((Fixed or Direct) address(here address is specified as a part of the instruction)

16 bit address located in register DX(Variable Address or Indirect)

I/O INSTRUCTIONS

MNEMONIC

MEANING FORMAT OPERATION

IN INPUT DIRECT IN AL , ADDRESS 8 BIT

PORT->AL(BYTE)

IN AX , ADDRESS 8 BIT

PORT->AX(WORD)

INPUT INDIRECT

IN AL, DX PORT->AL(BYTE)

IN AX, DX PORT->AX(WORD)

OUT OUTPUT DIRECT

OUT ADDRESS 8 BIT,AL

AL->PORT(BYTE)

OUT ADDRESS 8 BIT,AX

AX->PORT(WORD)

OUTPUT INDIRECT

OUT DX , AL AL->PORT(BYTE)

OUT DX, AX AX->PORT(WORD)

I/O ports are actually 8 bits in width. So whenever 16 bit port is accessed two consecutive 8 bit ports are actually addressed.

Hence the 32 bit I/O port is actually 4 8 bit ports.

8 bit fixed port appears on address bus connection A7-A0 with bits A15 to A8 as (00000000)2.

This means that first 256 I/O port address(00h-FFh) are accessed by both the fixed and variable I/O instruction

But any I/O address from 0100h-FFFFh can accessed by only variable I/O address

MEMORY-MAPPED I/O

FFFFF

:Memory address

space:

E0FFF

: :I/O ports

::

E0003

E0002

E0001

E0000

:::

00001

00000

Port 4095

::

I/O ports::

Port 3

Port 2

Port 1

Port 0

I/O addresses

Port 0

(16 bit port)

Port 1

(16 bit port)

MEMORY SPACE

I/O SPACE

ISOLATED I/O

FFFF Port 65 535

I/O address space

00FF Port 255

00FE Port 254

.

.

.

.

.

.

0004 Port 4

0003 Port 3

0002 Port 2

0001 Port 1

0000 Port 0 Port 0 (16 bit port)

Port 1 (16 bit port)

Page 0

I/O SPACE

EXAMPLES

To output the data FFh to a byte-wide output port at address ABh of the I/O address space, we use: MOV AL, 0FFh OUT 0BAh, AL

To input the contents of the byte-wide input port at A000h of the I/O address space into BL, we use :

MOV DX, 0A000h IN AL, DX

MOV BL, AL

EXAMPLE FOR EMULATED LED DISPLAY

#start=led_display.exe##make_bin#name "led" mov ax, 1234 out 199, ax mov ax, -5678 out 199, ax mov ax, 0x1: out 199, ax Inc ax mov dx, 64h cmp ax , dx jz l1 Jmp x1l1: hlt

I/O MAPPED I/O

ADVANTAGES

1 MB memory address space is available for use with memory.

Special Instructions for I/O operations maximize I/O performance.

Used in system where complete memory capacity is required

DISADVANTAGES

Data has to be transferred to the accumulator (any one of the internal register ) to perform arithmetic and logic operation

MEMORY MAPPED I/O

ADVANTAGES

All I/O locations are addressed in exactly the same manner as memory locations; no special repertoire of I/O instructions is therefore .Thus the overall size of the instruction set is reduced.

All arithmetic and logical operations can be performed on I/O data directly

Used in system where

memory requirement is small

DISADVANTAGES

Part of the memory address space is lost. (however, that with ported I/O systems, not all of the available I/O address space is always used.)

PC I/O MAP

( INDUSTRY STANDARD ARCHITECTURE )

( PERIPHERAL COMPONENT INTERCONNECT )

MICROPROCESSOR BASED DATA TRANSFER SCHEME

Data transfer between central computer and I/O devices takes place in the following modes:

PROGRAMMED DATA TRANSFER SCHEME

INTERRUPT CONTROL DATA TRANSFER SCHEME

CPUI/O

DEVICE

INTERFACE

I/O Bus

Data Valid

Data Accepted

Data Bus

Address Bus

I/O Read

I/O Write

22

F1

2

0

DATA REGISTER

STATUS REGISTER

HOW INTERFACE HELPS IN COMMUNICATION BETWEEN CPU AND I/O

PROGRAMMED I/O

Result of I/O instruction written in the computer program.

Each data item transfer is initiated by an instruction in the program.

This method requires constant monitoring of the peripheral by the CPU.

Hence CPU stays in the program loop until I/O unit indicates it is ready for data transfer.

Hence the processor is kept busy needlessly.

Issue Read Command To I/O Module

Read Status Of I/O Module

Check Status

Read Word From I/O Module

Write Word Into Memory

Done Yes, Next Instruction

No

CPU Memory

I/O CPU

Ready

Error Condition

Not Ready

Pro

gra

m D

riven I/O

DRAWBACK OF PROGRAMMED DATA TRANSFER SCHEME

The programmed IO transfer method is quite insufficient .

Consider a typical computer can execute the two instruction that read and check status in 1 micro second. Assume that the input device transfers its data at an average rate of 100 bytes per sec. CPU will then check the flag 10000 times between each transfer

The CPU is wasting time while checking the flag instead of doing some useful work.

This method is useful in small low speed computers or in system dedicated to monitor the device continuously

The difference in information transfer rate make this type of transfer in efficient.

INTERRUPT INITIATED I/O

Here the interface informs the computer when it is ready to transfer data uses in the interrupt facility.

Here when CPU is running a program it does not check the flag but it is momentarily interrupted from proceeding the current program and is informed of the fact that the flag is set.

CPU deviates from what it is doing to take care of I/O transfer.

After the transfer is completed it returns to the previous program.

Issue Read Command To I/O Module

Read Status Of I/O Module

Check Status

Read Word From I/O Module

Write Word Into Memory

DoneYes, Next Instruction

No

CPU Memory

I/O CPU

Ready

Error Condition

I/O CPU

Interrupt

Do Something Else

CPU I/O

Inte

rru

pt

Dri

ven

I/

O

DRAWBACKS OF INTERRUPT DRIVEN DATA TRANSFER

The IO transfer rates is limited by the speed by which the CPU can test and service a device.

Interrupt IO frees up the CPU to some extent at the expense of IO transfer rate never the less both methods have an adverse impact on CPU activity and IO transfer rate.

Hence a more efficient technique was required and then Device data transfer scheme i.e DMA data transfer was introduced.

MEMORY MAPPING IN VARIOUS OTHER

PROCESSORS

Intel 8080,zilog z80,8088 - I/O mapped I/O

Pentium processors mostly use the isolated I/O method but provides both schemes and Motorola 68000-uses memory mapped I/O

IBM pc use both memory mapped I/O and I/O mapped I/O

Nowadays, whenever a new microprocessor is released into the marketplace, it usually incorporates the ability to utilize the already (and often quite substantial) support chip and software base from the previous processor generation.

Situation applies with the Intel family, which were able to utilize the earlier i8080(86) support chips.

Intel processors support ported I/O, whereas Motorola processors support memory-mapped I/O.

It should be pointed out that memory mapping can be used with Intel processors, over and above the inbuilt ported I/O structure, assuming that the additional external decoding circuitry is provided (Hybrid)