industry trends compare and contrast harry foster chief verification scientist

Industry Trends

Compare and Contrast

Harry FosterChief Verification Scientist

HDF – HVC 2009

State of the Industry

MindlessMindless StatisticsStatistics

There are three types of lies - lies, damn lies, and statistics. -Mark Twain

HDF – HVC 2009

Myth vs. Reality?

HDF – HVC 2009

4

197929,000

Transistors8088

1982134,000

Transistors286

1985275,000

Transistors386

19891,290,000

Transistors486

19933.1M+

TransistorsPentium

19955.5M+

TransistorsPentium Pro

19977.5m+

TransistorsPentium II

19999.5M+

TransistorsPentium III

200042M

TransistorsPentium 4

2004592M

TransistorsItanium 2 (9MB cache)

20051.72B

TransistorsDual Core Itanium

2002220M

TransistorsItanium 2

Slowing Adoption of New Technology

2008 2Billion transistors

Tukwila Quad Core


Tukwila Quad Core

HDF – HVC 2009

55

Frequent Statements About the Slowing of Technology Adoption

“The problem is that Moore's Law has collapsed," he says. Coburn asserts that there has been a slowdown in the previously steady move to smaller geometries and larger wafer sizes.

Pip Coburn, Coburn VenturesDecember 15th, 2008

Source: Barron’s “Why it’s going to get a lot worse,” Eric J. Savitz. Dec. 15, 2008http://online.barrons.com/article/SB122912495865802961.html?mod=gartner

“The slowdown in process technology transitions will mean that the semiconductor industry will be driven more by economics than technology …”

“You are not seeing these geometries rise and fall off the way they did before. Rather, they are living on.”

Len Jelinek, Director and chief analyst, Semiconductor Manufacturing, for iSuppli

Source: EE Times,“ISuppli: Gear costs to derail Moore's Law in 2014," Dylan McGrath, June 16, 2009 http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=217900102

“And, the customers have slowed down or delayed their technology transitions either by leveraging their existing installed base or just by delaying their new product introduction for later.”

Eric Meurice, Chairman,

President and CEO ASML Holding N.V.Source: Q4 2008 Earnings Call. January 15, 2009http://seekingalpha.com/article/115001-asml-holding-n-v-q4-2008-earnings-call-transcript?page=-1

HDF – HVC 2009

6

Design Completion TrendsDesign Completion Share by Linewidth

0%

5%

10%

15%

20%

25%

30%

35%

40%

1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009

Per

cen

t o

f T

ota

l D

esig

n C

om

ple

tio

ns

350nm 250nm 180nm 130nm 90nm 65nm 45nm

Source: VLSI Research, Design Completions, September 2008

6

HDF – HVC 2009

7

Volume of Wafer Starts by Linewidth (300mm wafer equivalents)

0%

5%

10%

15%

20%

25%

30%

35%

40%

1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009

Per

cen

t o

f T

ota

l S

ilic

on

Dem

and

350nm 250nm 180nm 130nm 90nm 65nm 45nm

Source: VLSI Research, Silicon Demand, EDA Tech Forum June, 2009

Silicon Volume of Wafer Starts(in 300mm Wafer Equivalents)

7

HDF – HVC 2009

8

Reticle Sales TrendsReticle Revenue Share by Linewidth

0%

5%

10%

15%

20%

25%

30%

35%

40%

1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009

Per

cen

t o

f T

ota

l R

etic

le R

even

ue

Sh

are

350nm 250nm 180nm 130nm 90nm 65nm 45nm

Source: VLSI Research, Reticles, September 2008

8

HDF – HVC 2009

9

Waffer in ProductionIC Fab Capacity by Node *

IC Fab Capacity by Node (MSI) January 2004 -to- June 2008

0

50

100

150

200

Jan-04 Jul-04 Jan-05 Jul-05 Jan-06 Jul-06 Jan-07 Jul-07 Jan-08 Jul-08

IC F

ab C

apac

ity

(MS

I)

45nm 65nm 90nm 130nm 180nmSource: VLSI Research, December 15, 2008

* Note: Realized

9

HDF – HVC 2009

10

Capacity Utilization Improvement Favors 65/45nm Technology

30%

40%

50%

60%

70%

80%

90%

100%

Jan-0

8

Feb-08

Mar

-08

Apr-08

May

-08

Jun-0

8

Jul-0

8

Aug-08

Sep-0

8

Oct

-08

Nov-08

Dec-0

8

Jan-0

9

Feb-09

Mar

-09

Apr-09

Uti

liza

tio

n %

180nm

130nm

90nm

65nm

45nm

Source: Selantek Capacity Analysis, May, 2009, and October 2009

90nm,19.0%130nm,

8.6%

65nm, 14.7%

150nm, 1.8%

40/45nm, 4.9%

180nm, 7.1%

>180nm, 27.1%

Capacity by Node - April

HDF – HVC 2009

11

197929,000

Transistors8088

1982134,000

Transistors286

1985275,000

Transistors386

19891,290,000

Transistors486

19933.1M+

TransistorsPentium

19955.5M+


19977.5m+


19999.5M+


200042M


2004592M


20051.72B


2002220M


Adoption of Leading-Edge Semiconductor Technology Is at the Same Rate as in the Past

Slowing Adoption of New Technology


Tukwila Quad Core


Tukwila Quad Core

HDF – HVC 2009

Forecast

60% PCs & Cellphones

Huge growth in smartphones

2013 1/3 cells a smartphones

62.8 64.768.9

52.243.7

52.4

62.9 67.3 65.969.2 72.6 75.1

0

10

20

30

40

5060

70

80

$ B

illio

ns

1Q08 3Q08 1Q09 3Q09 1Q10 3Q10Quarter

World Semiconductor Market

Com

putin

g

Com

munication

Digital Video

ConsumerElectronics

HDF – HVC 2009

SoC Designs Dominate

HDF – HVC 2009

SOC Design & VerificationEmbedded Microprocessor Cores Trend

35%

14%

3%

11%

48%

7%

39%

6%

32%

7%

0%

5%

10%

15%

20%

25%

30%

35%

40%

45%

50%

NONE 1 2 3 4 5 or MORE

2004 2007

HDF – HVC 2009

SOC Design & VerificationEmbedded DSP Cores

20%

9%

2% 2% 3%

65%

0%

10%

20%

30%

40%

50%

60%

70%

NONE 1 2 3 4 5 or MORE

HDF – HVC 2009

What Does 45-nm Mean To Us?Challenges and Opportunities

Active and standby leakage

accounts for 65% of overall

power consumption at 45-nm

Low-power techniques are

necessary at 45-nm

45-nm offers 2X reduction in

die size or 2X increase in gate

count over 65-nm300 mm2 45-nm wafer

45-nm Wolfdale65-nm Conroe

HDF – HVC 2009

17

Myth vs. Reality?Rising Design Costs Will Limit New Applications

HDF – HVC 2009

1818

Source: Technology Research Group – EDA Database, 1986, EDA TAM, 1989 & Gartner/Dataquest 2005 Seat Count Report, Gary Smith EDA, 2008 Seat Count Analysis VLSI Research, 2008 - Transistors Produced Analysis

Transistors Produced per Electrical Engineer Nearly 4-Orders of Magnitude since 1985

HDF – HVC 2009

19

EDA Revenue Is Flat 2% of IC Revenue

EDA License & Maintenance/IC Revenue (% Percent)

0.0%

0.5%

1.0%

1.5%

2.0%

2.5%

3.0%

3.5%

4.0%

1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008

Source: Mentor Graphics, EDAC MSS & SIA WSTS

HDF – HVC 2009

2020

EDA Cost per Transistor vs Total IC Revenue per Transistor

Source: SIA, VLSI Research, Federal Reserve Note: EDA Cost Consists of EDA License and Maintenance revenue adjusted for Inflation… 1985 - 2007

1.00E-09

1.00E-08

1.00E-07

1.00E-06

1.00E-05

1.00E-04

1.00E+13 1.00E+14 1.00E+15 1.00E+16 1.00E+17 1.00E+18 1.00E+19 1.00E+20

ED

A C

os

t/T

ran

sis

tor

($)

IC R

ev

enu

e/T

ran

sis

tor

($)

1.00E-09

1.00E-08

1.00E-07

1.00E-06

1.00E-05

1.00E-04

1.00E+13 1.00E+14 1.00E+15 1.00E+16 1.00E+17 1.00E+18 1.00E+19 1.00E+20

AT

E C

ap

ita

l Co

st/

Tra

ns

isto

r ($

)

HDF – HVC 2009

SOC Design Costs Forecasted to Exceed $100 Million Within 3 Years

Impact of Design Technology on SOC Consumer Portable Implementation Cost

0

20

40

60

80

100

120

2007e 2008f 2009f 2010f 2011f 2012f

$ U

S M

illio

ns

Hardware Costs Software Costs1 2

1 Total Hardware Engineering Costs + EDA Tool Costs2 Total Software Engineering Costs + Electronic Software Design Tool CostsSource: 2007 ITRS Roadmap

Notes:

21

HDF – HVC 2009

Software Developers Outnumber Hardware Designers 2-to-1

Source: VDC - Embedded Systems Market Statistics 2007

(in 000’s)

22

HDF – HVC 2009

System Design Has Shifted to the Semiconductor Suppliers

Buses

CPU MEMHW

SWDriver

HW

SW Driver

HW

SWDriver

HW

SW Driver

OS

Middleware

Service Abstraction

Apps Apps Apps Apps AppsMuch of what was part of the end-system is now incorporated within a System-On-Chip

23

HDF – HVC 2009

24

Semiconductor Companies Are Assuming More of the System and Embedded Software

Engineering Design Responsibility

Rising Design Costs Limit New Applications

HDF – HVC 2009

Myth vs. Reality?Verification Is Keeping Up With Moore’s Law

HDF – HVC 2009

An Optimistic View of the Productivity Gap

Productivity Gap

Verify

Design

Manufacture

Time (years)

Siz

e (

# t

ran

sis

tors

)

Let’s assume…

Number of transistor doubles every 18 months (58% / yr)

Amount of logic we can design doubles every 2 years (41% / yr)

Amount of logic we can verify doubles every 2.5 years (25% per year)

HDF – HVC 2009

0

20

40

60

80

1988 1992 1996 2000 2005Ability to Verify

Ability to Design

Ability to Fabricate

DesignGap

VerificationGap

De

sig

n S

ize

in

Mil

lio

ns

of

Ga

tes

27

* Based on data from the 2003 ITRS, Collett International 2004 FV Survey, and customer surveys

The Verification Gap— Many companies still using 1990’s verification technologies

— Traditional verification techniques can’t keep up

Productivity Gap

HDF – HVC 2009

Imagine verifying a car using a directed-test approach— Requirement: Fuse will not blow under any normal operation

— Scenario 1: accelerate to 37 mph, pop in the new

Lady GaGa CD, and turn on the windshield wipers

The Verification Gap Directed Test

State-of-the-Art Verification Circa 1990

HDF – HVC 2009

Imagine verifying a car using a directed-test approach— Requirement: Fuse will not blow under any normal operation

— Scenario 1: accelerate to 37 mph, pop in the new

John Mayer CD, and turn on the windshield wipers



A Few Weeks Later. . . . .

HDF – HVC 2009

Imagine verifying a car using a directed-test approach— Requirement: Fuse will not blow under any normal operation— Scenario 714: accelerate to 48 mph, roll down the window, and

turn on the left-turn signal



HDF – HVC 2009

A purely directed-test methodology does not scale— Imagine writing a directed test for this scenario!

— Truly heroic effort—but not practical

Concurrency Challenge

HDF – HVC 2009

Today’s Concurrency Challenge

Packet-Based Design

TLP

DLLP

RetryMemory

Arbiter

Tx

Rx

FromFabric

ToPHY

FromRX

HDF – HVC 2009

What Are We Doing To Close The Gap?

Productivity Gap

Verify

Design

Manufacture

Time (years)

Siz

e (

# t

ran

sis

tors

)

HDF – HVC 2009

34

197929,000

Transistors8088

1982134,000

Transistors286

1985275,000

Transistors386

19891,290,000

Transistors486

19933.1M+

TransistorsPentium

19955.5M+


19977.5m+


19999.5M+


200042M


2004592M


20051.72B


2002220M


Moore with Less

Verification for Every Man, Woman, and Child in IndiaVerification for Every Man, Woman, and Child in India

HDF – HVC 2009

Myth vs. Reality?70% of the project effort is spent in verification….

HDF – HVC 2009

36

Design Engineers Are Becoming Verification Engineers

Source: 2007 Farwest Research IC/ASIC Functional Verification Study, Used with Permission

Verification 35%

Other14%

Design51%

Verification 46%

Design54%

HDF – HVC 2009

37

More and More Verification Cycles

HDF – HVC 2009

38

Faster Computers

0.01

0.10

1.00

10.00

100.00

1000.00

10000.00

1975 1980 1985 1990 1995 2000 2005

MIP

s

HDF – HVC 2009

39

Lots of Computers

Year # of Servers

1996 50

2006 5000+ (over 10,000 CPUs)

00

55

1010

1515

2020

2525

20012001 20022002 20032003 20042004 20052005 20062006

AMD GridAMD Grid Growth 2001-2006

(Relative to 2001 = 1.0)

Source: The AMD Grid: Enabling Grid Computing for the Corporation, August 2006

HDF – HVC 2009

So, with all this effort, what’s the results?

HDF – HVC 2009

Source: 2007 Far West Research and Mentor Graphics

41

Results2/3 Projects Miss Schedule

Designs completed on time according to project's original schedule

0.0

5.0

10.0

15.0

20.0

25.0

30.0

> +10% +10% 0 -10% -20% -30% -40% -50% > -50%

> +10%

+10%

0

-10%

-20%

-30%

-40%

-50%

> -50%

HDF – HVC 2009

6%8%

6%

1% 1% 2%

39%

17%

38%33%

20%

39%

28%

21%

42%

0%

5%

10%

15%

20%

25%

30%

35%

40%

45%

1 2 3 4 5 6 >= 7

2002 2004 2007

First Silicon Success Spins

Des

ign

s

Results77% Respins Due to Functional Bugs

Source: Collett International 2002, 2004,Farwest Research 2007 Functional Verification Study

HDF – HVC 2009

ResultsTypes of Flaws

22%27% 25%

13%

27%33%

26%

19%

5%

32%

14%

75%

11% 7%15%

11%7%

21%20%

19% 17%23%24%

77%

0%

20%

40%

60%

80%

100%

LOGIC ORFUNCTIONAL

CLOCKING TUNINGANALOGCIRCUIT

CROSSTALK-INDUCEDDELAYS,

GLITCHES

POWERCONSUMPTION

MIXED-SIGNALINTERFACE

YIELD ORRELIABILITY

TIMING – PATHTOO SLOW

FIRMWARE TIMING – PATHTOO FAST,

RACECONDITION

IR DROPS OTHER

2004 2007

Source: Collett International 2002, 2004,Farwest Research 2007 Functional Verification Study

HDF – HVC 2009

ResultsCauses of Functional Flaws


35%

41%

60%

18%15%

3%

0%

10%

20%

30%

40%

50%

60%

70%

INCORRECT orINCOMPLETE

SPECIFICATION

CHANGES INSPECIFICATION

DESIGN ERROR FLAW ININTERNALREUSED IP

FLAW INEXTERNAL IP

OTHER

HDF – HVC 2009

Myth vs. Reality?The industry is evolving its verification capabilities?

HDF – HVC 2009

0

20

40

60

80

1988 1992 1996 2000 2005Ability to Verify

Ability to Design

Ability to Fabricate

DesignGap

VerificationGap

De

sig

n S

ize

in

Mil

lio

ns

of

Ga

tes

46

* Based on data from the 2003 ITRS, Collett International 2004 FV Survey, and customer surveys

The Verification Gap— Many companies still using 1990’s verification technologies

— Traditional verification techniques can’t keep up

Productivity Gap

Ability to Adopt?

HDF – HVC 2009

Dynamic Techniques Usage


7%

9%

10%

10%

10%

21%

23%

24%

25%

26%

27%

33%

36%

37%

40%

41%

48%

51%

67%

0% 20% 40% 60% 80% 100%

PROTOTYPING WITH SPECIAL TEST CHIPS

RF SIMULATION

EMULATION (CUSTOM BUILT SYSTEMS)

ACCELERATED SIMULATION

EMULATION (COMMERCIAL SYSTEMS)

EMBEDDED CHECKERS TO TRAP ILLEGAL CONDITIONS IN THE DESIGN

TRANSACTION-LEVEL SIMULATION

TRANSISTOR-LEVEL SIMULATION

SYSTEM C SIMULATION

HARDWARE/SOFTWARE CO-VERIFICATION

ANALOG/MIXED-SIGNAL SIMULATION

C/C++ SIMULATION

FUNCTIONAL SIMULATION ABOVE RTL LEVEL

ASSERTIONS

FUNCTIONAL COVERAGE

FPGA PROTOTYPING

FUNCTIONAL SIMULATION AT GATE LEVEL

TIMING SIMULATION AT GATE LEVEL

FUNCTIONAL SIMULATION AT RTL LEVEL

HDF – HVC 2009

Static Verification Techniques Usage


1%

19%

35%

40%

43%

44%

48%

57%

62%

83%

0% 20% 40% 60% 80% 100%

Other

FORMAL PROPERTY CHECKING

DESIGN FOR VERIFICATION TECHNIQUES

EQUIVALENCE CHECKING ABOVE GATELEVEL

LINT CHECK

CODING GUIDELINES THAT AREENFORCED

CODE COVERAGE ANALYSIS

CODE REVIEWS

EQUIVALENCE CHECKING AT GATELEVEL

STATIC TIMING ANALYSIS

HDF – HVC 2009

49

Stop, time to recap. . . .

HDF – HVC 2009

Recap

1. Industry fails to mature its processes

2. Concurrency is difficult to verify

3. Throw lots of bodies at the problem

4. Throw lots of computers at it too

5. All this . . . and poor results

HDF – HVC 2009 WCR February, 2008

51

Verification Challenges Keep Coming

Low power

Clock domain crossing

Hardware/software

Network-on-chip

Multi-level verification

Multi-core verification

System verification

IP reuse (black box)

Mixed-signal (RF/analog/digital)

HDF – HVC 2009

Myth vs. Reality?The biggest bottleneck in the flow is simulation performance?

HDF – HVC 2009

Debugging is the Bottleneck

Effort Allocation of Dedicated Verification Engineers by Type of Activity

52%

34%

14%

Verif ication Debug Testbench Development Other

HDF – HVC 2009

Hey. . . how about some possibilities and prescription!

HDF – HVC 2009

SoC Designs DominateCoverage Confusion

Coverage — How big of a deal is it?

HDF – HVC 2009

Coverage ConfusionHow big of deal is it?

Not A Problem!

Not A Problem!

Coverage Adoption

48%40%

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

CODE COVERAGE FUNCTIONALCOVERAGE

ConfusedConfused Major Deal!

Major Deal!

HDF – HVC 2009

Challenges Users Want Solved3 of the top 6 changes are related to coverage!

38%

18%

15%

10%

9%

9%

2%

0% 5% 10% 15% 20% 25% 30% 35% 40%

CLOSING COVERAGE

MANAGING COVERAGEDATA

MANAGING THEVERIFICATION PROCESS

ISOLATING BUGS

TIME TO DISCOVER THENEXT BUG

CREATING FUNCTIONALCOVERAGE MODEL

Other

HDF – HVC 2009

Summary

Today I shared some common themes and insight of

what we are seeing and hearing in the industry

HDF – HVC 2009 WCR February, 2008

59

industry trends compare and contrast harry foster chief verification scientist

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